Name cleanup.

src/ifu/bpred/bpred.sv

@@ -67,14 +67,14 @@ module bpred (
   output logic             BPDirPredWrongM,           // Prediction direction is wrong
   output logic             BTBPredPCWrongM,           // Prediction target wrong
   output logic             RASPredPCWrongM,           // RAS prediction is wrong
-  output logic             PredictionInstrClassWrongM // Class prediction is wrong
+  output logic             IClassWrongM // Class prediction is wrong
   );
 
   logic [1:0] 		   BPDirPredF;
 
   logic [`XLEN-1:0] 	   BTAF, RASPCF;
   logic 		   BPPCWrongE;
-  logic 		   AnyWrongPredInstrClassD, AnyWrongPredInstrClassE;
+  logic 		   IClassWrongE;
   logic 		   BPDirPredWrongE;
   
   logic 		   BPPCSrcF;
@@ -153,7 +153,7 @@ module bpred (
           .PCNextF, .PCF, .PCD, .PCE, .PCM,
           .BTAF, .BTAD, .BTAE,
           .BTBIClassF({BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF}),
-          .PredictionInstrClassWrongM, .AnyWrongPredInstrClassE,
+          .IClassWrongM, .IClassWrongE,
           .IEUAdrE, .IEUAdrM,
           .InstrClassD({CallD, ReturnD, JumpD, BranchD}), 
           .InstrClassE({CallE, ReturnE, JumpE, BranchE}), 
@@ -163,7 +163,7 @@ module bpred (
   icpred #(`INSTR_CLASS_PRED) icpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
 		.PostSpillInstrRawF, .InstrD, .BranchD, .BranchE, .JumpD, .JumpE, .BranchM, .BranchW, .JumpM, .JumpW,
 		.CallD, .CallE, .CallM, .CallW, .ReturnD, .ReturnE, .ReturnM, .ReturnW, .BTBCallF, .BTBReturnF, .BTBJumpF,
-		.BTBBranchF, .BPCallF, .BPReturnF, .BPJumpF, .BPBranchF, .PredictionInstrClassWrongM, .AnyWrongPredInstrClassE, .WrongBPReturnD);
+		.BTBBranchF, .BPCallF, .BPReturnF, .BPJumpF, .BPBranchF, .IClassWrongM, .IClassWrongE, .WrongBPReturnD);
 
   // Part 3 RAS
   RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
@@ -200,7 +200,7 @@ module bpred (
     logic [`XLEN-1:0] 	    RASPCD, RASPCE;
     logic 					BTBPredPCWrongE, RASPredPCWrongE;	
     // performance counters
-    // 1. class         (class wrong / minstret) (PredictionInstrClassWrongM / csr)                    // Correct now
+    // 1. class         (class wrong / minstret) (IClassWrongM / csr)                    // Correct now
     // 2. target btb    (btb target wrong / class[0,1,3])  (btb target wrong / (br + j + jal)
     // 3. target ras    (ras target wrong / class[2])
     // 4. direction     (br dir wrong / class[0])

src/ifu/bpred/btb.sv

@@ -40,8 +40,8 @@ module btb #(parameter Depth = 10 ) (
   output logic [`XLEN-1:0] BTAE,
   output logic [3:0] 	   BTBIClassF, // BTB's guess at instruction class
   // update
-  input  logic 			   PredictionInstrClassWrongM, // BTB's instruction class guess was wrong
+  input  logic 			   IClassWrongM, // BTB's instruction class guess was wrong
-  input  logic             AnyWrongPredInstrClassE,
+  input  logic             IClassWrongE,
   input  logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb
   input  logic [`XLEN-1:0] IEUAdrM, // Branch/jump target address to insert into btb
   input  logic [3:0] 	   InstrClassD, // Instruction class to insert into btb
@@ -99,7 +99,7 @@ module btb #(parameter Depth = 10 ) (
     .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredF),
      .ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(BTBWrongM), .bwe2('1));
 
-  assign UpdateEn = |InstrClassM | PredictionInstrClassWrongM;
+  assign UpdateEn = |InstrClassM | IClassWrongM;
 
   flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, BTAF, BTAD);
 
@@ -108,7 +108,7 @@ module btb #(parameter Depth = 10 ) (
   // 2. BTAWrongE is used by the performance counters to track when the BTB's BTA or instruction class is wrong.
   flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, BTAD, BTAE);
   assign BTAWrongE = (BTAE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]);
-  assign BTBWrongE = BTAWrongE | AnyWrongPredInstrClassE;
+  assign BTBWrongE = BTAWrongE | IClassWrongE;
   flopenrc #(1) BTBWrongMReg(clk, reset, FlushM, ~StallM, BTBWrongE, BTBWrongM);
 
   flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);

src/ifu/bpred/icpred.sv

@@ -42,10 +42,10 @@ module icpred #(parameter INSTR_CLASS_PRED = 1)(
   output logic             ReturnD, ReturnE, ReturnM, ReturnW,
   input  logic             BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF,
   output logic             BPCallF, BPReturnF, BPJumpF, BPBranchF,
-  output logic             PredictionInstrClassWrongM, WrongBPReturnD, AnyWrongPredInstrClassE
+  output logic             IClassWrongM, WrongBPReturnD, IClassWrongE
 );
 
-  logic 		   AnyWrongPredInstrClassD;
+  logic 		   IClassWrongD;
   logic 					BPBranchD, BPJumpD, BPReturnD, BPCallD;
 
   if (!INSTR_CLASS_PRED) begin : DirectClassDecode
@@ -93,14 +93,14 @@ module icpred #(parameter INSTR_CLASS_PRED = 1)(
   flopenrc #(4) InstrClassRegW(clk, reset,  FlushM, ~StallW, {CallM, ReturnM, JumpM, BranchM}, {CallW, ReturnW, JumpW, BranchW});
 
   // branch predictor
-  flopenrc #(1) BPClassWrongRegM(clk, reset, FlushM, ~StallM, AnyWrongPredInstrClassE, PredictionInstrClassWrongM);
+  flopenrc #(1) BPClassWrongRegM(clk, reset, FlushM, ~StallM, IClassWrongE, IClassWrongM);
-  flopenrc #(1) WrongInstrClassRegE(clk, reset, FlushE, ~StallE, AnyWrongPredInstrClassD, AnyWrongPredInstrClassE);
+  flopenrc #(1) WrongInstrClassRegE(clk, reset, FlushE, ~StallE, IClassWrongD, IClassWrongE);
 
   // pipeline the predicted class
   flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, {BPCallF, BPReturnF, BPJumpF, BPBranchF}, {BPCallD, BPReturnD, BPJumpD, BPBranchD});
 
   // branch class prediction wrong.
-  assign AnyWrongPredInstrClassD = |({BPCallD, BPReturnD, BPJumpD, BPBranchD} ^ {CallD, ReturnD, JumpD, BranchD});
+  assign IClassWrongD = |({BPCallD, BPReturnD, BPJumpD, BPBranchD} ^ {CallD, ReturnD, JumpD, BranchD});
   assign WrongBPReturnD = BPReturnD ^ ReturnD;
 
 endmodule

src/ifu/ifu.sv

@@ -69,7 +69,7 @@ module ifu (
   output logic 				BPDirPredWrongM,                      // Prediction direction is wrong
   output logic 				BTBPredPCWrongM,                          // Prediction target wrong
   output logic 				RASPredPCWrongM,                          // RAS prediction is wrong
-  output logic 				PredictionInstrClassWrongM,               // Class prediction is wrong
+  output logic 				IClassWrongM,               // Class prediction is wrong
   // Faults
   input logic 				IllegalBaseInstrD,                   // Illegal non-compressed instruction
   input logic         IllegalFPUInstrD,                    // Illegal FP instruction
@@ -332,12 +332,12 @@ module ifu (
                 .BranchD, .BranchE, .JumpD, .JumpE,
                 .InstrD, .PCNextF, .PCPlus2or4F, .PC1NextF, .PCE, .PCM, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCF, .NextValidPCE,
                 .PCD, .PCLinkE, .InstrClassM, .BPWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM, .BPWrongM,
-                .BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM);
+                .BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .IClassWrongM);
 
   end else begin : bpred
     mux2 #(`XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PC1NextF));    
     assign BPWrongE = PCSrcE;
-    assign {InstrClassM, BPDirPredWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM} = '0;
+    assign {InstrClassM, BPDirPredWrongM, BTBPredPCWrongM, RASPredPCWrongM, IClassWrongM} = '0;
     assign NextValidPCE = PCE;
   end      
 

src/privileged/csr.sv

@@ -60,7 +60,7 @@ module csr #(parameter
   input  logic             BPDirPredWrongM,
   input  logic             BTBPredPCWrongM,
   input  logic             RASPredPCWrongM,
-  input  logic             PredictionInstrClassWrongM,
+  input  logic             IClassWrongM,
   input  logic             BPWrongM,                              // branch predictor is wrong
   input  logic [3:0]       InstrClassM,
   input  logic             JumpOrTakenBranchM,                               // actual instruction class
@@ -259,7 +259,7 @@ module csr #(parameter
   if (`ZICOUNTERS_SUPPORTED) begin:counters
     csrc  counters(.clk, .reset, .StallE, .StallM, .FlushM,
       .InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM,
-      .BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, .JumpOrTakenBranchM, .BPWrongM,
+      .BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .IClassWrongM, .JumpOrTakenBranchM, .BPWrongM,
       .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
       .CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
       .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,

src/privileged/csrc.sv

@@ -47,7 +47,7 @@ module csrc #(parameter
   input  logic 	            BPDirPredWrongM,
   input  logic 	            BTBPredPCWrongM,
   input  logic 	            RASPredPCWrongM,
-  input  logic 	            PredictionInstrClassWrongM,
+  input  logic 	            IClassWrongM,
   input  logic              BPWrongM,                              // branch predictor is wrong
   input  logic [3:0]        InstrClassM,
   input  logic              JumpOrTakenBranchM,                               // actual instruction class
@@ -92,7 +92,7 @@ module csrc #(parameter
     assign CounterEvent[7] = JumpOrTakenBranchM & InstrValidNotFlushedM;                // jump or taken branch instructions
     assign CounterEvent[8] = RASPredPCWrongM & InstrValidNotFlushedM;                   // return address stack wrong address
     assign CounterEvent[9] = InstrClassM[2] & InstrValidNotFlushedM;                    // return instructions
-    assign CounterEvent[10] = PredictionInstrClassWrongM & InstrValidNotFlushedM;       // instruction class predictor wrong
+    assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM;       // instruction class predictor wrong
     assign CounterEvent[11] = DCacheAccess & InstrValidNotFlushedM;                     // data cache access
     assign CounterEvent[12] = DCacheMiss;                                               // data cache miss. Miss asserted 1 cycle at start of cache miss
     assign CounterEvent[13] = ICacheAccess & InstrValidNotFlushedM;                     // instruction cache access

src/privileged/privileged.sv

@@ -49,7 +49,7 @@ module privileged (
   input  logic 		         BPDirPredWrongM,                     // branch predictor guessed wrong directoin
   input  logic 		         BTBPredPCWrongM,                         // branch predictor guessed wrong target
   input  logic 		         RASPredPCWrongM,                         // return adddress stack guessed wrong target
-  input  logic 		         PredictionInstrClassWrongM,              // branch predictor guessed wrong instruction class
+  input  logic 		         IClassWrongM,              // branch predictor guessed wrong instruction class
   input  logic             BPWrongM,                              // branch predictor is wrong
   input  logic [3:0]       InstrClassM,                               // actual instruction class
   input  logic             JumpOrTakenBranchM,                               // actual instruction class
@@ -126,7 +126,7 @@ module privileged (
     .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
     .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD,
     .BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPWrongM,
-    .PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .JumpOrTakenBranchM,
+    .IClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .JumpOrTakenBranchM,
     .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW,
     .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM,
     .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS,

src/wally/wallypipelinedcore.sv

@@ -144,7 +144,7 @@ module wallypipelinedcore (
   logic                          BPDirPredWrongM;
   logic                          BTBPredPCWrongM;
   logic                          RASPredPCWrongM;
-  logic                          PredictionInstrClassWrongM;
+  logic                          IClassWrongM;
   logic [3:0]                    InstrClassM;
   logic                          InstrAccessFaultF, HPTWInstrAccessFaultM;
   logic [2:0]                    LSUHSIZE;
@@ -177,7 +177,7 @@ module wallypipelinedcore (
     // Mem
     .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
     .InstrD, .InstrM, .PCM, .InstrClassM, .BPDirPredWrongM, .JumpOrTakenBranchM,
-    .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
+    .BTBPredPCWrongM, .RASPredPCWrongM, .IClassWrongM,
     // Faults out
     .IllegalBaseInstrD, .IllegalFPUInstrD, .InstrPageFaultF, .IllegalIEUFPUInstrD, .InstrMisalignedFaultM,
     // mmu management
@@ -290,7 +290,7 @@ module wallypipelinedcore (
       .InstrValidM, .CommittedM, .CommittedF,
       .FRegWriteM, .LoadStallD,
       .BPDirPredWrongM, .BTBPredPCWrongM, .BPWrongM,
-      .RASPredPCWrongM, .PredictionInstrClassWrongM,
+      .RASPredPCWrongM, .IClassWrongM,
       .InstrClassM, .JumpOrTakenBranchM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
       .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
       .InstrMisalignedFaultM, .IllegalIEUFPUInstrD,