RAM declaration cleanup:

pipelined/src/generic/mem/ram1p1rwbe.sv

@@ -38,7 +38,8 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
   input logic [WIDTH-1:0]         din,
   input logic                     we,
   input logic [(WIDTH-1)/8:0]     bwe,
-  output logic [WIDTH-1:0]        dout);
+  output logic [WIDTH-1:0]        dout
+);
 
   logic [WIDTH-1:0]               RAM[DEPTH-1:0];
 
@@ -64,18 +65,18 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
     integer i;
 
     // Read
-    always @(posedge clk) 
+    always_ff @(posedge clk) 
       if(ce) dout <= #1 RAM[addr];
  
     // Write divided into part for bytes and part for extra msbs
     if(WIDTH >= 8) 
-      always @(posedge clk) 
+      always_ff @(posedge clk) 
         if (ce & we) 
           for(i = 0; i < WIDTH/8; i++) 
             if(bwe[i]) RAM[addr][i*8 +: 8] <= #1 din[i*8 +: 8];
           
     if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
-      always @(posedge clk) 
+      always_ff @(posedge clk) 
         if (ce & we & bwe[WIDTH/8])
           RAM[addr][WIDTH-1:WIDTH-WIDTH%8] <= #1 din[WIDTH-1:WIDTH-WIDTH%8];
   end

pipelined/src/generic/mem/ram2p1r1wb.sv

@@ -36,12 +36,8 @@
 
 `include "wally-config.vh"
 
-module ram2p1r1wb
-  #(parameter int DEPTH = 10,
-    parameter int WIDTH = 2
-    )
-
-  (input logic              clk,
+module ram2p1r1wb #(parameter DEPTH = 10, WIDTH = 2) (
+  input  logic              clk,
   input  logic              reset,
 
   // port 1 is read only

pipelined/src/generic/mem/ram2p1rwbefix.sv

@@ -39,7 +39,8 @@ module ram2p1r1wbefix #(parameter DEPTH=128, WIDTH=256) (
   input  logic [$clog2(DEPTH)-1:0] wa2,
   input  logic                     we2,
   input  logic [(WIDTH-1)/8:0]     bwe2,
-  output logic [WIDTH-1:0]        rd1);
+  output logic [WIDTH-1:0]         rd1
+);
 
   logic [WIDTH-1:0]               mem[DEPTH-1:0];
 
@@ -53,18 +54,18 @@ module ram2p1r1wbefix #(parameter DEPTH=128, WIDTH=256) (
     integer i;
 
   // Read
-  always @(posedge clk) 
+  always_ff @(posedge clk) 
     if(ce1) rd1 <= #1 mem[ra1];
   
   // Write divided into part for bytes and part for extra msbs
   if(WIDTH >= 8) 
-    always @(posedge clk) 
+    always_ff @(posedge clk) 
       if (ce2 & we2) 
         for(i = 0; i < WIDTH/8; i++) 
           if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8];
   
   if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
-    always @(posedge clk) 
+    always_ff @(posedge clk) 
       if (ce2 & we2 & bwe2[WIDTH/8])
         mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8];