Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

pipelined/src/fpu/fdivsqrt/fdivsqrt.sv

@@ -81,6 +81,6 @@ module fdivsqrt(
     .DivBusy);
   fdivsqrtpostproc fdivsqrtpostproc(
     .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, 
-    .SqrtM, .SpecialCaseM, .remOp(Funct3E[1]),
+    .SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]),
     .QmM, .WZero, .DivSM);
 endmodule

pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv

@@ -38,7 +38,7 @@ module fdivsqrtpostproc(
   input  logic  Firstun,
   input  logic SqrtM,
   input  logic SpecialCaseM,
-  input  logic remOp,
+  input  logic RemOp,
   output logic [`DIVb:0] QmM, 
   output logic WZero,
   output logic DivSM