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Moved all bus logic outside the dcache. Still needs cleanup.

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This commit is contained in:
Ross Thompson 2021-12-28 11:18:47 -06:00
parent 74d636cb53
commit 243728d089
1 changed files with 7 additions and 18 deletions
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25
wally-pipelined/src/lsu/lsu.sv
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@ -470,6 +470,9 @@ module lsu
case(BusCurrState) case(BusCurrState)
STATE_BUS_READY: begin STATE_BUS_READY: begin
if(IgnoreRequest) begin
BusNextState = STATE_BUS_READY;
end else
// uncache write // uncache write
if(MemRWMtoDCache[0] & ~CacheableMtoDCache) begin if(MemRWMtoDCache[0] & ~CacheableMtoDCache) begin
BusNextState = STATE_BUS_UNCACHED_WRITE; BusNextState = STATE_BUS_UNCACHED_WRITE;
@ -537,39 +540,25 @@ module lsu
CommittedMfromBus = 1'b1; CommittedMfromBus = 1'b1;
if (FetchCountFlag & DCfromAHBAck) begin if (FetchCountFlag & DCfromAHBAck) begin
BusNextState = STATE_BUS_FETCH_DONE; BusNextState = STATE_BUS_READY;
BUSACK = 1'b1;
end else begin end else begin
BusNextState = STATE_BUS_FETCH_WDV; BusNextState = STATE_BUS_FETCH_WDV;
end end
end end
STATE_BUS_FETCH_DONE: begin
BusStall = 1'b1;
CntReset = 1'b1;
CommittedMfromBus = 1'b1;
BusNextState = STATE_BUS_READY;
BUSACK = 1'b1;
end
STATE_BUS_EVICT_DIRTY: begin STATE_BUS_EVICT_DIRTY: begin
BusStall = 1'b1; BusStall = 1'b1;
PreCntEn = 1'b1; PreCntEn = 1'b1;
DCtoAHBWriteM = 1'b1; DCtoAHBWriteM = 1'b1;
CommittedMfromBus = 1'b1; CommittedMfromBus = 1'b1;
if(FetchCountFlag & DCfromAHBAck) begin if(FetchCountFlag & DCfromAHBAck) begin
BusNextState = STATE_BUS_WRITE_CACHE_BLOCK; BusNextState = STATE_BUS_READY;
BUSACK = 1'b1;
end else begin end else begin
BusNextState = STATE_BUS_EVICT_DIRTY; BusNextState = STATE_BUS_EVICT_DIRTY;
end end
end end
STATE_BUS_WRITE_CACHE_BLOCK: begin
BusStall = 1'b1;
CntReset = 1'b1;
CommittedMfromBus = 1'b1;
BusNextState = STATE_BUS_READY;
BUSACK = 1'b1;
end
endcase endcase
end end