forked from Github_Repos/cvw
small signs of life on new interrupt spoofing
This commit is contained in:
bbracker
parent
a09360f207
commit
23406d0926
@ -2,11 +2,14 @@ onerror {resume}
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quietly WaveActivateNextPane {} 0
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/reset_ext
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add wave -noupdate -expand -group Testbench /testbench/reset_ext
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add wave -noupdate -radix unsigned /testbench/InstrCountW
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add wave -noupdate -expand -group Testbench -radix unsigned /testbench/InstrCountW
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add wave -noupdate -radix unsigned /testbench/AttemptedInstructionCount
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add wave -noupdate -expand -group Testbench -radix unsigned /testbench/AttemptedInstructionCount
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add wave -noupdate /testbench/dut/core/SATP_REGW
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add wave -noupdate -expand -group Testbench -radix decimal /testbench/interruptInstrCount
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add wave -noupdate /testbench/dut/core/IllegalFPUInstrD
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add wave -noupdate -expand -group Testbench /testbench/interruptCauseVal
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add wave -noupdate -expand -group Testbench /testbench/interruptEpcVal
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add wave -noupdate -expand -group Testbench /testbench/interruptTVal
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add wave -noupdate -expand -group Testbench /testbench/interruptDesc
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/CSRWritePendingDEM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/CSRWritePendingDEM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
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@ -51,21 +54,21 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/ExpectedPCE
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add wave -noupdate -group {Execution Stage} /testbench/ExpectedPCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/MepcExpected
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add wave -noupdate -group {Execution Stage} /testbench/MepcExpected
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
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add wave -noupdate -expand -group {Execution Stage} /testbench/textE
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add wave -noupdate -group {Execution Stage} /testbench/textE
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add wave -noupdate -expand -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
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add wave -noupdate -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
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add wave -noupdate -expand -group {Memory Stage} /testbench/checkInstrM
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add wave -noupdate -group {Memory Stage} /testbench/checkInstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
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add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM
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add wave -noupdate -group {Memory Stage} /testbench/ExpectedPCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
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add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/textM
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add wave -noupdate -group {Memory Stage} /testbench/textM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
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add wave -noupdate -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
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add wave -noupdate -group {WriteBack stage} /testbench/checkInstrW
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add wave -noupdate -group {WriteBack stage} /testbench/checkInstrW
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add wave -noupdate -group {WriteBack stage} /testbench/InstrValidW
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add wave -noupdate -group {WriteBack stage} /testbench/InstrValidW
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add wave -noupdate -group {WriteBack stage} /testbench/PCW
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add wave -noupdate -group {WriteBack stage} /testbench/PCW
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@ -84,7 +87,7 @@ add wave -noupdate -group Bpred -group {branch update selection inputs} /testben
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add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
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add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
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add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
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add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
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add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
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add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
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add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
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add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 17 -radix binary}} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
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add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
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add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
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add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
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add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
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add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
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add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
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@ -193,204 +196,203 @@ add wave -noupdate -group ifu -expand -group icache -expand -group memory /testb
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add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
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add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
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add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF
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add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF
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add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
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add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrM
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add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUPAdrM
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add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUPAdrM
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add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState
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add wave -noupdate -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
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add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall
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add wave -noupdate -group lsu /testbench/dut/core/lsu/InterlockStall
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
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add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
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add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
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add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM
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add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/busdp/SelUncachedAdr
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add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/busdp/SelUncachedAdr
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add wave -noupdate -expand -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState
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add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState
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add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/BusStall
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add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall
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add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusRead
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add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusRead
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add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusWrite
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add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusWrite
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add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusAdr
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add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusAdr
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add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusAck
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add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusAck
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add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusHRDATA
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add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHRDATA
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add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusHWDATA
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add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHWDATA
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add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
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add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/SelReplayCPURequest
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
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add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/RAdrD}
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add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/RAdrD}
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add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
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add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
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add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
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add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
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add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
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add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
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add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay
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add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag
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add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData[69]}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData[69]}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag
|
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
|
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay
|
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirty
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/RW
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/RW
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/Atomic
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/Atomic
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/FinalWriteDataM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/FinalWriteDataM
|
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
|
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_D
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_D
|
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_A
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_A
|
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_U
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_U
|
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_X
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_X
|
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_W
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_W
|
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_R
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_R
|
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_V
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_V
|
add wave -noupdate -group lsu -group dtlb -expand -group Status -color Maroon /testbench/dut/core/lsu/dmmu/dmmu/DAPageFault
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status -color Maroon /testbench/dut/core/lsu/dmmu/dmmu/DAPageFault
|
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/ImproperPrivilege
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/ImproperPrivilege
|
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/UpperBitsUnequalPageFault
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/UpperBitsUnequalPageFault
|
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Misaligned
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Misaligned
|
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidRead
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidRead
|
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidWrite
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidWrite
|
add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
|
add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
|
add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
|
add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/WalkerState
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/WalkerState
|
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PCF
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PCF
|
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE
|
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr
|
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE
|
add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/ITLBMissF
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/ITLBMissF
|
add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/ITLBMissOrDAFaultF
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/ITLBMissOrDAFaultF
|
add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF
|
add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM
|
|
||||||
add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/BusState
|
add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/BusState
|
||||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/NextBusState
|
add wave -noupdate -group AHB /testbench/dut/core/ebu/NextBusState
|
||||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/AtomicMaskedM
|
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/AtomicMaskedM
|
||||||
@ -434,7 +436,6 @@ add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/GPIOIntr
|
|||||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADPLIC
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADPLIC
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HRESPPLIC
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HRESPPLIC
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADYPLIC
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADYPLIC
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/ExtIntM
|
|
||||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HCLK
|
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HCLK
|
||||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HSELGPIO
|
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HSELGPIO
|
||||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HADDR
|
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HADDR
|
||||||
@ -515,23 +516,9 @@ add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I
|
|||||||
add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
|
add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
|
||||||
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
|
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
|
||||||
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
|
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
|
||||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD
|
|
||||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrD
|
|
||||||
add wave -noupdate /testbench/dut/core/ifu/InstrRawD
|
|
||||||
add wave -noupdate /testbench/dut/core/ifu/PostSpillInstrRawF
|
|
||||||
add wave -noupdate /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0
|
|
||||||
add wave -noupdate /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillSaveF
|
|
||||||
add wave -noupdate /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState
|
|
||||||
add wave -noupdate /testbench/dut/core/ifu/SpillSupport/spillsupport/TakeSpillF
|
|
||||||
add wave -noupdate /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF
|
|
||||||
add wave -noupdate /testbench/dut/core/ifu/SpillSupport/spillsupport/IFUCacheBusStallF
|
|
||||||
add wave -noupdate -color Yellow /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DAPageFault
|
|
||||||
add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/ITLBMissF
|
|
||||||
add wave -noupdate /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/WriteAccess
|
|
||||||
add wave -noupdate /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/TLBPageFault
|
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 7} {62997113 ns} 1} {{Cursor 5} {65676608 ns} 1} {{Cursor 3} {65665947 ns} 1} {{Cursor 4} {65431218 ns} 0}
|
WaveRestoreCursors {{Cursor 4} {2240751 ns} 0}
|
||||||
quietly wave cursor active 4
|
quietly wave cursor active 1
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 314
|
configure wave -valuecolwidth 314
|
||||||
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
||||||
@ -546,4 +533,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {65430777 ns} {65431305 ns}
|
WaveRestoreZoom {2240730 ns} {2240764 ns}
|
||||||
|
|||||||
@ -40,84 +40,40 @@ module testbench;
|
|||||||
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
/////////////////////////////////// CONFIG ////////////////////////////////////
|
/////////////////////////////////// CONFIG ////////////////////////////////////
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
// Recommend setting all of these in do script using -G option
|
// Recommend setting all of these in 'do' script using -G option
|
||||||
parameter INSTR_LIMIT = 0; // # of instructions at which to stop
|
parameter INSTR_LIMIT = 0; // # of instructions at which to stop
|
||||||
parameter INSTR_WAVEON = 0; // # of instructions at which to turn on waves in graphical sim
|
parameter INSTR_WAVEON = 0; // # of instructions at which to turn on waves in graphical sim
|
||||||
parameter CHECKPOINT = 0;
|
parameter CHECKPOINT = 0;
|
||||||
parameter RISCV_DIR = "/opt/riscv";
|
parameter RISCV_DIR = "/opt/riscv";
|
||||||
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
|
||||||
////////////////////////////////// HARDWARE ///////////////////////////////////
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
|
||||||
logic clk, reset_ext;
|
|
||||||
logic reset;
|
|
||||||
initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
|
|
||||||
always begin clk <= 1; # 5; clk <= 0; # 5; end
|
|
||||||
|
|
||||||
logic [`AHBW-1:0] HRDATAEXT;
|
|
||||||
logic HREADYEXT, HRESPEXT;
|
|
||||||
logic HCLK, HRESETn;
|
|
||||||
logic HREADY;
|
|
||||||
logic HSELEXT;
|
|
||||||
logic [31:0] HADDR;
|
|
||||||
logic [`AHBW-1:0] HWDATA;
|
|
||||||
logic HWRITE;
|
|
||||||
logic [2:0] HSIZE;
|
|
||||||
logic [2:0] HBURST;
|
|
||||||
logic [3:0] HPROT;
|
|
||||||
logic [1:0] HTRANS;
|
|
||||||
logic HMASTLOCK;
|
|
||||||
logic [31:0] GPIOPinsIn;
|
|
||||||
logic [31:0] GPIOPinsOut, GPIOPinsEn;
|
|
||||||
logic UARTSin, UARTSout;
|
|
||||||
|
|
||||||
logic SDCCLK;
|
|
||||||
logic SDCCmdIn;
|
|
||||||
logic SDCCmdOut;
|
|
||||||
logic SDCCmdOE;
|
|
||||||
logic [3:0] SDCDatIn;
|
|
||||||
|
|
||||||
assign GPIOPinsIn = 0;
|
|
||||||
assign UARTSin = 1;
|
|
||||||
wallypipelinedsoc dut(.clk, .reset, .reset_ext,
|
|
||||||
.HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK,
|
|
||||||
.HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
|
||||||
.HTRANS, .HMASTLOCK,
|
|
||||||
.TIMECLK('0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
|
|
||||||
.UARTSin, .UARTSout,
|
|
||||||
.SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn);
|
|
||||||
|
|
||||||
|
|
||||||
// Write Back stage signals not needed by Wally itself
|
|
||||||
parameter nop = 'h13;
|
|
||||||
logic [`XLEN-1:0] PCW;
|
|
||||||
logic [31:0] InstrW;
|
|
||||||
logic InstrValidW;
|
|
||||||
logic [`XLEN-1:0] IEUAdrW, WriteDataW;
|
|
||||||
logic TrapW;
|
|
||||||
`define FLUSHW dut.core.FlushW
|
|
||||||
`define STALLW dut.core.StallW
|
|
||||||
flopenrc #(`XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.ifu.PCM, PCW);
|
|
||||||
flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.core.ifu.InstrM, InstrW);
|
|
||||||
flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW);
|
|
||||||
flopenrc #(`XLEN) IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW);
|
|
||||||
flopenrc #(`XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW);
|
|
||||||
flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW);
|
|
||||||
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
|
||||||
//////////////////////// Signals & Macro DECLARATIONS /////////////////////////
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
|
||||||
// Testbench Core
|
|
||||||
|
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
//////////////////////// SIGNAL / VAR / MACRO DECLARATIONS /////////////////////////
|
||||||
|
////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// ========== Testbench Core ==========
|
||||||
integer warningCount = 0;
|
integer warningCount = 0;
|
||||||
integer errorCount = 0;
|
integer errorCount = 0;
|
||||||
integer fault;
|
integer fault;
|
||||||
string ProgramAddrMapFile, ProgramLabelMapFile;
|
string ProgramAddrMapFile, ProgramLabelMapFile;
|
||||||
|
// ========== Initialization ==========
|
||||||
string testvectorDir;
|
string testvectorDir;
|
||||||
string linuxImageDir;
|
string linuxImageDir;
|
||||||
// Checkpointing
|
integer memFile;
|
||||||
|
integer readResult;
|
||||||
|
// ========== Checkpointing ==========
|
||||||
string checkpointDir;
|
string checkpointDir;
|
||||||
logic [1:0] initPriv;
|
logic [1:0] initPriv;
|
||||||
// Signals used to parse the trace file
|
// ========== Trace parsing & checking ==========
|
||||||
|
integer garbageInt;
|
||||||
|
string garbageString;
|
||||||
`define DECLARE_TRACE_SCANNER_SIGNALS(STAGE) \
|
`define DECLARE_TRACE_SCANNER_SIGNALS(STAGE) \
|
||||||
integer traceFile``STAGE; \
|
integer traceFile``STAGE; \
|
||||||
integer matchCount``STAGE; \
|
integer matchCount``STAGE; \
|
||||||
@ -141,14 +97,12 @@ module testbench;
|
|||||||
logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0];
|
logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0];
|
||||||
`DECLARE_TRACE_SCANNER_SIGNALS(E)
|
`DECLARE_TRACE_SCANNER_SIGNALS(E)
|
||||||
`DECLARE_TRACE_SCANNER_SIGNALS(M)
|
`DECLARE_TRACE_SCANNER_SIGNALS(M)
|
||||||
integer NextMIPexpected, NextSIPexpected;
|
// M-stage expected values
|
||||||
integer NextMepcExpected;
|
|
||||||
// Memory stage expected values from trace
|
|
||||||
logic checkInstrM;
|
logic checkInstrM;
|
||||||
integer MIPexpected, SIPexpected;
|
integer MIPexpected, SIPexpected;
|
||||||
string name;
|
string name;
|
||||||
logic [`AHBW-1:0] readDataExpected;
|
logic [`AHBW-1:0] readDataExpected;
|
||||||
// Write back stage expected values from trace
|
// W-stage expected values
|
||||||
logic checkInstrW;
|
logic checkInstrW;
|
||||||
logic [`XLEN-1:0] ExpectedPCW;
|
logic [`XLEN-1:0] ExpectedPCW;
|
||||||
logic [31:0] ExpectedInstrW;
|
logic [31:0] ExpectedInstrW;
|
||||||
@ -162,35 +116,33 @@ module testbench;
|
|||||||
string ExpectedCSRArrayW[10:0];
|
string ExpectedCSRArrayW[10:0];
|
||||||
logic [`XLEN-1:0] ExpectedCSRArrayValueW[10:0];
|
logic [`XLEN-1:0] ExpectedCSRArrayValueW[10:0];
|
||||||
logic [`XLEN-1:0] ExpectedIntType;
|
logic [`XLEN-1:0] ExpectedIntType;
|
||||||
logic forcedInterrupt;
|
|
||||||
integer NumCSRMIndex;
|
|
||||||
integer NumCSRWIndex;
|
integer NumCSRWIndex;
|
||||||
integer NumCSRPostWIndex;
|
integer NumCSRPostWIndex;
|
||||||
logic [`XLEN-1:0] InstrCountW;
|
logic [`XLEN-1:0] InstrCountW;
|
||||||
integer RequestDelayedMIP;
|
// ========== Interrupt parsing & spoofing ==========
|
||||||
integer RequestDelayedSIP;
|
string interrupt;
|
||||||
integer ForceMIPFuture;
|
string interruptLine;
|
||||||
integer CSRIndex;
|
integer interruptFile;
|
||||||
longint MepcExpected;
|
integer interruptInstrCount;
|
||||||
integer CheckMIPFutureE;
|
integer interruptHartVal;
|
||||||
integer CheckMIPFutureM;
|
integer interruptAsyncVal;
|
||||||
integer CheckSIPFutureE;
|
longint interruptCauseVal;
|
||||||
integer CheckSIPFutureM;
|
longint interruptEpcVal;
|
||||||
|
longint interruptTVal;
|
||||||
|
string interruptDesc;
|
||||||
|
integer NextMIPexpected, NextSIPexpected;
|
||||||
|
integer NextMepcExpected;
|
||||||
logic [`XLEN-1:0] AttemptedInstructionCount;
|
logic [`XLEN-1:0] AttemptedInstructionCount;
|
||||||
// Useful Aliases
|
// ========== Misc Aliases ==========
|
||||||
`define RF dut.core.ieu.dp.regf.rf
|
`define RF dut.core.ieu.dp.regf.rf
|
||||||
`define PC dut.core.ifu.pcreg.q
|
`define PC dut.core.ifu.pcreg.q
|
||||||
|
`define PRIV dut.core.priv.priv.privmodereg.q
|
||||||
`define CSR_BASE dut.core.priv.priv.csr
|
`define CSR_BASE dut.core.priv.priv.csr
|
||||||
`define HPMCOUNTER `CSR_BASE.counters.counters.HPMCOUNTER_REGW
|
`define HPMCOUNTER `CSR_BASE.counters.counters.HPMCOUNTER_REGW
|
||||||
`define PMP_BASE `CSR_BASE.csrm.pmp
|
|
||||||
`define PMPCFG genblk2.PMPCFGreg.q
|
|
||||||
`define PMPADDR PMPADDRreg.q
|
|
||||||
`define MEDELEG `CSR_BASE.csrm.deleg.MEDELEGreg.q
|
`define MEDELEG `CSR_BASE.csrm.deleg.MEDELEGreg.q
|
||||||
`define MIDELEG `CSR_BASE.csrm.deleg.MIDELEGreg.q
|
`define MIDELEG `CSR_BASE.csrm.deleg.MIDELEGreg.q
|
||||||
`define MIE `CSR_BASE.csri.MIE_REGW
|
`define MIE `CSR_BASE.csri.IE_REGW
|
||||||
`define MIP `CSR_BASE.csri.MIP_REGW
|
`define MIP `CSR_BASE.csri.IP_REGW_writeable
|
||||||
`define SIE `CSR_BASE.csri.SIE_REGW
|
|
||||||
`define SIP `CSR_BASE.csri.SIP_REGW
|
|
||||||
`define MCAUSE `CSR_BASE.csrm.MCAUSEreg.q
|
`define MCAUSE `CSR_BASE.csrm.MCAUSEreg.q
|
||||||
`define SCAUSE `CSR_BASE.csrs.csrs.SCAUSEreg.q
|
`define SCAUSE `CSR_BASE.csrs.csrs.SCAUSEreg.q
|
||||||
`define MEPC `CSR_BASE.csrm.MEPCreg.q
|
`define MEPC `CSR_BASE.csrm.MEPCreg.q
|
||||||
@ -202,6 +154,7 @@ module testbench;
|
|||||||
`define MTVEC `CSR_BASE.csrm.MTVECreg.q
|
`define MTVEC `CSR_BASE.csrm.MTVECreg.q
|
||||||
`define STVEC `CSR_BASE.csrs.csrs.STVECreg.q
|
`define STVEC `CSR_BASE.csrs.csrs.STVECreg.q
|
||||||
`define SATP `CSR_BASE.csrs.csrs.genblk1.SATPreg.q
|
`define SATP `CSR_BASE.csrs.csrs.genblk1.SATPreg.q
|
||||||
|
`define INSTRET `CSR_BASE.counters.counters.HPMCOUNTER_REGW[2]
|
||||||
`define MSTATUS `CSR_BASE.csrsr.MSTATUS_REGW
|
`define MSTATUS `CSR_BASE.csrsr.MSTATUS_REGW
|
||||||
`define SSTATUS `CSR_BASE.csrsr.SSTATUS_REGW
|
`define SSTATUS `CSR_BASE.csrsr.SSTATUS_REGW
|
||||||
`define STATUS_TSR `CSR_BASE.csrsr.STATUS_TSR_INT
|
`define STATUS_TSR `CSR_BASE.csrsr.STATUS_TSR_INT
|
||||||
@ -219,35 +172,123 @@ module testbench;
|
|||||||
`define STATUS_MIE `CSR_BASE.csrsr.STATUS_MIE
|
`define STATUS_MIE `CSR_BASE.csrsr.STATUS_MIE
|
||||||
`define STATUS_SIE `CSR_BASE.csrsr.STATUS_SIE
|
`define STATUS_SIE `CSR_BASE.csrsr.STATUS_SIE
|
||||||
`define STATUS_UIE `CSR_BASE.csrsr.STATUS_UIE
|
`define STATUS_UIE `CSR_BASE.csrsr.STATUS_UIE
|
||||||
`define PRIV dut.core.priv.priv.privmodereg.q
|
`define UART dut.uncore.uart.uart.u
|
||||||
`define INSTRET dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]
|
`define UART_IER `UART.IER
|
||||||
`define UART dut.uncore.uart.uart.u
|
`define UART_LCR `UART.LCR
|
||||||
`define UART_IER `UART.IER
|
`define UART_MCR `UART.MCR
|
||||||
`define UART_LCR `UART.LCR
|
`define UART_SCR `UART.SCR
|
||||||
`define UART_MCR `UART.MCR
|
`define PLIC dut.uncore.plic.plic
|
||||||
`define UART_SCR `UART.SCR
|
|
||||||
`define PLIC dut.uncore.plic.plic
|
|
||||||
`define PLIC_INT_PRIORITY `PLIC.intPriority
|
`define PLIC_INT_PRIORITY `PLIC.intPriority
|
||||||
`define PLIC_INT_ENABLE `PLIC.intEn
|
`define PLIC_INT_ENABLE `PLIC.intEn
|
||||||
`define PLIC_THRESHOLD `PLIC.intThreshold
|
`define PLIC_THRESHOLD `PLIC.intThreshold
|
||||||
// Common Macros
|
`define PCM dut.core.ifu.PCM
|
||||||
`define checkCSR(CSR) \
|
// ========== COMMON MACROS ==========
|
||||||
|
// Needed for initialization and core
|
||||||
|
`define SCAN_NEW_INTERRUPT \
|
||||||
begin \
|
begin \
|
||||||
if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \
|
$fgets(interruptLine, interruptFile); \
|
||||||
$display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, InstrCountW, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \
|
//$display("Time %t, interruptLine %x", $time, interruptLine); \
|
||||||
if(`DEBUG_TRACE >= 3) fault = 1; \
|
$fgets(interruptLine, interruptFile); \
|
||||||
end \
|
$sscanf(interruptLine, "%d", interruptInstrCount); \
|
||||||
end
|
$fgets(interruptLine, interruptFile); \
|
||||||
`define checkEQ(NAME, VAL, EXPECTED) \
|
$sscanf(interruptLine, "%d", interruptHartVal); \
|
||||||
if(VAL != EXPECTED) begin \
|
$fgets(interruptLine, interruptFile); \
|
||||||
$display("%tns, %d instrs: %s %x differs from expected %x", $time, InstrCountW, NAME, VAL, EXPECTED); \
|
$sscanf(interruptLine, "%d", interruptAsyncVal); \
|
||||||
if ((NAME == "PCW") | (`DEBUG_TRACE >= 2)) fault = 1; \
|
$fgets(interruptLine, interruptFile); \
|
||||||
end
|
$sscanf(interruptLine, "%x", interruptCauseVal); \
|
||||||
|
$fgets(interruptLine, interruptFile); \
|
||||||
|
$sscanf(interruptLine, "%x", interruptEpcVal); \
|
||||||
|
$fgets(interruptLine, interruptFile); \
|
||||||
|
$sscanf(interruptLine, "%x", interruptTVal); \
|
||||||
|
$fgets(interruptLine, interruptFile); \
|
||||||
|
$sscanf(interruptLine, "%s", interruptDesc); \
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
////////////////////////////////// HARDWARE ///////////////////////////////////
|
||||||
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Clock and Reset
|
||||||
|
logic clk, reset_ext;
|
||||||
|
logic reset;
|
||||||
|
initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
|
||||||
|
always begin clk <= 1; # 5; clk <= 0; # 5; end
|
||||||
|
// Wally Interface
|
||||||
|
logic [`AHBW-1:0] HRDATAEXT;
|
||||||
|
logic HREADYEXT, HRESPEXT;
|
||||||
|
logic HCLK, HRESETn;
|
||||||
|
logic HREADY;
|
||||||
|
logic HSELEXT;
|
||||||
|
logic [31:0] HADDR;
|
||||||
|
logic [`AHBW-1:0] HWDATA;
|
||||||
|
logic HWRITE;
|
||||||
|
logic [2:0] HSIZE;
|
||||||
|
logic [2:0] HBURST;
|
||||||
|
logic [3:0] HPROT;
|
||||||
|
logic [1:0] HTRANS;
|
||||||
|
logic HMASTLOCK;
|
||||||
|
logic [31:0] GPIOPinsIn;
|
||||||
|
logic [31:0] GPIOPinsOut, GPIOPinsEn;
|
||||||
|
logic UARTSin, UARTSout;
|
||||||
|
|
||||||
|
// FPGA-specific Stuff
|
||||||
|
logic SDCCLK;
|
||||||
|
logic SDCCmdIn;
|
||||||
|
logic SDCCmdOut;
|
||||||
|
logic SDCCmdOE;
|
||||||
|
logic [3:0] SDCDatIn;
|
||||||
|
|
||||||
|
// Hardwire UART, GPIO pins
|
||||||
|
assign GPIOPinsIn = 0;
|
||||||
|
assign UARTSin = 1;
|
||||||
|
|
||||||
|
// Wally
|
||||||
|
wallypipelinedsoc dut(.clk, .reset, .reset_ext,
|
||||||
|
.HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK,
|
||||||
|
.HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
||||||
|
.HTRANS, .HMASTLOCK,
|
||||||
|
.TIMECLK('0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
|
||||||
|
.UARTSin, .UARTSout,
|
||||||
|
.SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn);
|
||||||
|
|
||||||
|
// W-stage hardware not needed by Wally itself
|
||||||
|
parameter nop = 'h13;
|
||||||
|
logic [`XLEN-1:0] PCW;
|
||||||
|
logic [31:0] InstrW;
|
||||||
|
logic InstrValidW;
|
||||||
|
logic [`XLEN-1:0] IEUAdrW, WriteDataW;
|
||||||
|
logic TrapW;
|
||||||
|
`define FLUSHW dut.core.FlushW
|
||||||
|
`define STALLW dut.core.StallW
|
||||||
|
flopenrc #(`XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, `PCM, PCW);
|
||||||
|
flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.core.ifu.InstrM, InstrW);
|
||||||
|
flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW);
|
||||||
|
flopenrc #(`XLEN) IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW);
|
||||||
|
flopenrc #(`XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW);
|
||||||
|
flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW);
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
/////////////////////////////// INITIALIZATION ////////////////////////////////
|
/////////////////////////////// INITIALIZATION ////////////////////////////////
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
// Checkpoint initializations
|
// ========== CHECKPOINTING ==========
|
||||||
`define MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \
|
`define MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \
|
||||||
logic DIM init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \
|
logic DIM init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \
|
||||||
initial begin \
|
initial begin \
|
||||||
@ -280,21 +321,6 @@ module testbench;
|
|||||||
end \
|
end \
|
||||||
end \
|
end \
|
||||||
end
|
end
|
||||||
// For the annoying case where the pathname to the array elements includes
|
|
||||||
// a "genblk<i>" in the signal name
|
|
||||||
`define INIT_CHECKPOINT_GENBLK_ARRAY(SIGNAL_BASE,SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \
|
|
||||||
`MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \
|
|
||||||
for (i=ARRAY_MIN; i<ARRAY_MAX+1; i=i+1) begin \
|
|
||||||
initial begin \
|
|
||||||
if (CHECKPOINT!=0) begin \
|
|
||||||
force `SIGNAL_BASE[i].`SIGNAL = init``SIGNAL[i]; \
|
|
||||||
while (reset!==1) #1; \
|
|
||||||
while (reset!==0) #1; \
|
|
||||||
#1; \
|
|
||||||
release `SIGNAL_BASE[i].`SIGNAL; \
|
|
||||||
end \
|
|
||||||
end \
|
|
||||||
end
|
|
||||||
|
|
||||||
// Note that dimension usage is very intentional here.
|
// Note that dimension usage is very intentional here.
|
||||||
// We are dancing around (un)packed type requirements.
|
// We are dancing around (un)packed type requirements.
|
||||||
@ -318,8 +344,6 @@ module testbench;
|
|||||||
`INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]);
|
`INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]);
|
||||||
`INIT_CHECKPOINT_VAL(MIE, [11:0]);
|
`INIT_CHECKPOINT_VAL(MIE, [11:0]);
|
||||||
`INIT_CHECKPOINT_VAL(MIP, [11:0]);
|
`INIT_CHECKPOINT_VAL(MIP, [11:0]);
|
||||||
`INIT_CHECKPOINT_VAL(SIE, [11:0]);
|
|
||||||
`INIT_CHECKPOINT_VAL(SIP, [11:0]);
|
|
||||||
`INIT_CHECKPOINT_VAL(MCAUSE, [`XLEN-1:0]);
|
`INIT_CHECKPOINT_VAL(MCAUSE, [`XLEN-1:0]);
|
||||||
`INIT_CHECKPOINT_VAL(SCAUSE, [`XLEN-1:0]);
|
`INIT_CHECKPOINT_VAL(SCAUSE, [`XLEN-1:0]);
|
||||||
`INIT_CHECKPOINT_VAL(MEPC, [`XLEN-1:0]);
|
`INIT_CHECKPOINT_VAL(MEPC, [`XLEN-1:0]);
|
||||||
@ -332,32 +356,31 @@ module testbench;
|
|||||||
`INIT_CHECKPOINT_VAL(STVEC, [`XLEN-1:0]);
|
`INIT_CHECKPOINT_VAL(STVEC, [`XLEN-1:0]);
|
||||||
`INIT_CHECKPOINT_VAL(SATP, [`XLEN-1:0]);
|
`INIT_CHECKPOINT_VAL(SATP, [`XLEN-1:0]);
|
||||||
`INIT_CHECKPOINT_VAL(PRIV, [1:0]);
|
`INIT_CHECKPOINT_VAL(PRIV, [1:0]);
|
||||||
`MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [`XLEN-1:0],0,0);
|
|
||||||
`MAKE_CHECKPOINT_INIT_SIGNAL(SSTATUS, [`XLEN-1:0],0,0);
|
|
||||||
// Many UART registers are difficult to initialize because under the hood
|
|
||||||
// they are not simple registers. Instead some are generated by interesting
|
|
||||||
// combinational blocks such that they depend upon a variety of different
|
|
||||||
// underlying flops. See for example how RBR might be the actual RXBR
|
|
||||||
// register, but it could also just as well be 0 or the tail of the fifo
|
|
||||||
// array.
|
|
||||||
//`INIT_CHECKPOINT_VAL(UART_RBR, [7:0]);
|
|
||||||
`INIT_CHECKPOINT_VAL(UART_IER, [7:0]);
|
|
||||||
//`INIT_CHECKPOINT_VAL(UART_IIR, [7:0]);
|
|
||||||
`INIT_CHECKPOINT_VAL(UART_LCR, [7:0]);
|
|
||||||
`INIT_CHECKPOINT_VAL(UART_MCR, [4:0]);
|
|
||||||
//`INIT_CHECKPOINT_VAL(UART_LSR, [7:0]);
|
|
||||||
//`INIT_CHECKPOINT_VAL(UART_MSR, [7:0]);
|
|
||||||
`INIT_CHECKPOINT_VAL(UART_SCR, [7:0]);
|
|
||||||
`INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_PRIORITY, [2:0],`PLIC_NUM_SRC,1);
|
`INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_PRIORITY, [2:0],`PLIC_NUM_SRC,1);
|
||||||
`INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:1],1,0);
|
`INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:1],1,0);
|
||||||
`INIT_CHECKPOINT_PACKED_ARRAY(PLIC_THRESHOLD, [2:0],1,0);
|
`INIT_CHECKPOINT_PACKED_ARRAY(PLIC_THRESHOLD, [2:0],1,0);
|
||||||
|
// UART checkpointing does not cover entire UART state
|
||||||
|
// Many UART registers are difficult to initialize because under the hood
|
||||||
|
// they are not simple registers. Instead some are generated by interesting
|
||||||
|
// combinational blocks such that they depend upon a variety of different
|
||||||
|
// underlying flops. See for example how RBR might be the actual RXBR
|
||||||
|
// register, but it could also just as well be 0 or the tail of the fifo
|
||||||
|
// array.
|
||||||
|
`INIT_CHECKPOINT_VAL(UART_IER, [7:0]);
|
||||||
|
`INIT_CHECKPOINT_VAL(UART_LCR, [7:0]);
|
||||||
|
`INIT_CHECKPOINT_VAL(UART_MCR, [4:0]);
|
||||||
|
`INIT_CHECKPOINT_VAL(UART_SCR, [7:0]);
|
||||||
|
// xSTATUS need to be handled manually because the most upstream signals
|
||||||
|
// are made of individual bits, not registers
|
||||||
|
`MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [`XLEN-1:0],0,0);
|
||||||
|
`MAKE_CHECKPOINT_INIT_SIGNAL(SSTATUS, [`XLEN-1:0],0,0);
|
||||||
|
|
||||||
integer memFile;
|
// ========== INITIALIZATION ==========
|
||||||
integer readResult;
|
|
||||||
initial begin
|
initial begin
|
||||||
force dut.core.priv.priv.SwIntM = 0;
|
//force dut.core.priv.priv.SwIntM = 0;
|
||||||
force dut.core.priv.priv.TimerIntM = 0;
|
force dut.core.priv.priv.TimerIntM = 0;
|
||||||
force dut.core.priv.priv.MExtIntM = 0;
|
force dut.core.priv.priv.MExtIntM = 0;
|
||||||
|
force dut.core.priv.priv.SExtIntM = 0;
|
||||||
$sformat(testvectorDir,"%s/linux-testvectors/",RISCV_DIR);
|
$sformat(testvectorDir,"%s/linux-testvectors/",RISCV_DIR);
|
||||||
$sformat(linuxImageDir,"%s/buildroot/output/images/",RISCV_DIR);
|
$sformat(linuxImageDir,"%s/buildroot/output/images/",RISCV_DIR);
|
||||||
if (CHECKPOINT!=0)
|
if (CHECKPOINT!=0)
|
||||||
@ -377,18 +400,27 @@ module testbench;
|
|||||||
memFile = $fopen({checkpointDir,"ram.bin"}, "rb");
|
memFile = $fopen({checkpointDir,"ram.bin"}, "rb");
|
||||||
readResult = $fread(dut.uncore.ram.ram.memory.RAM,memFile);
|
readResult = $fread(dut.uncore.ram.ram.memory.RAM,memFile);
|
||||||
$fclose(memFile);
|
$fclose(memFile);
|
||||||
if (CHECKPOINT==0) begin // normal
|
// ---------- Ground-Zero -----------
|
||||||
|
if (CHECKPOINT==0) begin
|
||||||
traceFileM = $fopen({testvectorDir,"all.txt"}, "r");
|
traceFileM = $fopen({testvectorDir,"all.txt"}, "r");
|
||||||
traceFileE = $fopen({testvectorDir,"all.txt"}, "r");
|
traceFileE = $fopen({testvectorDir,"all.txt"}, "r");
|
||||||
|
interruptFile = $fopen({testvectorDir,"interrupts.txt"}, "r");
|
||||||
|
`SCAN_NEW_INTERRUPT
|
||||||
InstrCountW = '0;
|
InstrCountW = '0;
|
||||||
AttemptedInstructionCount = '0;
|
AttemptedInstructionCount = '0;
|
||||||
end else begin // checkpoint
|
// ---------- Checkpoint ----------
|
||||||
|
end else begin
|
||||||
//$readmemh({checkpointDir,"ram.txt"}, dut.uncore.ram.ram.memory.RAM);
|
//$readmemh({checkpointDir,"ram.txt"}, dut.uncore.ram.ram.memory.RAM);
|
||||||
traceFileE = $fopen({checkpointDir,"all.txt"}, "r");
|
traceFileE = $fopen({checkpointDir,"all.txt"}, "r");
|
||||||
traceFileM = $fopen({checkpointDir,"all.txt"}, "r");
|
traceFileM = $fopen({checkpointDir,"all.txt"}, "r");
|
||||||
|
interruptFile = $fopen({testvectorDir,"interrupts.txt"}, "r");
|
||||||
|
`SCAN_NEW_INTERRUPT
|
||||||
|
while(interruptInstrCount < CHECKPOINT) begin
|
||||||
|
`SCAN_NEW_INTERRUPT
|
||||||
|
end
|
||||||
InstrCountW = CHECKPOINT;
|
InstrCountW = CHECKPOINT;
|
||||||
AttemptedInstructionCount = CHECKPOINT;
|
AttemptedInstructionCount = CHECKPOINT;
|
||||||
// manual checkpoint initializations that don't neatly fit into MACRO
|
// manual checkpoint initializations
|
||||||
force {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV} = initMSTATUS[0][22:17];
|
force {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV} = initMSTATUS[0][22:17];
|
||||||
force {`STATUS_FS,`STATUS_MPP} = initMSTATUS[0][14:11];
|
force {`STATUS_FS,`STATUS_MPP} = initMSTATUS[0][14:11];
|
||||||
force {`STATUS_SPP,`STATUS_MPIE} = initMSTATUS[0][8:7];
|
force {`STATUS_SPP,`STATUS_MPIE} = initMSTATUS[0][8:7];
|
||||||
@ -409,11 +441,10 @@ module testbench;
|
|||||||
matchCountE = $fgets(lineE,traceFileE);
|
matchCountE = $fgets(lineE,traceFileE);
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
//////////////////////////////////// CORE /////////////////////////////////////
|
//////////////////////////////////// CORE /////////////////////////////////////
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
// =========== TRACE PARSING MACRO ==========
|
||||||
// Because qemu does not match exactly to wally it is necessary to read the the
|
// Because qemu does not match exactly to wally it is necessary to read the the
|
||||||
// trace in the memory stage and detect if anything in wally must be overwritten.
|
// trace in the memory stage and detect if anything in wally must be overwritten.
|
||||||
// This includes mtimer, interrupts, and various bits in mstatus and xtval.
|
// This includes mtimer, interrupts, and various bits in mstatus and xtval.
|
||||||
@ -422,7 +453,6 @@ module testbench;
|
|||||||
// on the next falling edge the expected state is compared to the wally state.
|
// on the next falling edge the expected state is compared to the wally state.
|
||||||
|
|
||||||
// step 0: read the expected state
|
// step 0: read the expected state
|
||||||
assign checkInstrM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM & ~dut.core.StallM;
|
|
||||||
`define SCAN_NEW_INSTR_FROM_TRACE(STAGE) \
|
`define SCAN_NEW_INSTR_FROM_TRACE(STAGE) \
|
||||||
// always check PC, instruction bits \
|
// always check PC, instruction bits \
|
||||||
if (checkInstrM) begin \
|
if (checkInstrM) begin \
|
||||||
@ -486,22 +516,6 @@ module testbench;
|
|||||||
matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE], "%s", ExpectedCSRArray``STAGE[NumCSR``STAGE]); \
|
matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE], "%s", ExpectedCSRArray``STAGE[NumCSR``STAGE]); \
|
||||||
matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%x", ExpectedCSRArrayValue``STAGE[NumCSR``STAGE]); \
|
matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%x", ExpectedCSRArrayValue``STAGE[NumCSR``STAGE]); \
|
||||||
MarkerIndex``STAGE += 2; \
|
MarkerIndex``STAGE += 2; \
|
||||||
if(`"STAGE`"=="E") begin \
|
|
||||||
// match MIP to QEMU's because interrupts are imprecise \
|
|
||||||
if(ExpectedCSRArrayE[NumCSRE].substr(0, 2) == "mip") begin \
|
|
||||||
CheckMIPFutureE = 1; \
|
|
||||||
NextMIPexpected = ExpectedCSRArrayValueE[NumCSRE]; \
|
|
||||||
end \
|
|
||||||
if(ExpectedCSRArrayE[NumCSRE].substr(0, 2) == "sip") begin \
|
|
||||||
CheckSIPFutureE = 1; \
|
|
||||||
NextSIPexpected = ExpectedCSRArrayValueE[NumCSRE]; \
|
|
||||||
end \
|
|
||||||
if(ExpectedCSRArrayE[NumCSRE].substr(0,3) == "mepc") begin \
|
|
||||||
// $display("hello! we are here."); \
|
|
||||||
MepcExpected = ExpectedCSRArrayValueE[NumCSRE]; \
|
|
||||||
$display("%tns: MepcExpected: %x",$time,MepcExpected); \
|
|
||||||
end \
|
|
||||||
end \
|
|
||||||
\
|
\
|
||||||
NumCSR``STAGE++; \
|
NumCSR``STAGE++; \
|
||||||
end \
|
end \
|
||||||
@ -520,93 +534,28 @@ module testbench;
|
|||||||
end \
|
end \
|
||||||
end \
|
end \
|
||||||
|
|
||||||
|
// ========== VALUE-CHECKING MACROS ==========
|
||||||
|
`define checkEQ(NAME, VAL, EXPECTED) \
|
||||||
|
if(VAL != EXPECTED) begin \
|
||||||
|
$display("%tns, %d instrs: %s %x differs from expected %x", $time, InstrCountW, NAME, VAL, EXPECTED); \
|
||||||
|
if ((NAME == "PCW") | (`DEBUG_TRACE >= 2)) fault = 1; \
|
||||||
|
end
|
||||||
|
|
||||||
|
`define checkCSR(CSR) \
|
||||||
|
begin \
|
||||||
|
if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \
|
||||||
|
$display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, InstrCountW, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \
|
||||||
|
if(`DEBUG_TRACE >= 3) fault = 1; \
|
||||||
|
end \
|
||||||
|
end
|
||||||
|
|
||||||
|
// =========== CORE ===========
|
||||||
|
assign checkInstrM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM & ~dut.core.StallM;
|
||||||
always @(negedge clk) begin
|
always @(negedge clk) begin
|
||||||
`SCAN_NEW_INSTR_FROM_TRACE(E)
|
`SCAN_NEW_INSTR_FROM_TRACE(E)
|
||||||
end
|
|
||||||
|
|
||||||
always @(negedge clk) begin
|
|
||||||
`SCAN_NEW_INSTR_FROM_TRACE(M)
|
`SCAN_NEW_INSTR_FROM_TRACE(M)
|
||||||
end
|
end
|
||||||
|
|
||||||
// MIP spoofing
|
|
||||||
always @(posedge clk) begin
|
|
||||||
#1;
|
|
||||||
if(CheckMIPFutureE) CheckMIPFutureE <= 0;
|
|
||||||
CheckMIPFutureM <= CheckMIPFutureE;
|
|
||||||
if(CheckMIPFutureM) begin
|
|
||||||
// $display("%tns: ExpectedPCM %x",$time,ExpectedPCM);
|
|
||||||
// $display("%tns: ExpectedPCE %x",$time,ExpectedPCE);
|
|
||||||
// $display("%tns: ExpectedPCW %x",$time,ExpectedPCW);
|
|
||||||
// *** this is probably not right anymore since either MIP or SIP can be forced.
|
|
||||||
if((ExpectedPCE != MepcExpected) & ((MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE) <= 200) | ~dut.core.ieu.c.InstrValidM) begin
|
|
||||||
RequestDelayedMIP <= 1;
|
|
||||||
$display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected);
|
|
||||||
end else begin // update MIP immediately
|
|
||||||
$display("%tns: Updating MIP to %x",$time,NextMIPexpected);
|
|
||||||
MIPexpected = NextMIPexpected;
|
|
||||||
//force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected;
|
|
||||||
//force dut.core.priv.priv.csr.csri.SIP_REGW = MIPexpected;
|
|
||||||
force dut.core.priv.priv.csr.csri.IP_REGW = MIPexpected;
|
|
||||||
end
|
|
||||||
// $display("%tn: ExpectedCSRArrayM = %p",$time,ExpectedCSRArrayM);
|
|
||||||
// $display("%tn: ExpectedCSRArrayValueM = %p",$time,ExpectedCSRArrayValueM);
|
|
||||||
// $display("%tn: ExpectedTokens = %p",$time,ExpectedTokensM);
|
|
||||||
// $display("%tn: MepcExpected = %x",$time,MepcExpected);
|
|
||||||
// $display("%tn: ExpectedPCE = %x",$time,ExpectedPCE);
|
|
||||||
// $display("%tns: Difference/multiplication thing: %x",$time,(MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE));
|
|
||||||
// $display("%tn: ExpectedCSRArrayM[NumCSRM] %x",$time,ExpectedCSRArrayM[NumCSRM]);
|
|
||||||
// $display("%tn: ExpectedCSRArrayValueM[NumCSRM] %x",$time,ExpectedCSRArrayValueM[NumCSRM]);
|
|
||||||
end
|
|
||||||
if(RequestDelayedMIP & checkInstrM) begin
|
|
||||||
$display("%tns: Executing Delayed MIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW);
|
|
||||||
$display("%tns: Updating MIP to %x",$time,NextMIPexpected);
|
|
||||||
MIPexpected = NextMIPexpected;
|
|
||||||
//force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected;
|
|
||||||
//force dut.core.priv.priv.csr.csri.SIP_REGW = MIPexpected;
|
|
||||||
force dut.core.priv.priv.csr.csri.IP_REGW = MIPexpected;
|
|
||||||
$display("%tns: Finished Executing Delayed MIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW);
|
|
||||||
RequestDelayedMIP = 0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// SIP spoofing
|
|
||||||
/* -----\/----- EXCLUDED -----\/-----
|
|
||||||
always @(posedge clk) begin
|
|
||||||
#1;
|
|
||||||
if(CheckSIPFutureE) CheckSIPFutureE <= 0;
|
|
||||||
CheckSIPFutureM <= CheckSIPFutureE;
|
|
||||||
if(CheckSIPFutureM) begin
|
|
||||||
// $display("%tns: ExpectedPCM %x",$time,ExpectedPCM);
|
|
||||||
// $display("%tns: ExpectedPCE %x",$time,ExpectedPCE);
|
|
||||||
// $display("%tns: ExpectedPCW %x",$time,ExpectedPCW);
|
|
||||||
if((ExpectedPCE != MepcExpected) & ((MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE) <= 200) | ~dut.core.ieu.c.InstrValidM) begin
|
|
||||||
RequestDelayedSIP <= 1;
|
|
||||||
$display("%tns: Requesting Delayed SIP. Current MEPC value is %x",$time,MepcExpected);
|
|
||||||
end else begin // update SIP immediately
|
|
||||||
$display("%tns: Updating SIP to %x",$time,NextSIPexpected);
|
|
||||||
SIPexpected = NextSIPexpected;
|
|
||||||
force dut.core.priv.priv.csr.csri.SIP_REGW = SIPexpected;
|
|
||||||
end
|
|
||||||
// $display("%tn: ExpectedCSRArrayM = %p",$time,ExpectedCSRArrayM);
|
|
||||||
// $display("%tn: ExpectedCSRArrayValueM = %p",$time,ExpectedCSRArrayValueM);
|
|
||||||
// $display("%tn: ExpectedTokens = %p",$time,ExpectedTokensM);
|
|
||||||
// $display("%tn: MepcExpected = %x",$time,MepcExpected);
|
|
||||||
// $display("%tn: ExpectedPCE = %x",$time,ExpectedPCE);
|
|
||||||
// $display("%tns: Difference/multiplication thing: %x",$time,(MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE));
|
|
||||||
// $display("%tn: ExpectedCSRArrayM[NumCSRM] %x",$time,ExpectedCSRArrayM[NumCSRM]);
|
|
||||||
// $display("%tn: ExpectedCSRArrayValueM[NumCSRM] %x",$time,ExpectedCSRArrayValueM[NumCSRM]);
|
|
||||||
end
|
|
||||||
if(RequestDelayedSIP & checkInstrM) begin
|
|
||||||
$display("%tns: Executing Delayed SIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW);
|
|
||||||
$display("%tns: Updating SIP to %x",$time,NextSIPexpected);
|
|
||||||
SIPexpected = NextSIPexpected;
|
|
||||||
force dut.core.priv.priv.csr.csri.SIP_REGW = SIPexpected;
|
|
||||||
$display("%tns: Finished Executing Delayed SIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW);
|
|
||||||
RequestDelayedSIP = 0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
-----/\----- EXCLUDED -----/\----- */
|
|
||||||
|
|
||||||
// step 1: register expected state into the write back stage.
|
// step 1: register expected state into the write back stage.
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
if (reset) begin
|
if (reset) begin
|
||||||
@ -667,7 +616,7 @@ module testbench;
|
|||||||
end
|
end
|
||||||
|
|
||||||
// step2: make all checks in the write back stage.
|
// step2: make all checks in the write back stage.
|
||||||
assign checkInstrW = InstrValidW & ~dut.core.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction.
|
assign checkInstrW = InstrValidW & ~dut.core.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction.
|
||||||
always @(negedge clk) begin
|
always @(negedge clk) begin
|
||||||
// always check PC, instruction bits
|
// always check PC, instruction bits
|
||||||
if (checkInstrW) begin
|
if (checkInstrW) begin
|
||||||
@ -736,18 +685,38 @@ module testbench;
|
|||||||
end // always @ (negedge clk)
|
end // always @ (negedge clk)
|
||||||
|
|
||||||
|
|
||||||
// track the current function
|
// New IP spoofing
|
||||||
|
always @(posedge clk) begin
|
||||||
|
#1
|
||||||
|
if(checkInstrM) begin
|
||||||
|
if((interruptInstrCount+1) == AttemptedInstructionCount) begin
|
||||||
|
force dut.core.priv.priv.csr.csri.IP_REGW = 32'b1 << interruptCauseVal;
|
||||||
|
$display("Forcing interrupt.");
|
||||||
|
`SCAN_NEW_INTERRUPT
|
||||||
|
garbageInt = $fgets(garbageString,traceFileE);
|
||||||
|
garbageInt = $fgets(garbageString,traceFileM);
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
//////////////////////////////// Extra Features ///////////////////////////////
|
||||||
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Function Tracking
|
||||||
FunctionName FunctionName(.reset(reset),
|
FunctionName FunctionName(.reset(reset),
|
||||||
.clk(clk),
|
.clk(clk),
|
||||||
.ProgramAddrMapFile(ProgramAddrMapFile),
|
.ProgramAddrMapFile(ProgramAddrMapFile),
|
||||||
.ProgramLabelMapFile(ProgramLabelMapFile));
|
.ProgramLabelMapFile(ProgramLabelMapFile));
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
|
||||||
//////////////////////////////// Extra Features ///////////////////////////////
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
|
||||||
// Instr Opcode Tracking
|
// Instr Opcode Tracking
|
||||||
// For waveview convenience
|
// For waveview convenience
|
||||||
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
|
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user