Merge remote-tracking branch 'upstream/main' into main

sim/wally-imperas-cov.do

@@ -0,0 +1,69 @@
+# wally.do 
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+#
+# Modification by Oklahoma State University & Harvey Mudd College
+# Use with Testbench 
+# James Stine, 2008; David Harris 2021
+# Go Cowboys!!!!!!
+#
+# Takes 1:10 to run RV64IC tests using gui
+
+onbreak {resume}
+
+# create library
+if [file exists work] {
+    vdel -all
+}
+vlib work
+
+# compile source files
+# suppress spurious warnngs about 
+# "Extra checking for conflicts with always_comb done at vopt time"
+# because vsim will run vopt
+
+# start and run simulation
+# remove +acc flag for faster sim during regressions if there is no need to access internal signals
+        # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN.  For now just live with the warnings.
+vlog +incdir+../config/$1 \
+     +incdir+../config/shared \
+     +define+USE_IMPERAS_DV \
+     +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
+     +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
+     $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv    \
+     $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv      \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv   \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/imperasDV-api-pkg.sv \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv  \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv  \
+     \
+     +define+INCLUDE_TRACE2COV +define+COVER_BASE_RV64I +define+COVER_LEVEL_DV_PR_EXT \
+       +define+COVER_RV64I \
+       +define+COVER_RV64C \
+       +define+COVER_RV64M \
+     +incdir+$env(IMPERAS_HOME)/ImpProprietary/source/host/riscvISACOV/source \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv  \
+     \
+     ../testbench/testbench_imperas.sv \
+     ../testbench/common/*.sv   \
+     ../src/*/*.sv \
+     ../src/*/*/*.sv \
+     -suppress 2583 \
+     -suppress 7063  \
+     +acc
+vopt +acc work.testbench -G DEBUG=1 -o workopt 
+vsim workopt +nowarn3829  -fatal 7 \
+     -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \
+     +testDir=$env(TESTDIR) $env(OTHERFLAGS) +TRACE2COV_ENABLE=1 \
+     -do "coverage save -onexit ./riscv.ucdb"
+
+view wave
+#-- display input and output signals as hexidecimal values
+# add log -recursive /*
+# do wave.do
+
+run -all
+
+noview ../testbench/testbench_imperas.sv
+view wave
+
+quit -f

sim/wally-imperas.do

@@ -32,6 +32,7 @@ vlog +incdir+../config/$1 \
      $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv    \
      $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv      \
      $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv   \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/imperasDV-api-pkg.sv \
      $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv  \
      $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv  \
      ../testbench/testbench_imperas.sv \

src/ifu/bpred/bpred.sv

@@ -103,7 +103,7 @@ module bpred (
       .PCSrcE);
 
   end else if (`BPRED_TYPE == "BP_GLOBAL") begin:Predictor
-    gshare #(`BPRED_SIZE, "global") DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+    gshare #(`BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
       .PCSrcE);
@@ -131,7 +131,7 @@ module bpred (
 
 =======
   end else if (`BPRED_TYPE == "BP_GLOBAL_BASIC") begin:Predictor
-    gsharebasic #(`BPRED_SIZE, "global") DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+    gsharebasic #(`BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
 	

src/ifu/bpred/gshare.sv

@@ -30,7 +30,7 @@
 `include "wally-config.vh"
 
 module gshare #(parameter k = 10,
-                parameter string TYPE = "gshare") (
+                parameter integer TYPE = 1) (
   input logic             clk,
   input logic             reset,
   input logic             StallF, StallD, StallE, StallM, 
@@ -54,13 +54,13 @@ module gshare #(parameter k = 10,
   logic [k-1:0]            GHRNextM, GHRNextF;
   logic                    PCSrcM;
 
-  if(TYPE == "gshare") begin
+  if(TYPE == 1) begin
 	assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
 	assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
 	assign IndexD = GHRD ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
 	assign IndexE = GHRE ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
 	assign IndexM = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
-  end else if(TYPE == "global") begin
+  end else if(TYPE == 0) begin
 	assign IndexNextF = GHRNextF;
 	assign IndexF = GHRF;
 	assign IndexD = GHRD;

src/ifu/bpred/gsharebasic.sv

@@ -30,7 +30,7 @@
 `include "wally-config.vh"
 
 module gsharebasic #(parameter k = 10,
-                     parameter string TYPE = "global") (
+                     parameter TYPE = 1) (
   input logic             clk,
   input logic             reset,
   input logic             StallF, StallD, StallE, StallM, StallW,
@@ -50,10 +50,10 @@ module gsharebasic #(parameter k = 10,
   logic [k-1:0]            GHRNext;
   logic                    PCSrcM;
 
-  if(TYPE == "gshare") begin
+  if(TYPE == 1) begin
 	assign IndexNextF = GHR ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
 	assign IndexE = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
-  end else if(TYPE == "global") begin
+  end else if(TYPE == 0) begin
 	assign IndexNextF = GHRNext;
 	assign IndexE = GHRE;
   end

testbench/testbench_imperas.sv

@@ -40,6 +40,7 @@ module testbench;
 `ifdef USE_IMPERAS_DV
   import rvviPkg::*;
   import rvviApiPkg::*;
+  import idvApiPkg::*;
 `endif
 
   logic        clk;