Updated EBU to replace tabs with spaces.

src/ebu/ahbinterface.sv

@@ -53,7 +53,6 @@ module ahbinterface #(
 );
   
   logic                                 CaptureEn;
-
   localparam                            LEN = (LSU ? `XLEN : 32);   // 32 bits for IFU, XLEN for LSU
   
   flopen #(LEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA[LEN-1:0]), .q(FetchBuffer));
@@ -70,4 +69,5 @@ module ahbinterface #(
   busfsm busfsm(.HCLK, .HRESETn, .Flush, .BusRW,
     .BusCommitted, .Stall, .BusStall, .CaptureEn, .HREADY,
     .HTRANS, .HWRITE);
+
 endmodule

src/ebu/ebu.sv

@@ -89,8 +89,6 @@ module ebu (
   logic                       IFUReq;
   logic 					  LSUReq;
 
-  
-  
   assign HCLK = clk;
   assign HRESETn = ~reset;
 

src/ebu/ebufsmarb.sv

@@ -41,7 +41,6 @@ module ebufsmarb (
   input  logic       LSUReq,
   input  logic       IFUReq,
   
-  
   output logic       IFUSave,
   output logic       IFURestore,
   output logic       IFUDisable,
@@ -100,27 +99,24 @@ module ebufsmarb (
 
   assign BeatCntReset = NextState == IDLE;
   assign FinalBeat = (BeatCount == Threshold); // Detect when we are waiting on the final access.
+  // Counting the beats in the EBU is only necessary when both the LSU and IFU request concurrently.  
+  // LSU has priority. HREADY serves double duty during a burst transaction.  It indicates when the
+  // beat completes and when the transaction finishes.  However there is nothing external to
+  // differentiate them.  The EBU counts the HREADY beats so it knows when to switch to the IFU's 
+  // request.
   assign BeatCntEn = (NextState == ARBITRATE) & HREADY; 
   counter #(4) BeatCounter(HCLK, ~HRESETn | BeatCntReset | FinalBeat, BeatCntEn, BeatCount);  
  
   // Used to store data from data phase of AHB.
   flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | BeatCntReset, BeatCntEn, FinalBeat, FinalBeatD);
 
-  // unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST.
+  // unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST, Threshold = num beats - 1.
-  //  HBURST[2:1] Beats
+  //  HBURST[2:1] Beats  threshold
-  //  00          1
+  //  00          1      0
-  //  01          4
+  //  01          4      3
-  //  10          8
+  //  10          8      7
-  //  11          16
+  //  11          16     15
   always_comb 
     if (HBURST[2:1] == 2'b00) Threshold = 4'b0000;
     else                      Threshold = (2 << HBURST[2:1]) - 1;
-/*    case(HBURST)
-      0:        Threshold = 4'b0000;
-      3:        Threshold = 4'b0011; // INCR4
-      5:        Threshold = 4'b0111; // INCR8
-      7:        Threshold = 4'b1111; // INCR16
-      default:  Threshold = 4'b0000; // INCR without end.
-    endcase
-  end */
 endmodule