Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

wally-pipelined/config/rv32ic/wally-config.vh

@@ -68,8 +68,8 @@
 
 `define BOOTTIMBASE   32'h00000000
 `define BOOTTIMRANGE  32'h00003FFF
-`define TIMBASE    32'h80000000
+`define TIMBASE       32'h80000000
-`define TIMRANGE   32'h0007FFFF
+`define TIMRANGE      32'h07FFFFFF
 `define CLINTBASE  32'h02000000
 `define CLINTRANGE 32'h0000FFFF
 `define GPIOBASE   32'h10012000

wally-pipelined/config/rv64ic/wally-config.vh

@@ -72,8 +72,8 @@
 
 `define BOOTTIMBASE   32'h00000000
 `define BOOTTIMRANGE  32'h00003FFF
-`define TIMBASE    32'h80000000
+`define TIMBASE       32'h80000000
-`define TIMRANGE   32'h0007FFFF
+`define TIMRANGE      32'h07FFFFFF
 `define CLINTBASE  32'h02000000
 `define CLINTRANGE 32'h0000FFFF
 `define GPIOBASE   32'h10012000

wally-pipelined/regression/regression-wally.py

@@ -19,7 +19,7 @@ configs = [
     Config(
         name="busybear",
         cmd="vsim -do wally-busybear-batch.do -c > {}",
-        grepstr="# loaded 800000 instructions"
+        grepstr="# loaded 40000 instructions"
     ),
     Config(
         name="buildroot",

wally-pipelined/src/privileged/csrm.sv

@@ -97,7 +97,7 @@ module csrm #(parameter
   );
 
   logic [`XLEN-1:0] MISA_REGW;
-  logic [`XLEN-1:0] MSCRATCH_REGW,MCAUSE_REGW, MTVAL_REGW;
+  logic [`XLEN-1:0] MSCRATCH_REGW, MCAUSE_REGW, MTVAL_REGW;
   logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW; // 64-bit registers in RV64, or two 32-bit registers in RV32
   logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15];  // *** Might have to make 16 individual registers
   //logic [`XLEN-1:0] PMPADDR0_REGW;

wally-pipelined/src/privileged/trap.sv

@@ -27,7 +27,7 @@
 `include "wally-config.vh"
 
 module trap (
-  input  logic             reset, 
+  input  logic             clk, reset, 
   input  logic             InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM,
   input  logic             BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM,
   input  logic             LoadAccessFaultM, StoreAccessFaultM, EcallFaultM, InstrPageFaultM,
@@ -40,6 +40,7 @@ module trap (
   input  logic [`XLEN-1:0] PCM,
   input  logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, 
   input  logic [31:0]      InstrM,
+  input  logic             StallW,
   output logic             TrapM, MTrapM, STrapM, UTrapM, RetM,
   output logic             InterruptM,
   output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM
@@ -74,11 +75,18 @@ module trap (
 
   // Handle vectored traps (when mtvec/stvec/utvec csr value has bits [1:0] == 01)
   // For vectored traps, set program counter to _tvec value + 4 times the cause code
+  //
+  // POSSIBLE OPTIMIZATION: 
+  // From 20190608 privielegd spec page 27 (3.1.7)
+  // > Allowing coarser alignments in Vectored mode enables vectoring to be
+  // > implemented without a hardware adder circuit.
+  // For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with
+  // [untested] PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:7], CauseM[3:0], 4'b0000}
   generate
     if(`VECTORED_INTERRUPTS_SUPPORTED) begin
         always_comb
           if (PrivilegedTrapVector[1:0] == 2'b01 && CauseM[`XLEN-1] == 1)
-            PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + CauseM[`XLEN-3:0], 2'b00};
+            PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + {CauseM[`XLEN-5:0], 2'b00}, 2'b00};
           else
             PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00};
     end
@@ -91,7 +99,7 @@ module trap (
     if      (mretM)                         PrivilegedNextPCM = MEPC_REGW;
     else if (sretM)                         PrivilegedNextPCM = SEPC_REGW;
     else if (uretM)                         PrivilegedNextPCM = UEPC_REGW;
-    else                                    PrivilegedNextPCM = PrivilegedTrapVector;
+    else                                    PrivilegedNextPCM = PrivilegedVectoredTrapVector;
 
   // Cause priority defined in table 3.7 of 20190608 privileged spec
   // Exceptions are of lower priority than all interrupts (3.1.9)

wally-pipelined/testbench/function_radix.sv

@@ -110,6 +110,8 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
   integer ProgramAddrMapLineCount, ProgramLabelMapLineCount;
   longint ProgramAddrMapLine;
   string  ProgramLabelMapLine;
+  integer status;
+  
 
   // preload
 //  initial begin
@@ -123,7 +125,7 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
     // read line by line to count lines
     if (ProgramAddrMapFP) begin
       while (! $feof(ProgramAddrMapFP)) begin
-	$fscanf(ProgramAddrMapFP, "%h\n", ProgramAddrMapLine);
+	status = $fscanf(ProgramAddrMapFP, "%h\n", ProgramAddrMapLine);
 	
 	ProgramAddrMapLineCount = ProgramAddrMapLineCount + 1;
       end
@@ -141,7 +143,7 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
     
     if (ProgramLabelMapFP) begin
       while (! $feof(ProgramLabelMapFP)) begin
-	$fscanf(ProgramLabelMapFP, "%s\n", ProgramLabelMapLine);
+	status = $fscanf(ProgramLabelMapFP, "%s\n", ProgramLabelMapLine);
 	ProgramLabelMapMemory[ProgramLabelMapLineCount] = ProgramLabelMapLine;
 	ProgramLabelMapLineCount = ProgramLabelMapLineCount + 1;
       end

wally-pipelined/testbench/testbench-imperas.sv

@@ -351,6 +351,7 @@ module testbench();
     "rv64p/WALLY-SEPC", "4000",
     "rv64p/WALLY-MTVAL", "6000",
     "rv64p/WALLY-STVAL", "4000",
+    "rv64p/WALLY-MTVEC", "2000",
     "rv64p/WALLY-MARCHID", "4000",
     "rv64p/WALLY-MIMPID", "4000",
     "rv64p/WALLY-MHARTID", "4000",
@@ -371,6 +372,7 @@ module testbench();
     "rv32p/WALLY-MHARTID", "4000",
     "rv32p/WALLY-MVENDORID", "4000"
     //"rv32p/WALLY-MEDELEG", "4000" // all 32 bit tests are currently failing, so haven't been able to confirm this test works yet. It should, though.
+    //"rv32p/WALLY-MTVEC", "2000" // all 32 bit tests are currently failing, so haven't been able to confirm this test works yet. It should, though.
   };
 
   string tests64periph[] = '{