added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)

.gitmodules

@@ -16,7 +16,10 @@
 	url = https://github.com/google/riscv-dv
 [submodule "addins/embench-iot"]
 	path = addins/embench-iot
-	url = https://github.com/embench/embench-iot
+	url = https://github.com/DTowersM/embench-iot
+[submodule "addins/coremark"]
+	path = addins/coremark
+	url = https://github.com/eembc/coremark
 [submodule "addins/sky130_osu_sc_t18"]
 	path = addins/sky130_osu_sc_t18
 	url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t18

addins/coremark

@@ -0,0 +1 @@
+Subproject commit f3e8f2e0941e42961aadcc52750b1b5577c157c9

benchmarks/coremark/.gitignore

@@ -1,2 +0,0 @@
-coremark.riscv
-coremark.bare.riscv

benchmarks/coremark/.gitmodules

@@ -1,3 +0,0 @@
-[submodule "coremark"]
-	path = src
-	url = https://github.com/eembc/coremark

benchmarks/coremark/Makefile

@@ -1,28 +1,29 @@
 #cmbase=../../addins/coremark
 PORT_DIR = $(CURDIR)/riscv64-baremetal
-cmbase=src
+cmbase=../../addins/coremark
+work_dir=$(cmbase)/work
 sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h  \
         $(cmbase)/core_matrix.c $(cmbase)/core_state.c $(cmbase)/core_util.c \
 		$(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \
 		$(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c
 
-work/coremark.bare.riscv.elf.memfile: work/coremark.bare.riscv
+$(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
 	riscv64-unknown-elf-objdump -D $< > $<.elf.objdump
 	riscv64-unknown-elf-elf2hex --bit-width 64 --input $< --output $@
 	extractFunctionRadix.sh $<.elf.objdump
-	(cd ../../pipelined/regression && (vsim -c -do "do wally-pipelined-batch.do rv64gc coremark" > ../../benchmarks/coremark/work/coremark.bare.riscv.sim.output))
+	(cd ../../pipelined/regression && (vsim -c -do "do wally-pipelined-batch.do rv64gc coremark" > $(work_dir)/coremark.sim.log))
 	cd ../../benchmarks/coremark/
 
-work/coremark.bare.riscv: $(sources) Makefile
+$(work_dir)/coremark.bare.riscv: $(sources) Makefile
-#	make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=/opt/riscv/riscv-gnu-toolchain XCFLAGS="-march=rv64imd -mabi=lp64d -mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-7-series -Ofast -funroll-all-loops -fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 -funroll-all-loops --param=uninlined-function-insns=8 -fno-tree-vrp -fwrapv -fno-toplevel-reorder --param=max-inline-insns-size=128 -fipa-pta"
+    # make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=/opt/riscv/riscv-gnu-toolchain XCFLAGS="-march=rv64imd -mabi=lp64d -mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-7-series -Ofast -funroll-all-loops -fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 -funroll-all-loops --param=uninlined-function-insns=8 -fno-tree-vrp -fwrapv -fno-toplevel-reorder --param=max-inline-insns-size=128 -fipa-pta"
- # These flags were used by WD on CoreMark
+    # These flags were used by WD on CoreMark
 	make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=$(RISCV)/riscv-gnu-toolchain XCFLAGS="-march=rv64imd -mabi=lp64d -mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-7-series -Ofast -funroll-all-loops -fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 -funroll-all-loops --param=uninlined-function-insns=8 -fno-tree-vrp -fwrapv -fipa-pta " 
-# -fno-toplevel-reorder --param=max-inline-insns-size=128 " # adding this bit caused a compiler error
+    # -fno-toplevel-reorder --param=max-inline-insns-size=128 " # adding this bit caused a compiler error
-	mkdir -p work/
+	mkdir -p $(work_dir)
-	mv $(cmbase)/coremark.bare.riscv work/
+	mv $(cmbase)/coremark.bare.riscv $(work_dir)
 
 
 .PHONY: clean
 
 clean:
-	rm -f work/*
+	rm -f $(work_dir)/*

benchmarks/coremark/riscv64-baremetal/core_portme.c

@@ -210,9 +210,12 @@ CORE_TICKS get_time(void) {
 */
 secs_ret time_in_secs(CORE_TICKS ticks) {
 	secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC;
-	int retvalint = (int)retval;
+	float retvalint = (float) retval;
-	//ee_printf("RETURN VALUE FROM TIME IN SECS FUNCTION: %d\n", retvalint);
+	ee_printf("RETURN VALUE FROM TIME IN SECS FUNCTION: %d\n", retvalint);
-	return retval;
+	ee_printf("RETURN VALUE FROM TIME IN SECS FUNCTION: %f\n", retvalint);
+	ee_printf("RETURN VALUE FROM TIME IN SECS FUNCTION: %d\n", retval);
+	ee_printf("RETURN VALUE FROM TIME IN SECS FUNCTION: %f\n", retval);
+	return retvalint;
 }
 #else
 #error "Please implement timing functionality in core_portme.c"

benchmarks/embench/Makefile

@@ -2,6 +2,8 @@
 # Expanded and developed by Daniel Torres dtorres@hmc.edu
 # Compile Embench for Wally
 
+embench_dir = ../../addins/embench-iot
+
 all: sim size
 
 allClean: clean all
@@ -10,12 +12,12 @@ build: buildspeed buildsize
 
 # uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed
 buildspeed:
-	../../addins/embench-iot/build_all.py --builddir=bd_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-O2 -nostartfiles" 
+	$(embench_dir)/build_all.py --builddir=bd_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-O2 -nostartfiles" 
-	find ../../addins/embench-iot/bd_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done
+	find $(embench_dir)/bd_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done
 
 # uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for size
 buildsize:
-	../../addins/embench-iot/build_all.py --builddir=bd_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S" --cflags="-Os -msave-restore" --dummy-libs="libgcc libm libc crt0"
+	$(embench_dir)/build_all.py --builddir=bd_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S" --cflags="-Os -msave-restore" --dummy-libs="libgcc libm libc crt0"
 
 # builds dependencies, then launches modelsim and finally runs python wrapper script to present results
 sim: modelsim_build_memfile modelsim_run speed
@@ -27,36 +29,36 @@ modelsim_run:
 
 # builds the objdump based on the compiled c elf files
 objdump: buildspeed
-	find ../../addins/embench-iot/bd_speed/ -type f -name "*.elf" | while read f; do riscv64-unknown-elf-objdump -S -D "$$f" > "$$f.objdump"; done
+	find $(embench_dir)/bd_speed/ -type f -name "*.elf" | while read f; do riscv64-unknown-elf-objdump -S -D "$$f" > "$$f.objdump"; done
 
 # build memfiles, objdump.lab and objdump.addr files
 modelsim_build_memfile: objdump
-	find ../../addins/embench-iot/bd_speed/ -type f -name "*.elf" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 32 --input "$$f" --output "$$f.memfile"; done
+	find $(embench_dir)/bd_speed/ -type f -name "*.elf" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 32 --input "$$f" --output "$$f.memfile"; done
-	find ../../addins/embench-iot/bd_speed/ -type f -name "*.elf.objdump" | while read f; do extractFunctionRadix.sh $$f; done
+	find $(embench_dir)/bd_speed/ -type f -name "*.elf.objdump" | while read f; do extractFunctionRadix.sh $$f; done
 
 # builds the tests for speed, runs them on spike and then launches python script to present results
 # note that the speed python script benchmark_speed.py can get confused if there's both a .output file created from spike and modelsim
 # you'll need to manually remove one of the two .output files, or run make clean
-spike: buildspeed spikecmd speed
+spike: buildspeed objdump spike_run speed
 
 # command to run spike on all of the benchmarks
-spike_run: buildspeed
+spike_run:
-	find ../../addins/embench-iot/bd_speed/ -type f -name "*.elf" | while read f; do spike --isa=rv32imac +signature=$$f.spike.output +signature-granularity=4 $$f; done
+	find $(embench_dir)/bd_speed/ -type f -name "*.elf" | while read f; do spike --isa=rv32imac +signature=$$f.spike.output +signature-granularity=4 $$f; done
 
 # python wrapper to present results of embench size benchmark
 size: buildsize
-	../../addins/embench-iot/benchmark_size.py --builddir=bd_size
+	$(embench_dir)/benchmark_size.py --builddir=bd_size --json-output > wallySize.output
 
 # python wrapper to present results of embench speed benchmark
 speed:
-	../../addins/embench-iot/benchmark_speed.py --builddir=bd_speed --target-module run_wally --cpu-mhz=1
+	$(embench_dir)/benchmark_speed.py --builddir=bd_speed --target-module run_wally --cpu-mhz=1 --json-output > wallySpeed.json
 
 # deletes all files
 clean: 
-	rm -rf ../../addins/embench-iot/bd_speed/
+	rm -rf $(embench_dir)/bd_speed/
-	rm -rf ../../addins/embench-iot/bd_size/
+	rm -rf $(embench_dir)/bd_size/
 
 allclean: clean
-	rm -rf ../../addins/embench-iot/logs/
+	rm -rf $(embench_dir)/logs/
 
 # riscv64-unknown-elf-gcc -O2 -g -nostartfiles -I/home/harris/riscv-wally/addins/embench-iot/support -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/boards/ri5cyverilator -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/chips/generic -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32 -DCPU_MHZ=1 -DWARMUP_HEAT=1 -o main.o /home/harris/riscv-wally/addins/embench-iot/support/main.c

benchmarks/riscv-coremark/Makefile

@@ -0,0 +1,25 @@
+#cmbase=../../addins/coremark
+PORT_DIR = $(CURDIR)/riscv64-baremetal
+cmbase=coremark
+sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h  \
+        $(cmbase)/core_matrix.c $(cmbase)/core_state.c $(cmbase)/core_util.c \
+		$(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \
+		$(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c
+
+work/coremark.bare.riscv.elf.memfile: work/coremark.bare.riscv
+	riscv64-unknown-elf-objdump -D $< > $<.elf.objdump
+	riscv64-unknown-elf-elf2hex --bit-width 64 --input $< --output $@
+	extractFunctionRadix.sh $<.elf.objdump
+
+work/coremark.bare.riscv: $(sources) Makefile
+#	make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=/opt/riscv/riscv-gnu-toolchain XCFLAGS="-march=rv64imd -mabi=lp64d -mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-7-series -Ofast -funroll-all-loops -fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 -funroll-all-loops --param=uninlined-function-insns=8 -fno-tree-vrp -fwrapv -fno-toplevel-reorder --param=max-inline-insns-size=128 -fipa-pta"
+ # These flags were used by WD on CoreMark
+	make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=$(RISCV)/riscv-gnu-toolchain XCFLAGS="-march=rv64imd -mabi=lp64d -mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-7-series -Ofast -funroll-all-loops -fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 -funroll-all-loops --param=uninlined-function-insns=8 -fno-tree-vrp -fwrapv -fipa-pta " 
+# -fno-toplevel-reorder --param=max-inline-insns-size=128 " # adding this bit caused a compiler error
+	mkdir -p work/
+	mv $(cmbase)/coremark.bare.riscv work/
+
+.PHONY: clean
+
+clean:
+	rm -f work/*