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IFU and LSU now share the same busdp module.

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Ross Thompson 2022-01-31 16:25:41 -06:00
parent 86bac2a083
commit 1f0821da0d
1 changed files with 25 additions and 39 deletions
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62
pipelined/src/ifu/ifu.sv
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@ -169,16 +169,16 @@ module ifu (
// Memory // Memory
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
logic [`XLEN-1:0] AllInstrRawF;
assign InstrRawF = AllInstrRawF[31:0];
if (`MEM_IROM) begin : irom if (`MEM_IROM) begin : irom
logic [`XLEN-1:0] AllInstrRawF;
dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF), .IEUAdrE(PCNextFSpill), dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF), .IEUAdrE(PCNextFSpill),
.TrapM(1'b0), .FinalWriteDataM(), .TrapM(1'b0), .FinalWriteDataM(),
.ReadDataWordM(AllInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead), .ReadDataWordM(AllInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead),
.BusCommittedM(), .ReadDataWordMuxM(), .DCacheStallM(ICacheStallF), .BusCommittedM(), .ReadDataWordMuxM(), .DCacheStallM(ICacheStallF),
.DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess)); .DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess));
assign InstrRawF = AllInstrRawF[31:0];
end else begin : bus end else begin : bus
localparam integer WORDSPERLINE = `MEM_ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1; localparam integer WORDSPERLINE = `MEM_ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
@ -192,31 +192,24 @@ module ifu (
logic [LOGWPL-1:0] WordCount; logic [LOGWPL-1:0] WordCount;
logic SelUncachedAdr; logic SelUncachedAdr;
logic [LINELEN-1:0] ICacheMemWriteData; logic [LINELEN-1:0] ICacheMemWriteData;
logic ICacheBusAck;
logic [`PA_BITS-1:0] LocalIFUBusAdr; logic [`PA_BITS-1:0] LocalIFUBusAdr;
logic [`PA_BITS-1:0] ICacheBusAdr; logic [`PA_BITS-1:0] ICacheBusAdr;
logic ICacheBusAck;
genvar index; genvar index;
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
flopen #(`XLEN) fb(.clk(clk),
.en(IFUBusAck & IFUBusRead & (index == WordCount)),
.d(IFUBusHRDATA),
.q(ICacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
end
// select between dcache and direct from the BUS. Always selected if no dcache.
// handled in the busfsm.
mux2 #(32) UnCachedInstrMux(.d0(FinalInstrRawF[31:0]), .d1(ICacheMemWriteData[31:0]), .s(SelUncachedAdr), .y(InstrRawF));
assign LocalIFUBusAdr = SelUncachedAdr ? PCPF : ICacheBusAdr;
assign IFUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalIFUBusAdr;
busfsm #(WordCountThreshold, LOGWPL, `MEM_ICACHE) busdp #(WORDSPERLINE, LINELEN)
busfsm(.clk, .reset, .IgnoreRequest(ITLBMissF), busdp(.clk, .reset,
.LSURWM(2'b10), .DCacheFetchLine(ICacheFetchLine), .DCacheWriteLine(1'b0), .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(),
.LSUBusAck(IFUBusAck), .LSUBusRead(IFUBusRead), .LSUBusHWDATA(), .LSUBusSize(),
.CPUBusy, .CacheableM(CacheableF), .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr),
.BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead), .DCacheBusAck(ICacheBusAck), .ReadDataLineSetsM(), .DCacheFetchLine(ICacheFetchLine),
.BusCommittedM(), .SelUncachedAdr(SelUncachedAdr), .WordCount); .DCacheWriteLine(1'b0), .DCacheBusAck(ICacheBusAck),
.DCacheMemWriteData(ICacheMemWriteData), .LSUPAdrM(PCPF),
.FinalAMOWriteDataM(), .ReadDataWordM(FinalInstrRawF), .ReadDataWordMuxM(AllInstrRawF),
.IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF),
.BusStall, .BusCommittedM());
if(`MEM_ICACHE) begin : icache if(`MEM_ICACHE) begin : icache
logic [1:0] IFURWF; logic [1:0] IFURWF;
@ -225,29 +218,22 @@ module ifu (
cache #(.LINELEN(`ICACHE_LINELENINBITS), cache #(.LINELEN(`ICACHE_LINELENINBITS),
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
.NUMWAYS(`ICACHE_NUMWAYS), .DCACHE(0)) .NUMWAYS(`ICACHE_NUMWAYS), .DCACHE(0))
icache(.clk, .reset, .CPUBusy, .IgnoreRequest(ITLBMissF), .CacheMemWriteData(ICacheMemWriteData) , .CacheBusAck(ICacheBusAck), icache(.clk, .reset, .CPUBusy, .IgnoreRequest(ITLBMissF),
.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .ReadDataWord(FinalInstrRawF), .CacheMemWriteData(ICacheMemWriteData), .CacheBusAck(ICacheBusAck),
.CacheFetchLine(ICacheFetchLine), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
.CacheWriteLine(), .ReadDataWord(FinalInstrRawF), .CacheFetchLine(ICacheFetchLine),
.ReadDataLineSets(), .CacheWriteLine(), .ReadDataLineSets(),
.CacheMiss(ICacheMiss), .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
.CacheAccess(ICacheAccess),
.FinalWriteData('0), .FinalWriteData('0),
.RW(IFURWF), .RW(IFURWF),
.Atomic(2'b00), .Atomic(2'b00), .FlushCache(1'b0),
.FlushCache(1'b0),
.NextAdr(PCNextFSpill[11:0]), .NextAdr(PCNextFSpill[11:0]),
.PAdr(PCPF), .PAdr(PCPF),
.CacheCommitted(), .CacheCommitted(), .InvalidateCacheM(InvalidateICacheM));
.InvalidateCacheM(InvalidateICacheM));
end else begin : passthrough end else begin : passthrough
assign ICacheFetchLine = '0; assign {ICacheFetchLine, ICacheBusAdr, ICacheStallF, FinalInstrRawF} = '0;
assign ICacheBusAdr = '0; assign ICacheAccess = CacheableF; assign ICacheMiss = CacheableF;
assign ICacheStallF = '0;
assign FinalInstrRawF = '0;
assign ICacheAccess = CacheableF;
assign ICacheMiss = CacheableF;
end end
end end