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integrated peripheral testing into existing workflow

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bbracker 2021-04-08 15:31:39 -04:00
parent 005f838b8d
commit 1ee8feffe5
1 changed files with 4 additions and 4 deletions
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8
wally-pipelined/testbench/testbench-imperas.sv
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@ -29,7 +29,7 @@
module testbench(); module testbench();
parameter DEBUG = 0; parameter DEBUG = 0;
parameter TESTSBP = 0; parameter TESTSBP = 0;
parameter TESTSPERIPH = 1; parameter TESTSPERIPH = 0; // set to 0 for regression
logic clk; logic clk;
logic reset; logic reset;
@ -382,11 +382,11 @@ module testbench();
initial begin initial begin
if (`XLEN == 64) begin // RV64 if (`XLEN == 64) begin // RV64
if (TESTSBP) begin if (TESTSBP) begin
tests = testsBP64; tests = {testsBP64,tests64p};
end if (TESTSPERIPH) begin end if (TESTSPERIPH) begin
tests = tests64periph; tests = tests64periph;
end else begin end else begin
tests = {tests64i,tests64periph}; tests = {tests64i,tests64p,tests64periph};
if (`C_SUPPORTED) tests = {tests, tests64ic}; if (`C_SUPPORTED) tests = {tests, tests64ic};
else tests = {tests, tests64iNOc}; else tests = {tests, tests64iNOc};
if (`M_SUPPORTED) tests = {tests, tests64m}; if (`M_SUPPORTED) tests = {tests, tests64m};
@ -396,7 +396,7 @@ module testbench();
if (`MEM_VIRTMEM) tests = {tests64mmu, tests}; if (`MEM_VIRTMEM) tests = {tests64mmu, tests};
end end
//tests = {tests64a, tests}; //tests = {tests64a, tests};
tests = {tests, tests64p}; // tests = {tests, tests64p};
end else begin // RV32 end else begin // RV32
// *** add the 32 bit bp tests // *** add the 32 bit bp tests
if (TESTSPERIPH) begin if (TESTSPERIPH) begin