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Optimized gshare.
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Ross Thompson
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pipelined/src/ifu/optgshare.sv
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225
pipelined/src/ifu/optgshare.sv
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///////////////////////////////////////////
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// gsharePredictor.sv
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//
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// Written: Shreya Sanghai
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// Email: ssanghai@hmc.edu
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// Created: March 16, 2021
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// Modified:
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//
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// Purpose: Global History Branch predictor with parameterized global history register
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module optgshare
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#(parameter int k = 10
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)
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(input logic clk,
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input logic reset,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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// input logic [`XLEN-1:0] LookUpPC,
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output logic [1:0] DirPredictionF,
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output logic DirPredictionWrongE,
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// update
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input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
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input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
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input logic PCSrcE
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);
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logic MatchF, MatchD, MatchE, MatchM, MatchW;
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logic MatchNextX, MatchXF;
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logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE;
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logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM, NewDirPredictionW;
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logic [k-1:0] GHRF;
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logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW;
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logic [k-1:0] GHRNextF;
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logic [k:0] GHRNextD, GHRNextE, GHRNextM, GHRNextW;
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logic [k-1:0] IndexNextF, IndexF;
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logic [k-1:0] IndexD, IndexE, IndexM, IndexW;
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logic PCSrcM, PCSrcW;
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logic [`XLEN-1:0] PCW;
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logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF;
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logic [k+4:0] GHRNext, GHR;
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logic GHRUpdateEn;
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assign GHRUpdateEn = BranchInstrF | (DirPredictionWrongE & BranchInstrE) |
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FlushD | FlushE | FlushM | FlushW;
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// it doesn't work this way. Instead we need to see how many branch instructions are flushed.
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// then shift over by that amount.
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logic RemoveBrW, RemoveBrM, RemoveBrE, RemoveBrD, RemoveBrF, RemoveBrNextF;
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assign RemoveBrW = '0;
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assign RemoveBrM = BranchInstrM & FlushW;
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assign RemoveBrE = BranchInstrE & FlushM;
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assign RemoveBrD = BranchInstrD & FlushE;
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assign RemoveBrF = BranchInstrF & FlushD;
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assign RemoveBrNextF = BranchInstrF & FlushD;
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always_comb begin
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casez ({BranchInstrF, DirPredictionWrongE, RemoveBrF, RemoveBrD, RemoveBrE, RemoveBrM})
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6'b00_0000: GHRNext = GHR; // no change
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6'b00_0001: GHRNext = {GHR[k+4:k+1], GHR[k-1:0], 1'b0}; // RemoveBrM
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6'b0?_0010: GHRNext = {GHR[k+4:k+2], GHR[k:0], 1'b0}; // RemoveBrE
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6'b0?_0011: GHRNext = {GHR[k+4:k+2], GHR[k-1:0], 2'b0}; // RemoveBrE, RemoveBrM
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6'b00_0100: GHRNext = {GHR[k+4:k+2], GHR[k-1:0], 2'b0}; // RemoveBrD
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6'b00_0101: GHRNext = {GHR[k+4:k+3], GHR[k+1:0], 1'b0}; // RemoveBrD, RemoveBrM
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6'b0?_0110: GHRNext = {GHR[k+4:k+3], GHR[k+1], GHR[k-1:0], 2'b0}; // RemoveBrD, RemoveBrE
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6'b0?_0111: GHRNext = {GHR[k+4:k+3], GHR[k-1:0], 3'b0}; // RemoveBrD, RemoveBrE, RemoveBrM
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6'b?0_1000: GHRNext = {GHR[k+2:0], 2'b0}; // RemoveBrF,
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6'b?0_1001: GHRNext = {GHR[k+2:k+1], GHR[k-1:0], 3'b0}; // RemoveBrF, RemoveBrM
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6'b??_1010: GHRNext = {GHR[k+2], GHR[k:0], 3'b0}; // RemoveBrF, RemoveBrE
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6'b??_1011: GHRNext = {GHR[k+2], GHR[k-1:0], 4'b0}; // RemoveBrF, RemoveBrE, RemoveBrM
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6'b?0_1100: GHRNext = {GHR[k+1:0], 3'b0}; // RemoveBrF, RemoveBrD
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6'b?0_1101: GHRNext = {GHR[k+1], GHR[k-1:0], 4'b0}; // RemoveBrF, RemoveBrD, RemoveBrM
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6'b??_1110: GHRNext = {GHR[k:0], 4'b0}; // RemoveBrF, RemoveBrD, RemoveBrE
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6'b??_1111: GHRNext = {GHR[k-1:0], 5'b0}; // RemoveBrF, RemoveBrD, RemoveBrE, RemoveBrM
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6'b?1_0000: GHRNext = {PCSrcE, GHR[k+3:0]}; // Miss prediction, no branches to flushes
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6'b?1_0001: GHRNext = {PCSrcE, GHR[k+3:k], GHR[k-1:1], 1'b0}; // Miss prediction, branch in Memory stage dropped
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6'b?1_1100: GHRNext = {PCSrcE, GHR[k+1:0], 2'b00}; // Miss prediction, cannot have RemoveBrE
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6'b?1_1101: GHRNext = {PCSrcE, GHR[k+1], GHR[k-1:0], 3'b0}; // Miss prediction, cannot have RemoveBrE
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6'b10_0000: GHRNext = {DirPredictionF[1], GHR[k+4:1]};
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6'b10_0001: GHRNext = {DirPredictionF[1], GHR[k+4:k+1], GHR[k-1:1], 1'b0};
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6'b10_0010: GHRNext = {DirPredictionF[1], GHR[k+4:k+2], GHR[k:1], 1'b0};
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6'b10_0011: GHRNext = {DirPredictionF[1], GHR[k+4:k+2], GHR[k-1:1], 2'b0};
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6'b10_0100: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k+1:1], 1'b0};
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6'b10_0101: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k+1], GHR[k-1:1], 2'b0};
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6'b10_0110: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k], GHR[k-1:1], 2'b0};
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6'b10_0111: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k-1:1], 3'b0};
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default: GHRNext = GHR;
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endcase
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end
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flopenr #(k+5) GHRReg(clk, reset, GHRUpdateEn, GHRNext, GHR);
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logic [k-1:0] GHRNextF_temp, GHRF_temp;
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logic [k:0] GHRD_temp, GHRE_temp, GHRM_temp, GHRW_temp;
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logic GHRFExtra_temp;
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// these are also in the ieu controller. should create inputs.
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logic InstrValidF, InstrValidD, InstrValidE, InstrValidM, InstrValidW;
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flopenrc #(1) InstrValidFReg(clk, reset, FlushD, ~StallF, 1'b1, InstrValidF);
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flopenrc #(1) InstrValidDReg(clk, reset, FlushD, ~StallD, InstrValidF, InstrValidD);
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flopenrc #(1) InstrValidEReg(clk, reset, FlushE, ~StallE, InstrValidD, InstrValidE);
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flopenrc #(1) InstrValidMReg(clk, reset, FlushM, ~StallM, InstrValidE, InstrValidM);
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flopenrc #(1) InstrValidWReg(clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW);
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assign GHRNextF_temp = GHRNext[k+4:5];
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assign GHRF_temp = InstrValidF ? GHR[k+3:4] : GHRNextF_temp;
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assign GHRFExtra_temp = InstrValidF ? 1'b0 : GHR[k+4];
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assign GHRD_temp = InstrValidD ? GHR[k+3:3] : {GHRFExtra_temp, GHRF_temp};
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assign GHRE_temp = InstrValidE ? GHR[k+2:2] : GHRD_temp;
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assign GHRM_temp = InstrValidM ? GHR[k+1:1] : GHRE_temp;
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assign GHRW_temp = InstrValidW ? GHR[k:0] : GHRM_temp;
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assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
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assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
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assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
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assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
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assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
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assign IndexW = GHRW[k-1:0] ^ {PCW[k+1] ^ PCW[1], PCW[k:2]};
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ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
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.ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
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.ra1(IndexNextF),
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.rd1(TableDirPredictionF),
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.wa2(IndexW),
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.wd2(NewDirPredictionW),
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.we2(BranchInstrW & ~StallW & ~FlushW),
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.bwe2(1'b1));
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// if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
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// and then register for use in the Fetch stage.
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assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
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assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
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assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
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assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM);
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assign MatchW = BranchInstrW & (IndexNextF == IndexW);
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assign MatchNextX = MatchF | MatchD | MatchE | MatchM | MatchW;
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flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
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assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF :
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MatchD ? NewDirPredictionD :
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MatchE ? NewDirPredictionE :
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MatchM ? NewDirPredictionM :
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NewDirPredictionW;
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flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
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assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
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// DirPrediction pipeline
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flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
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flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
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// New prediction pipeline
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satCounter2 BPDirUpdateF(.BrDir(DirPredictionF[1]), .OldState(DirPredictionF), .NewState(NewDirPredictionF));
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flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD);
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satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
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flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM);
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flopenr #(2) NewPredWReg(clk, reset, ~StallW, NewDirPredictionM, NewDirPredictionW);
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// PCSrc pipeline
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flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
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flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW);
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// GHR pipeline
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assign GHRNextF = FlushD ? GHRNextD[k:1] :
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BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
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GHRF;
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flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
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assign GHRNextD = FlushD ? GHRNextE : {DirPredictionF[1], GHRF};
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flopenr #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
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assign GHRNextE = FlushE ? GHRNextM : GHRD;
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flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);
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assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE;
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assign GHRNextM = FlushM ? GHRNextW : GHRE;
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flopenr #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
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assign GHRNextW = FlushW ? GHRW : GHRM;
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flopenr #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW);
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assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
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flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
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endmodule
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