forked from Github_Repos/cvw
Progress towards the test bench flush.
This commit is contained in:
Ross Thompson
parent
f26d635614
commit
1cc258ade1
@ -7,37 +7,37 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func
|
|||||||
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
|
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
|
||||||
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
|
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
|
||||||
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
|
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
|
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
|
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
|
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
|
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
|
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
|
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall
|
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
|
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
|
||||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
|
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
|
||||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
|
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
|
||||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
|
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
|
||||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
|
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
|
||||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
|
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
|
||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
|
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
|
||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
|
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
|
||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
|
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
|
||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
|
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
|
||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
|
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
|
||||||
add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
|
add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
|
||||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
|
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
|
||||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
|
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
|
||||||
@ -250,25 +250,25 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cach
|
|||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[0]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[1]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[2]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[3]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
|
||||||
@ -280,7 +280,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU
|
|||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemAdrE
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemAdrE
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemPAdrM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemPAdrM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemPAdrW
|
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
||||||
@ -295,8 +294,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memo
|
|||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SRAMWordEnable
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SRAMWordEnable
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SetValidW
|
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SetDirtyW
|
|
||||||
add wave -noupdate -expand -group lsu -group old -color Gold /testbench/dut/hart/lsu/CurrState
|
add wave -noupdate -expand -group lsu -group old -color Gold /testbench/dut/hart/lsu/CurrState
|
||||||
add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/DisableTranslation
|
add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/DisableTranslation
|
||||||
add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemRWM
|
add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemRWM
|
||||||
@ -396,8 +393,8 @@ add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress
|
|||||||
add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
|
add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
|
||||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 4} {2797 ns} 0} {{Cursor 6} {3275 ns} 0} {{Cursor 8} {3905 ns} 0} {{Cursor 9} {4358 ns} 0} {{Cursor 10} {5007 ns} 0} {{Cursor 11} {57795 ns} 0}
|
WaveRestoreCursors {{Cursor 12} {57781 ns} 0} {{Cursor 13} {7061 ns} 0}
|
||||||
quietly wave cursor active 6
|
quietly wave cursor active 1
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 273
|
configure wave -valuecolwidth 273
|
||||||
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
||||||
@ -412,4 +409,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {57593 ns} {57969 ns}
|
WaveRestoreZoom {57704 ns} {58248 ns}
|
||||||
|
|||||||
2
wally-pipelined/src/cache/DCacheMem.sv
vendored
2
wally-pipelined/src/cache/DCacheMem.sv
vendored
@ -53,7 +53,7 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26
|
|||||||
genvar words;
|
genvar words;
|
||||||
|
|
||||||
generate
|
generate
|
||||||
for(words = 0; words < BLOCKLEN/`XLEN; words++) begin
|
for(words = 0; words < BLOCKLEN/`XLEN; words++) begin : word
|
||||||
sram1rw #(.DEPTH(`XLEN),
|
sram1rw #(.DEPTH(`XLEN),
|
||||||
.WIDTH(NUMLINES))
|
.WIDTH(NUMLINES))
|
||||||
CacheDataMem(.clk(clk),
|
CacheDataMem(.clk(clk),
|
||||||
|
|||||||
@ -44,14 +44,14 @@ module testbench();
|
|||||||
logic [31:0] InstrW;
|
logic [31:0] InstrW;
|
||||||
logic [`XLEN-1:0] meminit;
|
logic [`XLEN-1:0] meminit;
|
||||||
|
|
||||||
//string tests32mmu[] = '{
|
string tests32mmu[] = '{
|
||||||
//"rv32mmu/WALLY-MMU-SV32", "3000"
|
"rv32mmu/WALLY-MMU-SV32", "3000"
|
||||||
// };
|
};
|
||||||
|
|
||||||
//string tests64mmu[] = '{
|
string tests64mmu[] = '{
|
||||||
//"rv64mmu/WALLY-MMU-SV48", "3000",
|
"rv64mmu/WALLY-MMU-SV48", "3000",
|
||||||
//"rv64mmu/WALLY-MMU-SV39", "3000"
|
"rv64mmu/WALLY-MMU-SV39", "3000"
|
||||||
//};
|
};
|
||||||
|
|
||||||
|
|
||||||
string tests32f[] = '{
|
string tests32f[] = '{
|
||||||
@ -216,6 +216,7 @@ string tests32f[] = '{
|
|||||||
|
|
||||||
string tests64i[] = '{
|
string tests64i[] = '{
|
||||||
//"rv64i/WALLY-PIPELINE-100K", "f7ff0",
|
//"rv64i/WALLY-PIPELINE-100K", "f7ff0",
|
||||||
|
//"rv64i/WALLY-LOAD", "11bf0",
|
||||||
"rv64i/I-ADD-01", "3000",
|
"rv64i/I-ADD-01", "3000",
|
||||||
"rv64i/I-ADDI-01", "3000",
|
"rv64i/I-ADDI-01", "3000",
|
||||||
"rv64i/I-ADDIW-01", "3000",
|
"rv64i/I-ADDIW-01", "3000",
|
||||||
@ -286,7 +287,7 @@ string tests32f[] = '{
|
|||||||
"rv64i/WALLY-SLLI", "3000",
|
"rv64i/WALLY-SLLI", "3000",
|
||||||
"rv64i/WALLY-SRLI", "3000",
|
"rv64i/WALLY-SRLI", "3000",
|
||||||
"rv64i/WALLY-SRAI", "3000",
|
"rv64i/WALLY-SRAI", "3000",
|
||||||
"rv64i/WALLY-LOAD", "11bf0",
|
|
||||||
"rv64i/WALLY-JAL", "4000",
|
"rv64i/WALLY-JAL", "4000",
|
||||||
"rv64i/WALLY-JALR", "3000",
|
"rv64i/WALLY-JALR", "3000",
|
||||||
"rv64i/WALLY-STORE", "3000",
|
"rv64i/WALLY-STORE", "3000",
|
||||||
@ -513,6 +514,9 @@ string tests32f[] = '{
|
|||||||
logic HCLK, HRESETn;
|
logic HCLK, HRESETn;
|
||||||
logic [`XLEN-1:0] PCW;
|
logic [`XLEN-1:0] PCW;
|
||||||
|
|
||||||
|
logic DCacheFlushDone, DCacheFlushStart;
|
||||||
|
|
||||||
|
|
||||||
logic [`XLEN-1:0] debug;
|
logic [`XLEN-1:0] debug;
|
||||||
assign debug = dut.uncore.dtim.RAM[536872960];
|
assign debug = dut.uncore.dtim.RAM[536872960];
|
||||||
|
|
||||||
@ -540,9 +544,10 @@ string tests32f[] = '{
|
|||||||
else tests = {tests, tests64iNOc};
|
else tests = {tests, tests64iNOc};
|
||||||
if (`M_SUPPORTED) tests = {tests, tests64m};
|
if (`M_SUPPORTED) tests = {tests, tests64m};
|
||||||
if (`A_SUPPORTED) tests = {tests, tests64a};
|
if (`A_SUPPORTED) tests = {tests, tests64a};
|
||||||
//if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
|
if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
|
||||||
if (`F_SUPPORTED) tests = {tests64f, tests};
|
if (`F_SUPPORTED) tests = {tests64f, tests};
|
||||||
if (`D_SUPPORTED) tests = {tests64d, tests};
|
if (`D_SUPPORTED) tests = {tests64d, tests};
|
||||||
|
tests = {tests64i, tests};
|
||||||
end
|
end
|
||||||
//tests = {tests64a, tests};
|
//tests = {tests64a, tests};
|
||||||
end else begin // RV32
|
end else begin // RV32
|
||||||
@ -625,9 +630,9 @@ string tests32f[] = '{
|
|||||||
// check results
|
// check results
|
||||||
always @(negedge clk)
|
always @(negedge clk)
|
||||||
begin
|
begin
|
||||||
if (dut.hart.priv.EcallFaultM &&
|
if (DCacheFlushDone) begin
|
||||||
(dut.hart.ieu.dp.regf.rf[3] == 1 || (dut.hart.ieu.dp.regf.we3 && dut.hart.ieu.dp.regf.a3 == 3 && dut.hart.ieu.dp.regf.wd3 == 1))) begin
|
|
||||||
$display("Code ended with ecall with gp = 1");
|
$display("Code ended with ecall with gp = 1");
|
||||||
|
|
||||||
#60; // give time for instructions in pipeline to finish
|
#60; // give time for instructions in pipeline to finish
|
||||||
// clear signature to prevent contamination from previous tests
|
// clear signature to prevent contamination from previous tests
|
||||||
for(i=0; i<SIGNATURESIZE; i=i+1) begin
|
for(i=0; i<SIGNATURESIZE; i=i+1) begin
|
||||||
@ -706,6 +711,18 @@ string tests32f[] = '{
|
|||||||
.ProgramLabelMapFile(ProgramLabelMapFile));
|
.ProgramLabelMapFile(ProgramLabelMapFile));
|
||||||
end
|
end
|
||||||
|
|
||||||
|
assign DCacheFlushStart = dut.hart.priv.EcallFaultM &&
|
||||||
|
(dut.hart.ieu.dp.regf.rf[3] == 1 ||
|
||||||
|
(dut.hart.ieu.dp.regf.we3 &&
|
||||||
|
dut.hart.ieu.dp.regf.a3 == 3 &&
|
||||||
|
dut.hart.ieu.dp.regf.wd3 == 1));
|
||||||
|
|
||||||
|
DCacheFlushFSM DCacheFlushFSM(.clk(clk),
|
||||||
|
.reset(reset),
|
||||||
|
.start(DCacheFlushStart),
|
||||||
|
.done(DCacheFlushDone));
|
||||||
|
|
||||||
|
|
||||||
generate
|
generate
|
||||||
// initialize the branch predictor
|
// initialize the branch predictor
|
||||||
if (`BPRED_ENABLED == 1) begin : bpred
|
if (`BPRED_ENABLED == 1) begin : bpred
|
||||||
@ -959,5 +976,206 @@ module logging(
|
|||||||
|
|
||||||
always @(posedge clk)
|
always @(posedge clk)
|
||||||
if (HTRANS != 2'b00 && HADDR == 0)
|
if (HTRANS != 2'b00 && HADDR == 0)
|
||||||
$display("Warning: access to memory address 0\n");
|
$display("%t Warning: access to memory address 0\n", $realtime);
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
|
||||||
|
module DCacheFlushFSM
|
||||||
|
(input logic clk,
|
||||||
|
input logic reset,
|
||||||
|
input logic start,
|
||||||
|
output logic done);
|
||||||
|
|
||||||
|
localparam integer numlines = testbench.dut.hart.lsu.dcache.NUMLINES;
|
||||||
|
localparam integer numways = testbench.dut.hart.lsu.dcache.NUMWAYS;
|
||||||
|
localparam integer blockbytelen = testbench.dut.hart.lsu.dcache.BLOCKBYTELEN;
|
||||||
|
localparam integer numwords = testbench.dut.hart.lsu.dcache.BLOCKLEN/`XLEN;
|
||||||
|
localparam integer lognumlines = $clog2(numlines);
|
||||||
|
localparam integer logblockbytelen = $clog2(blockbytelen);
|
||||||
|
localparam integer lognumways = $clog2(numways);
|
||||||
|
localparam integer tagstart = lognumlines + logblockbytelen;
|
||||||
|
|
||||||
|
|
||||||
|
typedef enum {IDLE,
|
||||||
|
READ,
|
||||||
|
DONE} statetype;
|
||||||
|
|
||||||
|
statetype CurrState, NextState;
|
||||||
|
|
||||||
|
logic CountFlag;
|
||||||
|
logic CntEn;
|
||||||
|
|
||||||
|
logic [lognumways + lognumlines - 1 : 0] count, countNext;
|
||||||
|
|
||||||
|
flopenr #(lognumlines + lognumways)
|
||||||
|
FetchCountReg(.clk(clk),
|
||||||
|
.reset(reset),
|
||||||
|
.en(CntEn),
|
||||||
|
.d(countNext),
|
||||||
|
.q(count));
|
||||||
|
|
||||||
|
assign countNext = count + 1;
|
||||||
|
assign CountFlag = count == '1;
|
||||||
|
|
||||||
|
always_ff @(posedge clk, posedge reset) begin
|
||||||
|
if(reset) CurrState = IDLE;
|
||||||
|
else CurrState = NextState;
|
||||||
|
end
|
||||||
|
|
||||||
|
always_comb begin
|
||||||
|
case (CurrState)
|
||||||
|
IDLE: if(start) NextState = READ;
|
||||||
|
else NextState = IDLE;
|
||||||
|
READ: begin
|
||||||
|
force testbench.dut.hart.lsu.dcache.SRAMAdr = count;
|
||||||
|
if(CountFlag) begin
|
||||||
|
NextState = DONE;
|
||||||
|
end else begin
|
||||||
|
NextState = READ;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
DONE: begin
|
||||||
|
release testbench.dut.hart.lsu.dcache.SRAMAdr;
|
||||||
|
NextState = DONE;
|
||||||
|
end
|
||||||
|
default: NextState = IDLE;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
assign done = CurrState == DONE;
|
||||||
|
assign CntEn = CurrState == READ;
|
||||||
|
|
||||||
|
|
||||||
|
integer adr;
|
||||||
|
integer tag;
|
||||||
|
integer index;
|
||||||
|
integer way;
|
||||||
|
integer word;
|
||||||
|
|
||||||
|
logic dirty, valid;
|
||||||
|
|
||||||
|
always_comb begin
|
||||||
|
if (CurrState == READ) begin
|
||||||
|
assign index = count / numways;
|
||||||
|
assign way = count % numways;
|
||||||
|
assign tag = testbench.dut.hart.lsu.dcache.ReadTag[way];
|
||||||
|
assign dirty = testbench.dut.hart.lsu.dcache.Dirty[way];
|
||||||
|
assign valid = testbench.dut.hart.lsu.dcache.Valid[way];
|
||||||
|
assign adr = tag << (tagstart) + index;
|
||||||
|
|
||||||
|
$display("Index Way Tag V D %03x %d %016x %d %d %016x", index, way, tag, valid, dirty, adr);
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
|
||||||
|
task FlushDCache;
|
||||||
|
// takes no inputs or ouptuts but controls logics in the d cache.
|
||||||
|
|
||||||
|
// two possible implementations.
|
||||||
|
// 1) Can directly read/set the cache SRAM and the dtim.
|
||||||
|
// The problem here is the structure of the cache is
|
||||||
|
// not really easily known.
|
||||||
|
// 2) Use the cache's interface to read out blocks.
|
||||||
|
// The problem is we must do this over clock cycles.
|
||||||
|
// Honestly not sure which is easier.
|
||||||
|
// I don't think method 1 is possible because verilog cannot convert a string into
|
||||||
|
// an object's hierarchy or it is not possible because verilog cannot use
|
||||||
|
// variable index inside a generate block.
|
||||||
|
|
||||||
|
// path to d cache parameterization
|
||||||
|
//sim:/testbench/dut/hart/lsu/dcache/NUMLINES
|
||||||
|
//sim:/testbench/dut/hart/lsu/dcache/NUMWAYS
|
||||||
|
//sim:/testbench/dut/hart/lsu/dcache/BLOCKBYTELEN
|
||||||
|
|
||||||
|
//sim:/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData
|
||||||
|
//sim:/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData
|
||||||
|
//sim:/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits
|
||||||
|
//sim:/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits
|
||||||
|
|
||||||
|
static string GenericCacheDataMem = "testbench.dut.hart.lsu.dcache.CacheWays[%0d].MemWay.word[%0d].CacheDataMem.StoredData[%0d]";
|
||||||
|
static string GenericCacheTagMem = "testbench.dut.hart.lsu.dcache.CacheWays[%d].MemWay.CacheTagMem.StoredData[%d]";
|
||||||
|
static string GenericCacheValidMem = "testbench.dut.hart.lsu.dcache.CacheWays[%d].MemWay.ValidBits[%d]";
|
||||||
|
static string GenericCacheDirtyMem = "testbench.dut.hart.lsu.dcache.CacheWays[%d].MemWay.DirtyBits[%d]";
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
const integer numlines = testbench.dut.hart.lsu.dcache.NUMLINES;
|
||||||
|
const integer numways = testbench.dut.hart.lsu.dcache.NUMWAYS;
|
||||||
|
const integer blockbytelen = testbench.dut.hart.lsu.dcache.BLOCKBYTELEN;
|
||||||
|
const integer numwords = testbench.dut.hart.lsu.dcache.BLOCKLEN/`XLEN;
|
||||||
|
const integer lognumlines = $clog2(numlines);
|
||||||
|
const integer logblockbytelen = $clog2(blockbytelen);
|
||||||
|
const integer tagstart = lognumlines + logblockbytelen;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
// drive SRAMAdr
|
||||||
|
//sim:/testbench/dut/hart/lsu/dcache/SRAMAdr
|
||||||
|
// Read ReadTag and then mux out on the NUMWAYS
|
||||||
|
//sim:/testbench/dut/hart/lsu/dcache/ReadTag
|
||||||
|
//sim:/testbench/dut/hart/lsu/dcache/Valid
|
||||||
|
//sim:/testbench/dut/hart/lsu/dcache/Dirty
|
||||||
|
|
||||||
|
// if Valid and Dirty we write to dtim
|
||||||
|
|
||||||
|
logic [`PA_BITS-1:0] FullAdr;
|
||||||
|
|
||||||
|
integer adr;
|
||||||
|
integer tag;
|
||||||
|
integer index;
|
||||||
|
integer way;
|
||||||
|
integer word;
|
||||||
|
|
||||||
|
logic dirty, valid;
|
||||||
|
|
||||||
|
logic [`XLEN-1:0] value;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* -----\/----- EXCLUDED -----\/-----
|
||||||
|
$display("%d %d", tagstart, logblockbytelen);
|
||||||
|
|
||||||
|
|
||||||
|
for(adr = 0; adr < numways * numlines; adr++) begin
|
||||||
|
assign way = adr % numways;
|
||||||
|
assign index = adr / numways;
|
||||||
|
force testbench.dut.hart.lsu.dcache.SRAMAdr = index;
|
||||||
|
assign tag = testbench.dut.hart.lsu.dcache.ReadTag[way];
|
||||||
|
assign dirty = testbench.dut.hart.lsu.dcache.Dirty[way];
|
||||||
|
assign valid = testbench.dut.hart.lsu.dcache.Valid[way];
|
||||||
|
assign FullAdr = tag<<tagstart;
|
||||||
|
|
||||||
|
|
||||||
|
$display("Index Way Tag V D %03x %d %016x %d %d Full Adr %08x", index, way, tag, valid, dirty, FullAdr);
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
release testbench.dut.hart.lsu.dcache.SRAMAdr;
|
||||||
|
-----/\----- EXCLUDED -----/\----- */
|
||||||
|
static string path;
|
||||||
|
logic [`XLEN-1:0] CacheData;
|
||||||
|
|
||||||
|
assign value = testbench.dut.hart.lsu.dcache.CacheWays[0].MemWay.word[0].CacheDataMem.StoredData[0];
|
||||||
|
|
||||||
|
for(index = 0; index < numlines; index++) begin
|
||||||
|
for(way = 0; way < numways; way++) begin
|
||||||
|
for(word = 0; word < numwords; word++) begin
|
||||||
|
assign CacheData = testbench.dut.hart.lsu.dcache.CacheWays[0].MemWay.word[0].CacheDataMem.StoredData[index];
|
||||||
|
|
||||||
|
path = $sformatf(GenericCacheDataMem, way, word, index);
|
||||||
|
// I guess you cannot do this conversion.
|
||||||
|
//assign CacheData = path;
|
||||||
|
$display("%x", path);
|
||||||
|
$display(CacheData);
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
$display("%x", value);
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
endtask
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user