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TLB mux and swizzling cleanup

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This commit is contained in:
David Harris 2021-07-04 12:53:52 -04:00
parent 735f3b4217
commit 1b39481a16
1 changed files with 13 additions and 10 deletions
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23
wally-pipelined/src/mmu/tlb.sv
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@ -101,6 +101,7 @@ module tlb #(parameter ENTRY_BITS = 3,
logic [`VPN_BITS-1:0] VirtualPageNumber; logic [`VPN_BITS-1:0] VirtualPageNumber;
logic [`PPN_BITS-1:0] PhysicalPageNumber, PhysicalPageNumberMixed; logic [`PPN_BITS-1:0] PhysicalPageNumber, PhysicalPageNumberMixed;
logic [`PA_BITS-1:0] PhysicalAddressFull; logic [`PA_BITS-1:0] PhysicalAddressFull;
logic [`XLEN+1:0] VAExt;
// Sections of the page table entry // Sections of the page table entry
logic [7:0] PTEAccessBits; logic [7:0] PTEAccessBits;
@ -137,7 +138,7 @@ module tlb #(parameter ENTRY_BITS = 3,
endgenerate endgenerate
// Whether translation should occur // Whether translation should occur
assign Translate = (SvMode != `NO_TRANSLATE) & (PrivilegeModeW != `M_MODE) & ~ DisableTranslation; assign Translate = (SvMode != `NO_TRANSLATE) & (PrivilegeModeW != `M_MODE) & ~ DisableTranslation; // *** needs to account for mprv
// Determine how the TLB is currently being used // Determine how the TLB is currently being used
// Note that we use ReadAccess for both loads and instruction fetches // Note that we use ReadAccess for both loads and instruction fetches
@ -155,11 +156,8 @@ module tlb #(parameter ENTRY_BITS = 3,
tlbcam #(ENTRY_BITS, `VPN_BITS, `VPN_SEGMENT_BITS) tlbcam(.*); tlbcam #(ENTRY_BITS, `VPN_BITS, `VPN_SEGMENT_BITS) tlbcam(.*);
// unswizzle useful PTE bits // unswizzle useful PTE bits
assign PTE_U = PTEAccessBits[4]; assign {PTE_U, PTE_X, PTE_W, PTE_R} = PTEAccessBits[4:1];
assign PTE_X = PTEAccessBits[3];
assign PTE_W = PTEAccessBits[2];
assign PTE_R = PTEAccessBits[1];
// Check whether the access is allowed, page faulting if not. // Check whether the access is allowed, page faulting if not.
// *** We might not have S mode. // *** We might not have S mode.
generate generate
@ -198,17 +196,22 @@ module tlb #(parameter ENTRY_BITS = 3,
// Provide physical address only on TLBHits to cause catastrophic errors if // Provide physical address only on TLBHits to cause catastrophic errors if
// garbage address is used. // garbage address is used.
assign PhysicalAddressFull = (TLBHit) ? assign PhysicalAddressFull = (TLBHit) ? {PhysicalPageNumberMixed, PageOffset} : '0;
{PhysicalPageNumberMixed, PageOffset} : '0;
// Output the hit physical address if translation is currently on. // Output the hit physical address if translation is currently on.
generate /* generate
if (`XLEN == 32) begin if (`XLEN == 32) begin
VirtualAddressPALen = {2'b0, VirtualAddress};
mux2 #(`PA_BITS) addressmux({2'b0, VirtualAddress}, PhysicalAddressFull, Translate, PhysicalAddress); mux2 #(`PA_BITS) addressmux({2'b0, VirtualAddress}, PhysicalAddressFull, Translate, PhysicalAddress);
end else begin end else begin
VirtualAddressPALen = VirtualAddress[`PA_BITS-1:0];
mux2 #(`PA_BITS) addressmux(VirtualAddress[`PA_BITS-1:0], PhysicalAddressFull, Translate, PhysicalAddress); mux2 #(`PA_BITS) addressmux(VirtualAddress[`PA_BITS-1:0], PhysicalAddressFull, Translate, PhysicalAddress);
end end
endgenerate endgenerate*/
assign VAExt = {2'b00, VirtualAddress}; // extend length of virtual address if necessary for RV32
mux2 #(`PA_BITS) addressmux(VAExt[`PA_BITS-1:0], PhysicalAddressFull, Translate, PhysicalAddress);
assign TLBHit = CAMHit & TLBAccess; assign TLBHit = CAMHit & TLBAccess;
assign TLBMiss = ~TLBHit & ~TLBFlush & Translate & TLBAccess; assign TLBMiss = ~TLBHit & ~TLBFlush & Translate & TLBAccess;