forked from Github_Repos/cvw
moved ALUControlD into configurable block
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1e1ecaafb1
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@ -241,13 +241,13 @@ module controller(
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assign sltuD = (Funct3D == 3'b011);
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assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi
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assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
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assign ALUControlD = {(W64D | BW64D), SubArithD, ALUOpD};
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if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags
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bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE);
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assign RegWriteE = IEURegWriteE | FWriteIntE | BRegWriteE; // IRF register writes could come from IEU, BMU or FPU controllers
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assign SubArithD = (ALUOpD | BALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand
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assign ALUControlD = {(W64D | BW64D), SubArithD, ALUOpD};
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end else begin: bitmanipi
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assign ALUSelectD = Funct3D;
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assign ALUSelectE = Funct3E;
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@ -261,6 +261,7 @@ module controller(
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assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers
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assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD);
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assign ALUControlD = {W64D, SubArithD, ALUOpD};
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end
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// Fences
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