busybear: slight testbench update

2021-03-05 19:00:40 +00:00 · 2021-03-05 19:00:40 +00:00 · 1a11b60664
commit 1a11b60664
parent f48af209c4
1 changed files with 1 additions and 1 deletions
--- a/wally-pipelined/testbench/testbench-busybear.sv
+++ b/wally-pipelined/testbench/testbench-busybear.sv
@ -337,7 +337,7 @@ module testbench_busybear();
  logic [31:0] InstrMask;
  logic forcedInstr;
  logic [63:0] lastPCF;
-  always @(dut.PCF or dut.hart.ifu.InstrF) begin
+  always @(dut.PCF or dut.hart.ifu.InstrF or reset) begin
    if(~HWRITE) begin
    #3;
    if (~reset && dut.hart.ifu.InstrF[15:0] !== {16{1'bx}}) begin