forked from Github_Repos/cvw
Moved STATUS_FS_INT write to if statement to properly prioritize
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@ -156,8 +156,6 @@ module csrsr (
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STATUS_SBE <= #1 0;
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STATUS_UBE <= #1 0;
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end else if (~StallW) begin
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if (FRegWriteM | WriteFRMM | WriteFFLAGSM) STATUS_FS_INT <= #1 2'b11; // mark Float State dirty *** this should happen in M stage, be part of if/else;
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if (TrapM) begin
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// Update interrupt enables per Privileged Spec p. 21
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// y = PrivilegeModeW
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@ -211,6 +209,6 @@ module csrsr (
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STATUS_SPIE <= #1 `S_SUPPORTED & CSRWriteValM[5];
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STATUS_SIE <= #1 `S_SUPPORTED & CSRWriteValM[1];
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STATUS_UBE <= #1 CSRWriteValM[6] & `U_SUPPORTED & `BIGENDIAN_SUPPORTED;
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end
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end else if (FRegWriteM | WriteFRMM | WriteFFLAGSM) STATUS_FS_INT <= #1 2'b11;
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end
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endmodule
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