forked from Github_Repos/cvw
Cleaned up regfile x0 tied to gnd
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@ -44,8 +44,8 @@ module regfile #(parameter XLEN=32) (
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// reset is intended for simulation only, not synthesis
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always_ff @(negedge clk or posedge reset)
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if (reset) for(i=0; i<32; i++) rf[i] <= 0;
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else if (we3 & (a3 != 0)) rf[a3] <= wd3;
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if (reset) for(i=1; i<32; i++) rf[i] <= 0;
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else if (we3) rf[a3] <= wd3;
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assign #2 rd1 = (a1 != 0) ? rf[a1] : 0;
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assign #2 rd2 = (a2 != 0) ? rf[a2] : 0;
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