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TLB minor organization

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This commit is contained in:
David Harris 2021-07-04 14:30:56 -04:00
parent 7e22ae973e
commit 152923e552
1 changed files with 2 additions and 3 deletions
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wally-pipelined/src/mmu/tlb.sv
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@ -119,8 +119,9 @@ module tlb #(parameter ENTRY_BITS = 3,
// Whether the virtual address has a match in the CAM // Whether the virtual address has a match in the CAM
logic CAMHit; logic CAMHit;
// Grab the sv mode from SATP // Grab the sv mode from SATP and determine whether translation should occur
assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
assign Translate = (SvMode != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~ DisableTranslation;
// Decode the integer encoded WriteIndex into the one-hot encoded WriteLines // Decode the integer encoded WriteIndex into the one-hot encoded WriteLines
decoder #(ENTRY_BITS) writedecoder(WriteIndex, WriteLines); decoder #(ENTRY_BITS) writedecoder(WriteIndex, WriteLines);
@ -139,8 +140,6 @@ module tlb #(parameter ENTRY_BITS = 3,
end end
endgenerate endgenerate
// Whether translation should occur; ITLB ignores MPRVW
assign Translate = (SvMode != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~ DisableTranslation;
// Determine how the TLB is currently being used // Determine how the TLB is currently being used
// Note that we use ReadAccess for both loads and instruction fetches // Note that we use ReadAccess for both loads and instruction fetches