forked from Github_Repos/cvw
Added comments to lrsc module.
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@ -35,13 +35,14 @@ module lrsc(
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input logic reset,
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input logic reset,
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input logic StallW,
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input logic StallW,
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input logic MemReadM, // Memory read
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input logic MemReadM, // Memory read
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input logic [1:0] PreLSURWM,
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input logic [1:0] PreLSURWM, // Memory operation from the HPTW or IEU [1]: read, [0]: write
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output logic [1:0] LSURWM,
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output logic [1:0] LSURWM, // Memory operation after potential squash of SC
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input logic [1:0] LSUAtomicM,
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input logic [1:0] LSUAtomicM, // Atomic memory operaiton
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input logic [`PA_BITS-1:0] PAdrM, // from mmu to dcache
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input logic [`PA_BITS-1:0] PAdrM, // Physical memory address
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output logic SquashSCW
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output logic SquashSCW // Squash the store conditional by not allowing rf write
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);
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);
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// possible bug: *** double check if PreLSURWM needs to be flushed by ignorerequest.
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// Handle atomic load reserved / store conditional
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// Handle atomic load reserved / store conditional
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logic [`PA_BITS-1:2] ReservationPAdrW;
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logic [`PA_BITS-1:2] ReservationPAdrW;
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logic ReservationValidM, ReservationValidW;
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logic ReservationValidM, ReservationValidW;
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