Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Removed M suffix from interrupts because they are generated asynchronously to pipeline

Browse Source
This commit is contained in:
David Harris 2022-05-11 14:41:55 +00:00
parent 490902a655
commit 137b411bea
9 changed files with 27 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
pipelined/src/privileged/csr.sv
View File

@ -42,7 +42,7 @@ module csr #(parameter
input logic [31:0] InstrM, input logic [31:0] InstrM,
input logic [`XLEN-1:0] PCM, SrcAM, input logic [`XLEN-1:0] PCM, SrcAM,
input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, wfiM, InterruptM, input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, wfiM, InterruptM,
input logic TimerIntM, MExtIntM, SExtIntM, SwIntM, input logic TimerInt, MExtInt, SExtInt, SwInt,
input logic [63:0] MTIME_CLINT, input logic [63:0] MTIME_CLINT,
input logic InstrValidM, FRegWriteM, LoadStallD, input logic InstrValidM, FRegWriteM, LoadStallD,
input logic BPPredDirWrongM, input logic BPPredDirWrongM,
@ -134,7 +134,7 @@ module csr #(parameter
csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW,
.CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM,
.MExtIntM, .SExtIntM, .TimerIntM, .SwIntM, .MExtInt, .SExtInt, .TimerInt, .SwInt,
.MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW, .IP_REGW_writeable); .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW, .IP_REGW_writeable);
csrsr csrsr(.clk, .reset, .StallW, csrsr csrsr(.clk, .reset, .StallW,
.WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM, .WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM,

4
pipelined/src/privileged/csri.sv
View File

@ -42,7 +42,7 @@ module csri #(parameter
input logic CSRMWriteM, CSRSWriteM, input logic CSRMWriteM, CSRSWriteM,
input logic [`XLEN-1:0] CSRWriteValM, input logic [`XLEN-1:0] CSRWriteValM,
input logic [11:0] CSRAdrM, input logic [11:0] CSRAdrM,
(* mark_debug = "true" *) input logic MExtIntM, SExtIntM, TimerIntM, SwIntM, (* mark_debug = "true" *) input logic MExtInt, SExtInt, TimerInt, SwInt,
input logic [11:0] MIDELEG_REGW, input logic [11:0] MIDELEG_REGW,
output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
(* mark_debug = "true" *) output logic [11:0] IP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0 (* mark_debug = "true" *) output logic [11:0] IP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
@ -80,7 +80,7 @@ module csri #(parameter
else if (WriteMIEM) IE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields else if (WriteMIEM) IE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields
else if (WriteSIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (IE_REGW & 12'h888); // only S fields else if (WriteSIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (IE_REGW & 12'h888); // only S fields
assign IP_REGW = {MExtIntM,1'b0,SExtIntM|IP_REGW_writeable[9],1'b0,TimerIntM,1'b0,IP_REGW_writeable[5],1'b0,SwIntM,1'b0,IP_REGW_writeable[1],1'b0}; assign IP_REGW = {MExtInt,1'b0,SExtInt|IP_REGW_writeable[9],1'b0,TimerInt,1'b0,IP_REGW_writeable[5],1'b0,SwInt,1'b0,IP_REGW_writeable[1],1'b0};
assign MIP_REGW = IP_REGW; assign MIP_REGW = IP_REGW;
assign MIE_REGW = IE_REGW; assign MIE_REGW = IE_REGW;

4
pipelined/src/privileged/privileged.sv
View File

@ -55,7 +55,7 @@ module privileged (
input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD, input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD,
input logic LoadMisalignedFaultM, input logic LoadMisalignedFaultM,
input logic StoreAmoMisalignedFaultM, input logic StoreAmoMisalignedFaultM,
input logic TimerIntM, MExtIntM, SExtIntM, SwIntM, input logic TimerInt, MExtInt, SExtInt, SwInt,
input logic [63:0] MTIME_CLINT, input logic [63:0] MTIME_CLINT,
input logic [`XLEN-1:0] IEUAdrM, input logic [`XLEN-1:0] IEUAdrM,
input logic [4:0] SetFflagsM, input logic [4:0] SetFflagsM,
@ -161,7 +161,7 @@ module privileged (
.StallE, .StallM, .StallW, .StallE, .StallM, .StallW,
.InstrM, .PCM, .SrcAM, .InstrM, .PCM, .SrcAM,
.CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, .wfiM, .InterruptM, .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, .wfiM, .InterruptM,
.TimerIntM, .MExtIntM, .SExtIntM, .SwIntM, .TimerInt, .MExtInt, .SExtInt, .SwInt,
.MTIME_CLINT, .MTIME_CLINT,
.InstrValidM, .FRegWriteM, .LoadStallD, .InstrValidM, .FRegWriteM, .LoadStallD,
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM,

6
pipelined/src/uncore/clint.sv
View File

@ -43,7 +43,7 @@ module clint (
output logic [`XLEN-1:0] HREADCLINT, output logic [`XLEN-1:0] HREADCLINT,
output logic HRESPCLINT, HREADYCLINT, output logic HRESPCLINT, HREADYCLINT,
(* mark_debug = "true" *) output logic [63:0] MTIME, (* mark_debug = "true" *) output logic [63:0] MTIME,
output logic TimerIntM, SwIntM); output logic TimerInt, SwInt);
logic MSIP; logic MSIP;
@ -159,9 +159,9 @@ module clint (
end end
// Software interrupt when MSIP is set // Software interrupt when MSIP is set
assign SwIntM = MSIP; assign SwInt = MSIP;
// Timer interrupt when MTIME >= MTIMECMP // Timer interrupt when MTIME >= MTIMECMP
assign TimerIntM = ({1'b0, MTIME} >= {1'b0, MTIMECMP}); // unsigned comparison assign TimerInt = ({1'b0, MTIME} >= {1'b0, MTIMECMP}); // unsigned comparison
endmodule endmodule

6
pipelined/src/uncore/plic.sv
View File

@ -57,7 +57,7 @@ module plic (
input logic UARTIntr,GPIOIntr, input logic UARTIntr,GPIOIntr,
output logic [`XLEN-1:0] HREADPLIC, output logic [`XLEN-1:0] HREADPLIC,
output logic HRESPPLIC, HREADYPLIC, output logic HRESPPLIC, HREADYPLIC,
(* mark_debug = "true" *) output logic MExtIntM, SExtIntM); (* mark_debug = "true" *) output logic MExtInt, SExtInt);
logic memwrite, memread, initTrans; logic memwrite, memread, initTrans;
logic [23:0] entry, entryd; logic [23:0] entry, entryd;
@ -252,7 +252,7 @@ module plic (
end end
// is the max priority > threshold? // is the max priority > threshold?
// *** would it be any better to first priority encode maxPriority into binary and then ">" with threshold? // *** would it be any better to first priority encode maxPriority into binary and then ">" with threshold?
assign MExtIntM = |(threshMask[0] & priorities_with_irqs[0]); assign MExtInt = |(threshMask[0] & priorities_with_irqs[0]);
assign SExtIntM = |(threshMask[1] & priorities_with_irqs[1]); assign SExtInt = |(threshMask[1] & priorities_with_irqs[1]);
endmodule endmodule

12
pipelined/src/uncore/uncore.sv
View File

@ -55,7 +55,7 @@ module uncore (
input logic [3:0] HSIZED, input logic [3:0] HSIZED,
input logic HWRITED, input logic HWRITED,
// peripheral pins // peripheral pins
output logic TimerIntM, SwIntM, MExtIntM, SExtIntM, output logic TimerInt, SwInt, MExtInt, SExtInt,
input logic [31:0] GPIOPinsIn, input logic [31:0] GPIOPinsIn,
output logic [31:0] GPIOPinsOut, GPIOPinsEn, output logic [31:0] GPIOPinsOut, GPIOPinsEn,
input logic UARTSin, input logic UARTSin,
@ -120,11 +120,11 @@ module uncore (
.HREADCLINT, .HREADCLINT,
.HRESPCLINT, .HREADYCLINT, .HRESPCLINT, .HREADYCLINT,
.MTIME(MTIME_CLINT), .MTIME(MTIME_CLINT),
.TimerIntM, .SwIntM); .TimerInt, .SwInt);
end else begin : clint end else begin : clint
assign MTIME_CLINT = 0; assign MTIME_CLINT = 0;
assign TimerIntM = 0; assign SwIntM = 0; assign TimerInt = 0; assign SwInt = 0;
end end
if (`PLIC_SUPPORTED == 1) begin : plic if (`PLIC_SUPPORTED == 1) begin : plic
plic plic( plic plic(
@ -133,10 +133,10 @@ module uncore (
.HWRITE, .HREADY, .HTRANS, .HWDATA, .HWRITE, .HREADY, .HTRANS, .HWDATA,
.UARTIntr, .GPIOIntr, .UARTIntr, .GPIOIntr,
.HREADPLIC, .HRESPPLIC, .HREADYPLIC, .HREADPLIC, .HRESPPLIC, .HREADYPLIC,
.MExtIntM, .SExtIntM); .MExtInt, .SExtInt);
end else begin : plic end else begin : plic
assign MExtIntM = 0; assign MExtInt = 0;
assign SExtIntM = 0; assign SExtInt = 0;
end end
if (`GPIO_SUPPORTED == 1) begin : gpio if (`GPIO_SUPPORTED == 1) begin : gpio
gpio gpio( gpio gpio(

4
pipelined/src/wally/wallypipelinedcore.sv
View File

@ -34,7 +34,7 @@
module wallypipelinedcore ( module wallypipelinedcore (
input logic clk, reset, input logic clk, reset,
// Privileged // Privileged
input logic TimerIntM, MExtIntM, SExtIntM, SwIntM, input logic TimerInt, MExtInt, SExtInt, SwInt,
input logic [63:0] MTIME_CLINT, input logic [63:0] MTIME_CLINT,
// Bus Interface // Bus Interface
input logic [`AHBW-1:0] HRDATA, input logic [`AHBW-1:0] HRDATA,
@ -331,7 +331,7 @@ module wallypipelinedcore (
.InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM, .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
.InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD, .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD,
.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
.TimerIntM, .MExtIntM, .SExtIntM, .SwIntM, .TimerInt, .MExtInt, .SExtInt, .SwInt,
.MTIME_CLINT, .MTIME_CLINT,
.IEUAdrM, .IEUAdrM,
.SetFflagsM, .SetFflagsM,

8
pipelined/src/wally/wallypipelinedsoc.sv
View File

@ -72,9 +72,9 @@ module wallypipelinedsoc (
// logic reset; // logic reset;
logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore
logic HRESP; logic HRESP;
logic TimerIntM, SwIntM; // from CLINT logic TimerInt, SwInt; // from CLINT
logic [63:0] MTIME_CLINT; // from CLINT to CSRs logic [63:0] MTIME_CLINT; // from CLINT to CSRs
logic MExtIntM,SExtIntM; // from PLIC logic MExtInt,SExtInt; // from PLIC
logic [2:0] HADDRD; logic [2:0] HADDRD;
logic [3:0] HSIZED; logic [3:0] HSIZED;
logic HWRITED; logic HWRITED;
@ -84,7 +84,7 @@ module wallypipelinedsoc (
// instantiate processor and memories // instantiate processor and memories
wallypipelinedcore core(.clk, .reset, wallypipelinedcore core(.clk, .reset,
.TimerIntM, .MExtIntM, .SExtIntM, .SwIntM, .TimerInt, .MExtInt, .SExtInt, .SwInt,
.MTIME_CLINT, .MTIME_CLINT,
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA,
.HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
@ -94,7 +94,7 @@ module wallypipelinedsoc (
uncore uncore(.HCLK, .HRESETn, .TIMECLK, uncore uncore(.HCLK, .HRESETn, .TIMECLK,
.HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED,
.TimerIntM, .SwIntM, .MExtIntM, .SExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, .TimerInt, .SwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT,
.HSELEXT, .HSELEXT,
.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK

6
pipelined/testbench/testbench-linux.sv
View File

@ -140,9 +140,9 @@ module testbench;
`define PRIV_BASE dut.core.priv.priv `define PRIV_BASE dut.core.priv.priv
`define PRIV `PRIV_BASE.privmodereg.q `define PRIV `PRIV_BASE.privmodereg.q
`define CSR_BASE `PRIV_BASE.csr `define CSR_BASE `PRIV_BASE.csr
`define MEIP `PRIV_BASE.MExtIntM `define MEIP `PRIV_BASE.MExtInt
`define SEIP `PRIV_BASE.SExtIntM `define SEIP `PRIV_BASE.SExtInt
`define MTIP `PRIV_BASE.TimerIntM `define MTIP `PRIV_BASE.TimerInt
`define HPMCOUNTER `CSR_BASE.counters.counters.HPMCOUNTER_REGW `define HPMCOUNTER `CSR_BASE.counters.counters.HPMCOUNTER_REGW
`define MEDELEG `CSR_BASE.csrm.deleg.MEDELEGreg.q `define MEDELEG `CSR_BASE.csrm.deleg.MEDELEGreg.q
`define MIDELEG `CSR_BASE.csrm.deleg.MIDELEGreg.q `define MIDELEG `CSR_BASE.csrm.deleg.MIDELEGreg.q