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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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This commit is contained in:
David Harris 2021-01-28 15:44:14 -05:00
commit 12c6006f07
2 changed files with 7 additions and 3 deletions
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2
wally-pipelined/regression/wally-busybear.do
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@ -130,6 +130,6 @@ add wave /testbench_busybear/InstrWName
#set DefaultRadix hexadecimal #set DefaultRadix hexadecimal
# #
#-- Run the Simulation #-- Run the Simulation
run 2640 run 3850
#run -all #run -all
##quit ##quit

8
wally-pipelined/testbench/testbench-busybear.sv
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@ -123,8 +123,12 @@ module testbench_busybear();
end end
scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected); scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected);
scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected); scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected);
if (writeDataExpected != WriteDataM) begin for(int i=0; i<8; i++) begin
$display("%t ps: WriteDataM does not equal writeDataExpected: %x, %x", $time, WriteDataM, writeDataExpected); if (ByteMaskM[i]) begin
if (writeDataExpected[i*8+7 -: 8] != WriteDataM[i*8+7 -: 8]) begin
$display("%t ps: WriteDataM does not equal writeDataExpected: %x, %x", $time, WriteDataM, writeDataExpected);
end
end
end end
if (writeAdrExpected != DataAdrM) begin if (writeAdrExpected != DataAdrM) begin
$display("%t ps: DataAdrM does not equal writeAdrExpected: %x, %x", $time, DataAdrM, writeAdrExpected); $display("%t ps: DataAdrM does not equal writeAdrExpected: %x, %x", $time, DataAdrM, writeAdrExpected);