forked from Github_Repos/cvw
		
	Working for all of rv64i now, but not compressed instructions
This commit is contained in:
		
							parent
							
								
									602271ff7b
								
							
						
					
					
						commit
						128278ea27
					
				@ -53,12 +53,12 @@ module hazard(
 | 
			
		||||
 | 
			
		||||
  assign BranchFlushDE = BPPredWrongE | RetM | TrapM;
 | 
			
		||||
 | 
			
		||||
  assign StallFCause = CSRWritePendingDEM & ~(BranchFlushDE) | ICacheStallF;
 | 
			
		||||
  assign StallFCause = CSRWritePendingDEM & ~(BranchFlushDE);
 | 
			
		||||
  assign StallDCause = (LoadStallD | MulDivStallD | CSRRdStallD) & ~(BranchFlushDE);    // stall in decode if instruction is a load/mul/csr dependent on previous
 | 
			
		||||
//  assign StallDCause = LoadStallD | MulDivStallD | CSRRdStallD;    // stall in decode if instruction is a load/mul/csr dependent on previous
 | 
			
		||||
  assign StallECause = 0;
 | 
			
		||||
  assign StallMCause = 0; 
 | 
			
		||||
  assign StallWCause = DataStall;
 | 
			
		||||
  assign StallWCause = DataStall | ICacheStallF;
 | 
			
		||||
 | 
			
		||||
  // Each stage stalls if the next stage is stalled or there is a cause to stall this stage.
 | 
			
		||||
  assign StallF = StallD | StallFCause;
 | 
			
		||||
 | 
			
		||||
		Loading…
	
		Reference in New Issue
	
	Block a user