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Working for all of rv64i now, but not compressed instructions

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Jarred Allen 2021-03-24 17:23:00 -04:00
parent 602271ff7b
commit 128278ea27
1 changed files with 2 additions and 2 deletions
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wally-pipelined/src/hazard/hazard.sv
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@ -53,12 +53,12 @@ module hazard(
assign BranchFlushDE = BPPredWrongE | RetM | TrapM; assign BranchFlushDE = BPPredWrongE | RetM | TrapM;
assign StallFCause = CSRWritePendingDEM & ~(BranchFlushDE) | ICacheStallF; assign StallFCause = CSRWritePendingDEM & ~(BranchFlushDE);
assign StallDCause = (LoadStallD | MulDivStallD | CSRRdStallD) & ~(BranchFlushDE); // stall in decode if instruction is a load/mul/csr dependent on previous assign StallDCause = (LoadStallD | MulDivStallD | CSRRdStallD) & ~(BranchFlushDE); // stall in decode if instruction is a load/mul/csr dependent on previous
// assign StallDCause = LoadStallD | MulDivStallD | CSRRdStallD; // stall in decode if instruction is a load/mul/csr dependent on previous // assign StallDCause = LoadStallD | MulDivStallD | CSRRdStallD; // stall in decode if instruction is a load/mul/csr dependent on previous
assign StallECause = 0; assign StallECause = 0;
assign StallMCause = 0; assign StallMCause = 0;
assign StallWCause = DataStall; assign StallWCause = DataStall | ICacheStallF;
// Each stage stalls if the next stage is stalled or there is a cause to stall this stage. // Each stage stalls if the next stage is stalled or there is a cause to stall this stage.
assign StallF = StallD | StallFCause; assign StallF = StallD | StallFCause;