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ram uses always rather than always_ff due to modelsim issue.

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Ross Thompson 2023-01-19 17:41:15 -06:00
parent 23ab178192
commit 117ff8163b
1 changed files with 5 additions and 3 deletions
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8
pipelined/src/generic/mem/ram1p1rwbe.sv
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@ -64,19 +64,21 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
end else begin: ram end else begin: ram
integer i; integer i;
// Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff.
// Therefore these always blocks use the older always @(posedge clk)
// Read // Read
always_ff @(posedge clk) always @(posedge clk)
if(ce) dout <= #1 RAM[addr]; if(ce) dout <= #1 RAM[addr];
// Write divided into part for bytes and part for extra msbs // Write divided into part for bytes and part for extra msbs
if(WIDTH >= 8) if(WIDTH >= 8)
always_ff @(posedge clk) always @(posedge clk)
if (ce & we) if (ce & we)
for(i = 0; i < WIDTH/8; i++) for(i = 0; i < WIDTH/8; i++)
if(bwe[i]) RAM[addr][i*8 +: 8] <= #1 din[i*8 +: 8]; if(bwe[i]) RAM[addr][i*8 +: 8] <= #1 din[i*8 +: 8];
if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
always_ff @(posedge clk) always @(posedge clk)
if (ce & we & bwe[WIDTH/8]) if (ce & we & bwe[WIDTH/8])
RAM[addr][WIDTH-1:WIDTH-WIDTH%8] <= #1 din[WIDTH-1:WIDTH-WIDTH%8]; RAM[addr][WIDTH-1:WIDTH-WIDTH%8] <= #1 din[WIDTH-1:WIDTH-WIDTH%8];
end end