Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

pipelined/src/ebu/ahblite.sv

@@ -64,7 +64,7 @@ module ahblite (
   // AHB-Lite external signals
   (* mark_debug = "true" *) input logic HREADY, HRESP,
   (* mark_debug = "true" *) output logic HCLK, HRESETn,
-  (* mark_debug = "true" *) output logic [31:0] HADDR, // *** one day switch to a different bus that supports the full physical address
+  (* mark_debug = "true" *) output logic [`PA_BITS-1:0] HADDR, // *** one day switch to a different bus that supports the full physical address
   (* mark_debug = "true" *) output logic [`AHBW-1:0] HWDATA,
    output logic [`XLEN/8-1:0] HWSTRB,
   (* mark_debug = "true" *) output logic HWRITE, 
@@ -74,7 +74,6 @@ module ahblite (
   (* mark_debug = "true" *) output logic [1:0] HTRANS,
   (* mark_debug = "true" *) output logic HMASTLOCK,
   // Delayed signals for writes
-  (* mark_debug = "true" *) output logic [2:0] HADDRD,
   (* mark_debug = "true" *) output logic [3:0] HSIZED,
   (* mark_debug = "true" *) output logic HWRITED
 );
@@ -82,6 +81,7 @@ module ahblite (
   typedef enum logic [1:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype;
   statetype BusState, NextBusState;
   logic LSUGrant;
+  logic [2:0] HADDRD;
  
   assign HCLK = clk;
   assign HRESETn = ~reset;
@@ -113,15 +113,15 @@ module ahblite (
 
   //  LSU/IFU mux: choose source of access
   assign #1 LSUGrant = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE);
-  assign HADDR = LSUGrant ? LSUHADDR[31:0] : IFUHADDR[31:0];
+  assign HADDR = LSUGrant ? LSUHADDR : IFUHADDR;
   assign HSIZE = LSUGrant ? {1'b0, LSUHSIZE[1:0]} : 3'b010; // Instruction reads are always 32 bits
   assign HBURST = LSUGrant ? LSUHBURST : IFUHBURST; // If doing memory accesses, use LSUburst, else use Instruction burst.
-  assign HPROT = 4'b0011; // not used; see Section 3.7
   assign HTRANS = LSUGrant ? LSUHTRANS : IFUHTRANS; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
+  assign HPROT = 4'b0011; // not used; see Section 3.7
   assign HMASTLOCK = 0; // no locking supported
   assign HWRITE = (NextBusState == MEMWRITE);
   // Byte mask for HWSTRB
-  swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HADDRD[2:0]), .ByteMask(HWSTRB));
+  swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HADDRD), .ByteMask(HWSTRB));
 
   // delay write data by one cycle for
   flopen #(`XLEN) wdreg(HCLK, (LSUBusAck | LSUBusInit), LSUHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN

pipelined/src/uncore/ahbapbbridge.sv

@@ -32,7 +32,7 @@
 module ahbapbbridge #(PERIPHS = 2) (
   input  logic             HCLK, HRESETn,
   input  logic [PERIPHS-1:0] HSEL,  
-  input  logic [31:0]      HADDR, 
+  input  logic [`PA_BITS-1:0]  HADDR, 
   input  logic [`XLEN-1:0] HWDATA,
   input  logic [`XLEN/8-1:0] HWSTRB,
   input  logic             HWRITE,
@@ -68,7 +68,7 @@ module ahbapbbridge #(PERIPHS = 2) (
   assign initTransSel = initTrans & |HSEL; // capture data and address if any of the peripherals are selected
 
   // delay AHB Address phase signals to align with AHB Data phase because APB expects them at the same time
-  flopen #(32) addrreg(HCLK, HREADY, HADDR, PADDR);
+  flopen #(32) addrreg(HCLK, HREADY, HADDR[31:0], PADDR);
   flopenr #(1) writereg(HCLK, ~HRESETn, HREADY, HWRITE, PWRITE); 
   flopenr #(PERIPHS) selreg(HCLK, ~HRESETn, HREADY, HSEL & {PERIPHS{initTrans}}, PSEL); 
   // PPROT[2:0] = {Data/InstrB, Secure, Privileged};

pipelined/src/uncore/ram_ahb.sv

@@ -33,7 +33,7 @@
 module ram_ahb #(parameter BASE=0, RANGE = 65535) (
   input  logic             HCLK, HRESETn, 
   input  logic             HSELRam,
-  input  logic [31:0]      HADDR,
+  input  logic [`PA_BITS-1:0]      HADDR,
   input  logic             HWRITE,
   input  logic             HREADY,
   input  logic [1:0]       HTRANS,
@@ -47,7 +47,7 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) (
   localparam OFFSET = $clog2(`XLEN/8);   
 
   logic [`XLEN/8-1:0] 		  ByteMask;
-  logic [31:0]        HADDRD, RamAddr;
+  logic [`PA_BITS-1:0]        HADDRD, RamAddr;
   logic				  initTrans;
   logic				  memwrite, memwriteD, memread;
   logic         nextHREADYRam;
@@ -59,7 +59,7 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) (
   assign memread = initTrans & ~HWRITE;
  
   flopenr #(1) memwritereg(HCLK, ~HRESETn, HREADY, memwrite, memwriteD); 
-  flopenr #(32)   haddrreg(HCLK, ~HRESETn, HREADY, HADDR, HADDRD);
+  flopenr #(`PA_BITS)   haddrreg(HCLK, ~HRESETn, HREADY, HADDR, HADDRD);
 
   // Stall on a read after a write because the RAM can't take both adddresses on the same cycle
   assign nextHREADYRam = ~(memwriteD & memread);
@@ -67,7 +67,7 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) (
   assign HRESPRam = 0; // OK
 
   // On writes or during a wait state, use address delayed by one cycle to sync RamAddr with HWDATA or hold stalled address
-  mux2 #(32) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr);
+  mux2 #(`PA_BITS) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr);
 
   // single-ported RAM
   bram1p1rw #(`XLEN/8, 8, ADDR_WIDTH, `FPGA)

pipelined/src/uncore/rom_ahb.sv

@@ -33,7 +33,7 @@
 module rom_ahb #(parameter BASE=0, RANGE = 65535) (
   input  logic             HCLK, HRESETn, 
   input  logic             HSELRom,
-  input  logic [31:0]      HADDR,
+  input  logic [`PA_BITS-1:0]  HADDR,
   input  logic             HREADY,
   input  logic [1:0]       HTRANS,
   output logic [`XLEN-1:0] HREADRom,

pipelined/src/uncore/uncore.sv

@@ -37,7 +37,7 @@ module uncore (
   // AHB Bus Interface
   input  logic             HCLK, HRESETn,
   input  logic             TIMECLK,
-  input  logic [31:0]      HADDR,
+  input  logic [`PA_BITS-1:0] HADDR,
   input  logic [`AHBW-1:0] HWDATA,
   input  logic [`XLEN/8-1:0] HWSTRB,
   input  logic             HWRITE,
@@ -93,7 +93,7 @@ module uncore (
   // Determine which region of physical memory (if any) is being accessed
   // Use a trimmed down portion of the PMA checker - only the address decoders
   // Set access types to all 1 as don't cares because the MMU has already done access checking
-  adrdecs adrdecs({{(`PA_BITS-32){1'b0}}, HADDR}, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions);
+  adrdecs adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions);
 
   // unswizzle HSEL signals
   assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0];

pipelined/src/wally/wallypipelinedcore.sv

@@ -40,7 +40,7 @@ module wallypipelinedcore (
    input logic [`AHBW-1:0]  HRDATA,
    input logic             HREADY, HRESP,
    output logic         HCLK, HRESETn,
-   output logic [31:0]         HADDR,
+   output logic [`PA_BITS-1:0] HADDR,
    output logic [`AHBW-1:0] HWDATA,
    output logic [`XLEN/8-1:0] HWSTRB,
    output logic         HWRITE,
@@ -311,8 +311,7 @@ module wallypipelinedcore (
  
      .HREADY, .HRESP, .HCLK, .HRESETn,
      .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
-     .HPROT, .HTRANS, .HMASTLOCK, .HADDRD, .HSIZED,
+     .HPROT, .HTRANS, .HMASTLOCK, .HSIZED, .HWRITED);
-     .HWRITED);
   end
 
   

pipelined/src/wally/wallypipelinedsoc.sv

@@ -46,7 +46,7 @@ module wallypipelinedsoc (
   output logic 		   HSELEXT,
   // outputs to external memory, shared with uncore memory
   output logic 		   HCLK, HRESETn,
-  output logic [31:0] 	   HADDR,
+  output logic [`PA_BITS-1:0] HADDR,
   output logic [`AHBW-1:0] HWDATA,
   output logic [`XLEN/8-1:0] HWSTRB,
   output logic 		   HWRITE,

pipelined/testbench/testbench-linux.sv

@@ -244,7 +244,7 @@ module testbench;
   logic             HCLK, HRESETn;
   logic             HREADY;
   logic 	    HSELEXT;
-  logic [31:0]      HADDR;
+  logic [`PA_BITS-1:0] HADDR;
   logic [`AHBW-1:0] HWDATA;
   logic [`XLEN/8-1:0] HWSTRB;
   logic             HWRITE;

pipelined/testbench/testbench.sv

@@ -53,7 +53,7 @@ logic [3:0] dummy;
 
   logic [`AHBW-1:0] HRDATAEXT;
   logic             HREADYEXT, HRESPEXT;
-  logic [31:0]      HADDR;
+  logic [`PA_BITS-1:0] HADDR;
   logic [`AHBW-1:0] HWDATA;
   logic [`XLEN/8-1:0] HWSTRB;
   logic             HWRITE;