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Now reports i cache and d cache memory accesses.

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This commit is contained in:
Ross Thompson 2023-03-27 23:44:50 -05:00
parent 5844ba8e71
commit 108ad671cf
1 changed files with 33 additions and 6 deletions
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39
testbench/testbench.sv
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@ -30,7 +30,8 @@
`define PrintHPMCounters 1
`define BPRED_LOGGER 1
`define INSTR_FETCH_ADDR_LOGGER 0
`define I_CACHE_ADDR_LOGGER 1
`define D_CACHE_ADDR_LOGGER 1
module testbench;
parameter DEBUG=0;
@ -550,7 +551,7 @@ logic [3:0] dummy;
end
if (`INSTR_FETCH_ADDR_LOGGER == 1) begin
if (`I_CACHE_ADDR_LOGGER == 1) begin
int file;
string LogFile;
logic resetD, resetEdge;
@ -563,15 +564,41 @@ end
always @(posedge clk) begin
if(resetEdge) $fwrite(file, "TRAIN\n");
if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
if(dut.core.StallD & ~dut.core.FlushD) begin
$fwrite(file, "%h R\n", dut.core.ifu.PCF);
if(~dut.core.StallD & ~dut.core.FlushD) begin
$fwrite(file, "%h R\n", dut.core.ifu.PCPF);
end
if(EndSample) $fwrite(file, "END %s\n", memfilename);
end
end
if (`D_CACHE_ADDR_LOGGER == 1) begin
int file;
string LogFile;
logic resetD, resetEdge;
flop #(1) ResetDReg(clk, reset, resetD);
assign resetEdge = ~reset & resetD;
initial begin
LogFile = $psprintf("DCache.log");
file = $fopen(LogFile, "w");
end
always @(posedge clk) begin
if(resetEdge) $fwrite(file, "TRAIN\n");
if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
if(~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
if(dut.core.lsu.bus.dcache.CacheRWM == 2'b10) begin
$fwrite(file, "%h R\n", dut.core.lsu.PAdrM);
end else if (dut.core.lsu.bus.dcache.CacheRWM == 2'b01) begin
$fwrite(file, "%h W\n", dut.core.lsu.PAdrM);
end else if (dut.core.lsu.bus.dcache.CacheAtomicM[1] == 1'b1) begin // *** This may change
$fwrite(file, "%h A\n", dut.core.lsu.PAdrM);
end else if (dut.core.lsu.bus.dcache.FlushDCache) begin
$fwrite(file, "%h F\n", dut.core.lsu.PAdrM);
end
end
if(EndSample) $fwrite(file, "END %s\n", memfilename);
end
end
if (`BPRED_SUPPORTED == 1) begin
if (`BPRED_LOGGER) begin
string direction;