forked from Github_Repos/cvw
Fixed bug with the btb's valid bit not beind held on a stall.
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@ -94,7 +94,7 @@ module btb
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end else if ((UpdateEn) & ~StallM & ~FlushM) begin
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end else if ((UpdateEn) & ~StallM & ~FlushM) begin
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ValidBits[PCEIndex] <= #1 |InstrClassE;
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ValidBits[PCEIndex] <= #1 |InstrClassE;
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end
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end
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TablePredValidF = ValidBits[PCNextFIndex];
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if(~StallF | reset) TablePredValidF = ValidBits[PCNextFIndex];
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end
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end
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assign PredValidF = MatchXF ? 1'b1 : TablePredValidF;
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assign PredValidF = MatchXF ? 1'b1 : TablePredValidF;
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