More verilator fixes, but bpred is broken

wally-pipelined/config/buildroot/wally-config.vh

@@ -37,7 +37,7 @@
 `define MISA (32'h0014112D)
 `define ZCSR_SUPPORTED 1
 `define ZCOUNTERS_SUPPORTED 1
-`define COUNTERS 31
+`define COUNTERS 32
 
 // Microarchitectural Features
 `define UARCH_PIPELINED 1

wally-pipelined/config/busybear/wally-config.vh

@@ -37,7 +37,7 @@
 `define MISA (32'h0014112D)
 `define ZCSR_SUPPORTED 1
 `define ZCOUNTERS_SUPPORTED 1
-`define COUNTERS 31
+`define COUNTERS 32
 
 // Microarchitectural Features
 `define UARCH_PIPELINED 1

wally-pipelined/config/coremark/wally-config.vh

@@ -36,7 +36,7 @@
 //`define MISA (32'h00000104)
 `define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12)
 `define ZCSR_SUPPORTED 1
-`define COUNTERS 31
+`define COUNTERS 32
 `define ZCOUNTERS_SUPPORTED 1
 
 // Microarchitectural Features

wally-pipelined/config/coremark_bare/wally-config.vh

@@ -36,7 +36,7 @@
 //`define MISA (32'h00000104)
 `define MISA (32'h00001104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0)
 `define ZCSR_SUPPORTED 1
-`define COUNTERS 31
+`define COUNTERS 32
 `define ZCOUNTERS_SUPPORTED 1
 
 // Microarchitectural Features

wally-pipelined/config/rv32ic/wally-config.vh

@@ -35,7 +35,7 @@
 
 `define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12)
 `define ZCSR_SUPPORTED 1
-`define COUNTERS 31
+`define COUNTERS 32
 `define ZCOUNTERS_SUPPORTED 1
 
 // Microarchitectural Features

wally-pipelined/config/rv64BP/wally-config.vh

@@ -37,7 +37,7 @@
 //`define MISA (32'h00000105)
 `define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
 `define ZCSR_SUPPORTED 1
-`define COUNTERS 31
+`define COUNTERS 32
 `define ZCOUNTERS_SUPPORTED 1
 
 // Microarchitectural Features

wally-pipelined/config/rv64ic/wally-config.vh

@@ -36,7 +36,7 @@
 // MISA RISC-V configuration per specification
 `define MISA (32'h00000104 | 0 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
 `define ZCSR_SUPPORTED 1
-`define COUNTERS 31
+`define COUNTERS 32
 `define ZCOUNTERS_SUPPORTED 1
 
 // Microarchitectural Features
@@ -67,6 +67,8 @@
 
 `define BOOTTIMBASE   32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
 `define BOOTTIMRANGE  32'h00003FFF
+//`define BOOTTIMBASE   32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
+//`define BOOTTIMRANGE  32'h00000FFF
 `define TIMBASE       32'h80000000
 `define TIMRANGE      32'h07FFFFFF
 `define CLINTBASE  32'h02000000

wally-pipelined/config/rv64icfd/wally-config.vh

@@ -36,7 +36,7 @@
 // MISA RISC-V configuration per specification
 `define MISA (32'h00000104 | 0 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
 `define ZCSR_SUPPORTED 1
-`define COUNTERS 31
+`define COUNTERS 32
 `define ZCOUNTERS_SUPPORTED 1
 
 // Microarchitectural Features
@@ -62,7 +62,7 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
-`define BOOTTIMBASE   32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
+`define BOOTTIMBASE   32'h00000000
 `define BOOTTIMRANGE  32'h00003FFF
 `define TIMBASE    32'h80000000
 // `define TIMRANGE   32'h0007FFFF

wally-pipelined/config/rv64imc/wally-config.vh

@@ -35,7 +35,7 @@
 // MISA RISC-V configuration per specification
 `define MISA (32'h00000104 | 0 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
 `define ZCSR_SUPPORTED 1
-`define COUNTERS 31
+ 31
 `define ZCOUNTERS_SUPPORTED 1
 
 // Microarchitectural Features

wally-pipelined/config/shared/wally-shared.vh

@@ -39,6 +39,14 @@
 //`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
 `define N_SUPPORTED 0
 
+
+// logarithm of XLEN, used for number of index bits to select
+//`define LOG_XLEN (`XLEN == 32 ? 5 : 6)
+
+// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
+`define PMPCFG_ENTRIES (`PMP_ENTRIES\8)
+
+
 // Disable spurious Verilator warnings
 
 /* verilator lint_off STMTDLY */

wally-pipelined/src/cache/ICacheCntrl.sv

@@ -156,7 +156,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
   // on spill we want to get the first 2 bytes of the next cache block.
   // the spill only occurs if the PCPF mod BlockByteLength == -2.  Therefore we can
   // simply add 2 to land on the next cache block.
-  assign PCSpillF = PCPF + 2'b10;
+  assign PCSpillF = PCPF + `XLEN'b10;
 
   // now we have to select between these three PCs
   assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextF; // *** don't like the stallf, but it is necessary
@@ -188,7 +188,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
 
   assign spill = PCPF[4:1] == 4'b1111 ? 1'b1 : 1'b0;
   assign hit = ICacheMemReadValid; // note ICacheMemReadValid is hit.
-  assign FetchCountFlag = FetchCount == FetchCountThreshold;
+  assign FetchCountFlag = (FetchCount == FetchCountThreshold);
   
   // Next state logic
   always_comb begin

wally-pipelined/src/ifu/ifu.sv

@@ -92,7 +92,8 @@ module ifu (
   logic             misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
   logic             PrivilegedChangePCM;
   logic             IllegalCompInstrD;
-  logic [`XLEN-1:0] PCPlusUpperF, PCPlus2or4F, PCW, PCLinkD, PCLinkM, PCNextPF, PCPF;
+  logic [`XLEN-1:0] PCPlus2or4F, PCW, PCLinkD, PCLinkM, PCNextPF, PCPF;
+  logic [`XLEN-3:0] PCPlusUpperF;
   logic             CompressedF;
   logic [31:0]      InstrRawD;
   localparam [31:0]      nop = 32'h00000013; // instruction for NOP
@@ -117,7 +118,7 @@ module ifu (
 
   // branch predictor signals
   logic 	          SelBPPredF;
-  logic [`XLEN-1:0] BPPredPCF, PCCorrectE, PCNext0F, PCNext1F, PCNext2F, PCNext3F;
+  logic [`XLEN-1:0] BPPredPCF, PCNext0F, PCNext1F, PCNext2F, PCNext3F;
   logic [4:0] 	    InstrClassD, InstrClassE;