Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

.gitignore

@@ -70,3 +70,4 @@ synthDC/*.svf
 synthDC/runs/
 synthDC/hdl
 /pipelined/regression/power.saif
+tests/fp/vectors/*.tv

fpga/constraints/constraints.xdc

@@ -3,7 +3,7 @@
 # mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
 # This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
 
-create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
+create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
 
 ##### GPI ####
 set_property PACKAGE_PIN BB24 [get_ports {GPI[0]}]

fpga/constraints/debug2.xdc

@@ -562,9 +562,9 @@ connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/core/lsu/
 
 
 create_debug_port u_ila_0 probe
-set_property port_width 56 [get_debug_ports u_ila_0/probe121]
+set_property port_width 64 [get_debug_ports u_ila_0/probe121]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe121]
-connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} ]]
+connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsoc/core/SrcAM[0]} {wallypipelinedsoc/core/SrcAM[1]} {wallypipelinedsoc/core/SrcAM[2]} {wallypipelinedsoc/core/SrcAM[3]} {wallypipelinedsoc/core/SrcAM[4]} {wallypipelinedsoc/core/SrcAM[5]} {wallypipelinedsoc/core/SrcAM[6]} {wallypipelinedsoc/core/SrcAM[7]} {wallypipelinedsoc/core/SrcAM[8]} {wallypipelinedsoc/core/SrcAM[9]} {wallypipelinedsoc/core/SrcAM[10]} {wallypipelinedsoc/core/SrcAM[11]} {wallypipelinedsoc/core/SrcAM[12]} {wallypipelinedsoc/core/SrcAM[13]} {wallypipelinedsoc/core/SrcAM[14]} {wallypipelinedsoc/core/SrcAM[15]} {wallypipelinedsoc/core/SrcAM[16]} {wallypipelinedsoc/core/SrcAM[17]} {wallypipelinedsoc/core/SrcAM[18]} {wallypipelinedsoc/core/SrcAM[19]} {wallypipelinedsoc/core/SrcAM[20]} {wallypipelinedsoc/core/SrcAM[21]} {wallypipelinedsoc/core/SrcAM[22]} {wallypipelinedsoc/core/SrcAM[23]} {wallypipelinedsoc/core/SrcAM[24]} {wallypipelinedsoc/core/SrcAM[25]} {wallypipelinedsoc/core/SrcAM[26]} {wallypipelinedsoc/core/SrcAM[27]} {wallypipelinedsoc/core/SrcAM[28]} {wallypipelinedsoc/core/SrcAM[29]} {wallypipelinedsoc/core/SrcAM[30]} {wallypipelinedsoc/core/SrcAM[31]} {wallypipelinedsoc/core/SrcAM[32]} {wallypipelinedsoc/core/SrcAM[33]} {wallypipelinedsoc/core/SrcAM[34]} {wallypipelinedsoc/core/SrcAM[35]} {wallypipelinedsoc/core/SrcAM[36]} {wallypipelinedsoc/core/SrcAM[37]} {wallypipelinedsoc/core/SrcAM[38]} {wallypipelinedsoc/core/SrcAM[39]} {wallypipelinedsoc/core/SrcAM[40]} {wallypipelinedsoc/core/SrcAM[41]} {wallypipelinedsoc/core/SrcAM[42]} {wallypipelinedsoc/core/SrcAM[43]} {wallypipelinedsoc/core/SrcAM[44]} {wallypipelinedsoc/core/SrcAM[45]} {wallypipelinedsoc/core/SrcAM[46]} {wallypipelinedsoc/core/SrcAM[47]} {wallypipelinedsoc/core/SrcAM[48]} {wallypipelinedsoc/core/SrcAM[49]} {wallypipelinedsoc/core/SrcAM[50]} {wallypipelinedsoc/core/SrcAM[51]} {wallypipelinedsoc/core/SrcAM[52]} {wallypipelinedsoc/core/SrcAM[53]} {wallypipelinedsoc/core/SrcAM[54]} {wallypipelinedsoc/core/SrcAM[55]} {wallypipelinedsoc/core/SrcAM[56]} {wallypipelinedsoc/core/SrcAM[57]} {wallypipelinedsoc/core/SrcAM[58]} {wallypipelinedsoc/core/SrcAM[59]} {wallypipelinedsoc/core/SrcAM[60]} {wallypipelinedsoc/core/SrcAM[61]} {wallypipelinedsoc/core/SrcAM[62]} {wallypipelinedsoc/core/SrcAM[63]}]]
 
 
 create_debug_port u_ila_0 probe
@@ -599,18 +599,18 @@ connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/core/lsu/
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe127]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe127]
-connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[63]} ]]
+connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[63]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe128]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe128]
-connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[63]} ]]
+connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe129]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe129]
-connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63]} ]]
+connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe130]
@@ -651,3 +651,70 @@ create_debug_port u_ila_0 probe
 set_property port_width 12 [get_debug_ports u_ila_0/probe137]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe137]
 connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncore/plic.plic/intPending[12]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 12 [get_debug_ports u_ila_0/probe138]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138]
+connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[0]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[1]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[2]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[3]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[4]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[5]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[6]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[7]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[8]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[9]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[10]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[11]}]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe139]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe139]
+connect_debug_port u_ila_0/probe139 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe140]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe140]
+connect_debug_port u_ila_0/probe140 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe141]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe141]
+connect_debug_port u_ila_0/probe141 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe142]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe142]
+connect_debug_port u_ila_0/probe142 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM} ]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 70 [get_debug_ports u_ila_0/probe143]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe143]
+connect_debug_port u_ila_0/probe143 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][10]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 3 [get_debug_ports u_ila_0/probe144]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144]
+connect_debug_port u_ila_0/probe144 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intPriority[10][0]} {wallypipelinedsoc/uncore/plic.plic/intPriority[10][1]} {wallypipelinedsoc/uncore/plic.plic/intPriority[10][2]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 10 [get_debug_ports u_ila_0/probe145]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe145]
+connect_debug_port u_ila_0/probe145 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[1]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[2]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[3]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[4]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[5]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[6]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[7]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[8]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[9]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[10]} ]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe146]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe146]
+connect_debug_port u_ila_0/probe146 [get_nets [list {wallypipelinedsoc/uncore/clint.clint/MTIME[0]} {wallypipelinedsoc/uncore/clint.clint/MTIME[1]} {wallypipelinedsoc/uncore/clint.clint/MTIME[2]} {wallypipelinedsoc/uncore/clint.clint/MTIME[3]} {wallypipelinedsoc/uncore/clint.clint/MTIME[4]} {wallypipelinedsoc/uncore/clint.clint/MTIME[5]} {wallypipelinedsoc/uncore/clint.clint/MTIME[6]} {wallypipelinedsoc/uncore/clint.clint/MTIME[7]} {wallypipelinedsoc/uncore/clint.clint/MTIME[8]} {wallypipelinedsoc/uncore/clint.clint/MTIME[9]} {wallypipelinedsoc/uncore/clint.clint/MTIME[10]} {wallypipelinedsoc/uncore/clint.clint/MTIME[11]} {wallypipelinedsoc/uncore/clint.clint/MTIME[12]} {wallypipelinedsoc/uncore/clint.clint/MTIME[13]} {wallypipelinedsoc/uncore/clint.clint/MTIME[14]} {wallypipelinedsoc/uncore/clint.clint/MTIME[15]} {wallypipelinedsoc/uncore/clint.clint/MTIME[16]} {wallypipelinedsoc/uncore/clint.clint/MTIME[17]} {wallypipelinedsoc/uncore/clint.clint/MTIME[18]} {wallypipelinedsoc/uncore/clint.clint/MTIME[19]} {wallypipelinedsoc/uncore/clint.clint/MTIME[20]} {wallypipelinedsoc/uncore/clint.clint/MTIME[21]} {wallypipelinedsoc/uncore/clint.clint/MTIME[22]} {wallypipelinedsoc/uncore/clint.clint/MTIME[23]} {wallypipelinedsoc/uncore/clint.clint/MTIME[24]} {wallypipelinedsoc/uncore/clint.clint/MTIME[25]} {wallypipelinedsoc/uncore/clint.clint/MTIME[26]} {wallypipelinedsoc/uncore/clint.clint/MTIME[27]} {wallypipelinedsoc/uncore/clint.clint/MTIME[28]} {wallypipelinedsoc/uncore/clint.clint/MTIME[29]} {wallypipelinedsoc/uncore/clint.clint/MTIME[30]} {wallypipelinedsoc/uncore/clint.clint/MTIME[31]} {wallypipelinedsoc/uncore/clint.clint/MTIME[32]} {wallypipelinedsoc/uncore/clint.clint/MTIME[33]} {wallypipelinedsoc/uncore/clint.clint/MTIME[34]} {wallypipelinedsoc/uncore/clint.clint/MTIME[35]} {wallypipelinedsoc/uncore/clint.clint/MTIME[36]} {wallypipelinedsoc/uncore/clint.clint/MTIME[37]} {wallypipelinedsoc/uncore/clint.clint/MTIME[38]} {wallypipelinedsoc/uncore/clint.clint/MTIME[39]} {wallypipelinedsoc/uncore/clint.clint/MTIME[40]} {wallypipelinedsoc/uncore/clint.clint/MTIME[41]} {wallypipelinedsoc/uncore/clint.clint/MTIME[42]} {wallypipelinedsoc/uncore/clint.clint/MTIME[43]} {wallypipelinedsoc/uncore/clint.clint/MTIME[44]} {wallypipelinedsoc/uncore/clint.clint/MTIME[45]} {wallypipelinedsoc/uncore/clint.clint/MTIME[46]} {wallypipelinedsoc/uncore/clint.clint/MTIME[47]} {wallypipelinedsoc/uncore/clint.clint/MTIME[48]} {wallypipelinedsoc/uncore/clint.clint/MTIME[49]} {wallypipelinedsoc/uncore/clint.clint/MTIME[50]} {wallypipelinedsoc/uncore/clint.clint/MTIME[51]} {wallypipelinedsoc/uncore/clint.clint/MTIME[52]} {wallypipelinedsoc/uncore/clint.clint/MTIME[53]} {wallypipelinedsoc/uncore/clint.clint/MTIME[54]} {wallypipelinedsoc/uncore/clint.clint/MTIME[55]} {wallypipelinedsoc/uncore/clint.clint/MTIME[56]} {wallypipelinedsoc/uncore/clint.clint/MTIME[57]} {wallypipelinedsoc/uncore/clint.clint/MTIME[58]} {wallypipelinedsoc/uncore/clint.clint/MTIME[59]} {wallypipelinedsoc/uncore/clint.clint/MTIME[60]} {wallypipelinedsoc/uncore/clint.clint/MTIME[61]} {wallypipelinedsoc/uncore/clint.clint/MTIME[62]} {wallypipelinedsoc/uncore/clint.clint/MTIME[63]} ]]
+
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe147]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe147]
+connect_debug_port u_ila_0/probe147 [get_nets [list {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[0]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[1]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[2]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[3]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[4]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[5]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[6]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[7]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[8]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[9]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[10]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[11]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[12]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[13]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[14]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[15]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[16]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[17]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[18]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[19]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[20]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[21]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[22]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[23]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[24]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[25]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[26]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[27]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[28]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[29]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[30]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[31]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[32]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[33]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[34]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[35]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[36]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[37]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[38]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[39]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[40]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[41]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[42]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[43]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[44]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[45]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[46]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[47]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[48]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[49]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[50]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[51]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[52]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[53]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[54]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[55]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[56]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[57]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[58]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[59]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[60]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[61]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[62]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[63]} ]]
+
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 12 [get_debug_ports u_ila_0/probe148]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe148]
+connect_debug_port u_ila_0/probe148 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe149]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe149]
+connect_debug_port u_ila_0/probe149 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63]} ]]

fpga/generator/wave_config.wcfg

@@ -0,0 +1,495 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="/home/ross/repos/riscv-wally/fpga/generator/WallyFPGA.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wdb" id="1">
+         <top_modules>
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
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+         <obj_property name="ObjectShortName">r_curr_state[3:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16</obj_property>
+         <obj_property name="ObjectShortName">i_ERROR_CRC16</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[11:0]</obj_property>
+      <obj_property name="ObjectShortName">IP_REGW_writeable[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM</obj_property>
+      <obj_property name="ObjectShortName">MExtIntM</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM</obj_property>
+      <obj_property name="ObjectShortName">SExtIntM</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM</obj_property>
+      <obj_property name="ObjectShortName">SwIntM</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM</obj_property>
+      <obj_property name="ObjectShortName">TimerIntM</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
+      <obj_property name="ObjectShortName">MEDELEG_REGW[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0]</obj_property>
+      <obj_property name="ObjectShortName">MIDELEG_REGW[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/clint.clint/MTIMECMP">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/clint.clint/MTIMECMP[63:0]</obj_property>
+      <obj_property name="ObjectShortName">MTIMECMP[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/clint.clint/MTIME">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/clint.clint/MTIME[63:0]</obj_property>
+      <obj_property name="ObjectShortName">MTIME[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/intEn[1]__0">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[10:1]</obj_property>
+      <obj_property name="ObjectShortName">intEn[1]__0[10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/intPriority[10]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/intPriority[10][2:0]</obj_property>
+      <obj_property name="ObjectShortName">intPriority[10][2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][1][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][2][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][3][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][4][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][5][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][6][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][7][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+</wave_config>

fpga/generator/xlnx_ddr4.tcl

@@ -41,7 +41,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
 			CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \
 			CONFIG.Reference_Clock {Differential} \
 			CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
-			CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {10} \
+			CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {35} \
 			CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
 			CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \
 			CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \

linux/bootmem.txt

@@ -0,0 +1,12 @@
+00001000: 00000297		auipc t0, 0		# t0 = 0x00001000
+00001004: 02828613		addi a2, t0,0x28	# a2 = 0x00001028
+00001008: f1402573		csrr a0, mhartid	# a0 = mhartid
+0000100c: 0202b583		ld a1, 32(t0) 		# a1 = 87000000 - device tree address
+00001010: 0182b283		ld t0, 24(t0)		# t0 = 80000000 - start of firmware
+00001014: 00028067		jr t0			# jump to firmware
+00001018: 0000000080000000			# firmware start address
+00001020: 0000000087000000			# flattened device tree load address
+00001028: 000000004942534f			# a2 points to this 8 dword data structure
+00001030: 0000000000000002
+00001038: 0000000080200000
+00001040: 0000000000000001

linux/buildroot-scripts/Makefile

@@ -19,10 +19,10 @@ disassemble:
 	# -cd ${DIS}/rootfs; cpio -id --nonmatching 'dev/console' < ../../rootfs.cpio
 
 ${DIS}/fw_jump.objdump: ${IMAGES}/fw_jump.elf
-	riscv64-unknown-elf-objdump -D ${IMAGES}/fw_jump.elf >> ${DIS}/fw_jump.objdump
+	riscv64-unknown-elf-objdump -S ${IMAGES}/fw_jump.elf >> ${DIS}/fw_jump.objdump
 
 ${DIS}/vmlinux.objdump: ${IMAGES}/vmlinux
-	riscv64-unknown-elf-objdump -D ${IMAGES}/vmlinux >> ${DIS}/vmlinux.objdump
+	riscv64-unknown-elf-objdump -S ${IMAGES}/vmlinux >> ${DIS}/vmlinux.objdump
 
 ${DIS}/vmlinux.objdump.addr: ${DIS}/vmlinux.objdump
 	-cd ${DIS}; extractFunctionRadix.sh vmlinux.objdump

pipelined/config/buildroot/wally-config.vh

@@ -40,6 +40,7 @@
 `define ZICSR_SUPPORTED 1
 `define ZIFENCEI_SUPPORTED 1
 `define ZICOUNTERS_SUPPORTED 1
+`define ZFH_SUPPORTED 0
 `define COUNTERS 32
 `define DESIGN_COMPILER 0
 

pipelined/config/fpga/wally-config.vh

@@ -41,7 +41,9 @@
 `define ZICSR_SUPPORTED 1
 `define ZIFENCEI_SUPPORTED 1
 `define ZICOUNTERS_SUPPORTED 1
+`define ZFH_SUPPORTED 0
 `define COUNTERS 32
+`define DESIGN_COMPILER 0
 
 // Microarchitectural Features
 `define UARCH_PIPELINED 1

pipelined/config/rv32e/wally-config.vh

@@ -43,6 +43,7 @@
 `define ZIFENCEI_SUPPORTED 0
 `define COUNTERS 0
 `define ZICOUNTERS_SUPPORTED 0
+`define ZFH_SUPPORTED 0
 
 // Microarchitectural Features
 `define UARCH_PIPELINED 1

pipelined/config/rv32gc/wally-config.vh

@@ -42,6 +42,7 @@
 `define ZIFENCEI_SUPPORTED 1
 `define COUNTERS 32
 `define ZICOUNTERS_SUPPORTED 1
+`define ZFH_SUPPORTED 0
 
 // Microarchitectural Features
 `define UARCH_PIPELINED 1

pipelined/config/rv32ia/wally-config.vh

@@ -0,0 +1,136 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// include shared configuration
+`include "wally-shared.vh"
+
+`define FPGA 0
+`define QEMU 0
+`define DESIGN_COMPILER 0
+
+// RV32 or RV64: XLEN = 32 or 64
+`define XLEN 32
+
+// IEEE 754 compliance
+`define IEEE754 0
+
+// IA
+`define MISA (32'h00000100 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 << 3 | 1 << 5)
+`define ZICSR_SUPPORTED 1
+`define ZIFENCEI_SUPPORTED 1
+`define COUNTERS 32
+`define ZICOUNTERS_SUPPORTED 1
+`define ZFH_SUPPORTED 0
+
+// Microarchitectural Features
+`define UARCH_PIPELINED 1
+`define UARCH_SUPERSCALR 0
+`define UARCH_SINGLECYCLE 0
+// *** replace with MEM_BUS
+`define DMEM `MEM_CACHE
+`define IMEM `MEM_CACHE
+`define DBUS 1
+`define IBUS 1
+`define VIRTMEM_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
+
+// TLB configuration.  Entries should be a power of 2
+`define ITLB_ENTRIES 32
+`define DTLB_ENTRIES 32
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+`define DCACHE_NUMWAYS 4
+`define DCACHE_WAYSIZEINBYTES 4096
+`define DCACHE_LINELENINBITS 256
+`define ICACHE_NUMWAYS 4
+`define ICACHE_WAYSIZEINBYTES 4096
+`define ICACHE_LINELENINBITS 256
+
+// Integer Divider Configuration
+// DIV_BITSPERCYCLE must be 1, 2, or 4
+`define DIV_BITSPERCYCLE 4
+
+// Legal number of PMP entries are 0, 16, or 64
+`define PMP_ENTRIES 64
+
+// Address space
+`define RESET_VECTOR 32'h80000000
+
+// Peripheral Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   34'h00001000 
+`define BOOTROM_RANGE  34'h00000FFF
+`define RAM_SUPPORTED 1'b1
+`define RAM_BASE       34'h80000000
+`define RAM_RANGE      34'h07FFFFFF
+`define EXT_MEM_SUPPORTED 1'b0
+`define EXT_MEM_BASE       34'h80000000
+`define EXT_MEM_RANGE      34'h07FFFFFF
+`define CLINT_SUPPORTED 1'b0
+`define CLINT_BASE  34'h02000000
+`define CLINT_RANGE 34'h0000FFFF
+`define GPIO_SUPPORTED 1'b0
+`define GPIO_BASE   34'h10060000
+`define GPIO_RANGE  34'h000000FF
+`define UART_SUPPORTED 1'b1
+`define UART_BASE   34'h10000000
+`define UART_RANGE  34'h00000007
+`define PLIC_SUPPORTED 1'b1
+`define PLIC_BASE   34'h0C000000
+`define PLIC_RANGE  34'h03FFFFFF
+`define SDC_SUPPORTED 1'b0
+`define SDC_BASE   34'h00012100
+`define SDC_RANGE  34'h0000001F
+
+// Bus Interface width
+`define AHBW 32
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+`define GPIO_LOOPBACK_TEST 1
+
+// Hardware configuration
+`define UART_PRESCALE 1
+
+// Interrupt configuration
+`define PLIC_NUM_SRC 10 
+// comment out the following if >=32 sources
+`define PLIC_NUM_SRC_LT_32
+`define PLIC_GPIO_ID 3
+`define PLIC_UART_ID 10
+
+`define TWO_BIT_PRELOAD "../config/rv32ia/twoBitPredictor.txt"
+`define BTB_PRELOAD "../config/rv32ia/BTBPredictor.txt"
+`define BPRED_ENABLED 1
+`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define TESTSBP 0
+
+`define REPLAY 0
+`define HPTW_WRITES_SUPPORTED 0

pipelined/config/rv32ic/wally-config.vh

@@ -42,6 +42,7 @@
 `define ZIFENCEI_SUPPORTED 0
 `define COUNTERS 32
 `define ZICOUNTERS_SUPPORTED 0
+`define ZFH_SUPPORTED 0
 
 // Microarchitectural Features
 `define UARCH_PIPELINED 1

pipelined/config/rv64BP/wally-config.vh

@@ -44,6 +44,7 @@
 `define ZIFENCEI_SUPPORTED 1
 `define COUNTERS 32
 `define ZICOUNTERS_SUPPORTED 1
+`define ZFH_SUPPORTED 0
 
 // Microarchitectural Features
 `define UARCH_PIPELINED 1

pipelined/config/rv64fp/wally-config.vh

@@ -43,6 +43,7 @@
 `define ZIFENCEI_SUPPORTED 1
 `define COUNTERS 32
 `define ZICOUNTERS_SUPPORTED 1
+`define ZFH_SUPPORTED 0
 
 /// Microarchitectural Features
 `define UARCH_PIPELINED 1

pipelined/config/rv64gc/wally-config.vh

@@ -43,6 +43,7 @@
 `define ZIFENCEI_SUPPORTED 1
 `define COUNTERS 32
 `define ZICOUNTERS_SUPPORTED 1
+`define ZFH_SUPPORTED 0
 
 /// Microarchitectural Features
 `define UARCH_PIPELINED 1

pipelined/config/rv64ia/wally-config.vh

@@ -0,0 +1,137 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// include shared configuration
+`include "wally-shared.vh"
+
+`define FPGA 0
+`define QEMU 0
+`define DESIGN_COMPILER 0
+
+// RV32 or RV64: XLEN = 32 or 64
+`define XLEN 64
+
+// IEEE 754 compliance
+`define IEEE754 0
+
+// MISA RISC-V configuration per specification IA
+`define MISA (32'h00000100 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 << 3 | 1 << 5)
+`define ZICSR_SUPPORTED 1
+`define ZIFENCEI_SUPPORTED 1
+`define COUNTERS 32
+`define ZICOUNTERS_SUPPORTED 1
+`define ZFH_SUPPORTED 0
+
+/// Microarchitectural Features
+`define UARCH_PIPELINED 1
+`define UARCH_SUPERSCALR 0
+`define UARCH_SINGLECYCLE 0
+`define DMEM `MEM_CACHE
+`define IMEM `MEM_CACHE
+`define DBUS 1
+`define IBUS 1
+`define VIRTMEM_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
+
+// TLB configuration.  Entries should be a power of 2
+`define ITLB_ENTRIES 32
+`define DTLB_ENTRIES 32
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+`define DCACHE_NUMWAYS 4
+`define DCACHE_WAYSIZEINBYTES 4096
+`define DCACHE_LINELENINBITS 256
+`define ICACHE_NUMWAYS 4
+`define ICACHE_WAYSIZEINBYTES 4096
+`define ICACHE_LINELENINBITS 256
+
+// Integer Divider Configuration
+// DIV_BITSPERCYCLE must be 1, 2, or 4
+`define DIV_BITSPERCYCLE 4
+
+// Legal number of PMP entries are 0, 16, or 64
+`define PMP_ENTRIES 64
+
+// Address space
+`define RESET_VECTOR 64'h0000000080000000
+
+// Bus Interface width
+`define AHBW 64
+
+// Peripheral Physiccal Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+
+// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
+`define BOOTROM_RANGE  56'h00000FFF
+`define RAM_SUPPORTED 1'b1
+`define RAM_BASE       56'h80000000
+`define RAM_RANGE      56'h7FFFFFFF
+`define EXT_MEM_SUPPORTED 1'b0
+`define EXT_MEM_BASE       56'h80000000
+`define EXT_MEM_RANGE      56'h07FFFFFF
+`define CLINT_SUPPORTED 1'b1
+`define CLINT_BASE  56'h02000000
+`define CLINT_RANGE 56'h0000FFFF
+`define GPIO_SUPPORTED 1'b1
+`define GPIO_BASE   56'h10060000
+`define GPIO_RANGE  56'h000000FF
+`define UART_SUPPORTED 1'b1
+`define UART_BASE   56'h10000000
+`define UART_RANGE  56'h00000007
+`define PLIC_SUPPORTED 1'b1
+`define PLIC_BASE   56'h0C000000
+`define PLIC_RANGE  56'h03FFFFFF
+`define SDC_SUPPORTED 1'b0
+`define SDC_BASE   56'h00012100
+`define SDC_RANGE  56'h0000001F
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+`define GPIO_LOOPBACK_TEST 1
+
+// Hardware configuration
+`define UART_PRESCALE 1
+
+// Interrupt configuration
+`define PLIC_NUM_SRC 10
+// comment out the following if >=32 sources
+`define PLIC_NUM_SRC_LT_32
+`define PLIC_GPIO_ID 3
+`define PLIC_UART_ID 10
+
+`define TWO_BIT_PRELOAD "../config/rv64ia/twoBitPredictor.txt"
+`define BTB_PRELOAD "../config/rv64ia/BTBPredictor.txt"
+`define BPRED_ENABLED 1
+`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define TESTSBP 0
+
+`define REPLAY 0
+`define HPTW_WRITES_SUPPORTED 0

pipelined/config/rv64ic/wally-config.vh

@@ -43,6 +43,7 @@
 `define ZIFENCEI_SUPPORTED 0
 `define COUNTERS 32
 `define ZICOUNTERS_SUPPORTED 0
+`define ZFH_SUPPORTED 0
 
 // Microarchitectural Features
 `define UARCH_PIPELINED 1

pipelined/config/shared/wally-shared.vh

@@ -50,10 +50,6 @@
 // Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
 `define PMPCFG_ENTRIES (`PMP_ENTRIES/8)
 
-
-// Floating-point half-precision
-`define ZFH_SUPPORTED 0
-
 // Floating point constants for Quad, Double, Single, and Half precisions
 `define Q_LEN 128
 `define Q_NE 15

pipelined/fpu-testfloat/FMA/tbgen/tb.sv

@@ -1,332 +0,0 @@
-
-`include "../../../config/old/rv64icfd/wally-config.vh"
-
-// `define FLEN (`Q_SUPPORTED ? 128 : `D_SUPPORTED ? 64 : `F_SUPPORTED ? 32 : 16)
-// `define NE   (`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : `F_SUPPORTED ? 8 : 5)
-// `define NF   (`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : `F_SUPPORTED ? 23 : 10)
-// `define FMT (`Q_SUPPORTED ? 3 : `D_SUPPORTED ? 1 : `F_SUPPORTED ? 0 : 2)
-// `define BIAS (`Q_SUPPORTED ? 16383 : `D_SUPPORTED ? 1023 : `F_SUPPORTED ? 127 : 15)
-// `define XLEN 64
-// `define IEEE754 1
-`define Q_SUPPORTED 1
-// `define D_SUPPORTED 0
-// `define F_SUPPORTED 0
-`define H_SUPPORTED 0
-`define FPSIZES ((`Q_SUPPORTED&`D_SUPPORTED&`F_SUPPORTED&`H_SUPPORTED) ? 4 : (`Q_SUPPORTED&`D_SUPPORTED&`F_SUPPORTED) | (`Q_SUPPORTED&`D_SUPPORTED&`H_SUPPORTED) | (`Q_SUPPORTED&`F_SUPPORTED&`H_SUPPORTED) | (`D_SUPPORTED&`F_SUPPORTED&`H_SUPPORTED) ? 3 : (`Q_SUPPORTED&`D_SUPPORTED) | (`Q_SUPPORTED&`F_SUPPORTED) | (`Q_SUPPORTED&`H_SUPPORTED) | (`D_SUPPORTED&`F_SUPPORTED) | (`D_SUPPORTED&`H_SUPPORTED) | (`F_SUPPORTED&`H_SUPPORTED) ? 2 : 1)
-`define LEN1  ((`D_SUPPORTED & (`FLEN !== 64)) ? 64   : (`F_SUPPORTED & (`FLEN !== 32)) ? 32  : 16)
-`define NE1   ((`D_SUPPORTED & (`FLEN !== 64)) ? 11   : (`F_SUPPORTED & (`FLEN !== 32)) ? 8   : 5)
-`define NF1   ((`D_SUPPORTED & (`FLEN !== 64)) ? 52   : (`F_SUPPORTED & (`FLEN !== 32)) ? 23  : 10)
-`define FMT1  ((`D_SUPPORTED & (`FLEN !== 64)) ? 1    : (`F_SUPPORTED & (`FLEN !== 32)) ? 0   : 2)
-`define BIAS1 ((`D_SUPPORTED & (`FLEN !== 64)) ? 1023 : (`F_SUPPORTED & (`FLEN !== 32)) ? 127 : 15)
-`define LEN2  ((`F_SUPPORTED & (`LEN1 !== 32)) ? 32   : 16)
-`define NE2   ((`F_SUPPORTED & (`LEN1 !== 32)) ? 8    : 5)
-`define NF2   ((`F_SUPPORTED & (`LEN1 !== 32)) ? 23   : 10)
-`define FMT2  ((`F_SUPPORTED & (`LEN1 !== 32)) ? 0    : 2)
-`define BIAS2 ((`F_SUPPORTED & (`LEN1 !== 32)) ? 127  : 15)
-`define LEN3 16
-`define NE3 5//make constants for the constants ie 11/8/5 ect
-`define NF3 10 // always support less hten max - maybe halfs
-`define FMT3 2
-`define BIAS3 15
-module testbench3();
-
- logic [31:0] errors=0;
- logic [31:0] vectornum=0;
- logic [`FLEN*4+7:0] testvectors[6133248:0];
-
-//  logic 	[63:0]		X,Y,Z;
- logic 	[`FLEN-1:0]		ans;
- logic 	[7:0]	 	flags;
- logic 	[2:0]		FrmE;
- logic	[`FPSIZES/3:0]			FmtE;
- logic  [`FLEN-1:0]      FMAResM;
- logic  [4:0]       FMAFlgM;
-logic 	[2:0]		FOpCtrlE;
-logic 		[2*`NF+1:0]		ProdManE; 
-logic 		[3*`NF+5:0]		AlignedAddendE;	
-logic 		[`NE+1:0]		ProdExpE; 
-logic 					AddendStickyE;
-logic 					KillProdE; 
-
-logic wnan;
-logic ansnan, clk;
-
-
-assign FOpCtrlE = 3'b0;  
-
-// nearest even - 000
-// twords zero - 001
-// down - 010
-// up - 011
-// nearest max mag - 100  
-assign FrmE = 3'b010;
-assign FmtE = (`FPSIZES/3+1)'(1);
-
-    logic  [`FLEN-1:0] X, Y, Z;
-    // logic         FmtE;
-    // logic  [2:0]  FOpCtrlE;
-    logic        XSgnE, YSgnE, ZSgnE;
-    logic [`NE-1:0] XExpE, YExpE, ZExpE;
-    logic [`NF:0] XManE, YManE, ZManE;
-    logic XNormE;
-    logic XExpMaxE;
-    logic XNaNE, YNaNE, ZNaNE;
-    logic XSNaNE, YSNaNE, ZSNaNE;
-    logic XDenormE, YDenormE, ZDenormE;
-    logic XZeroE, YZeroE, ZZeroE;
-    logic [`NE-1:0] BiasE;
-    logic XInfE, YInfE, ZInfE;
-    logic [`FLEN-1:0]    Addend; // value to add (Z or zero)
-    logic           YExpMaxE, ZExpMaxE, Mult;  // input exponent all 1s
-
-	assign Mult = 1'b0;
-  unpacking unpacking(.*);
-
-// assign	wnan = XNaNE|YNaNE|ZNaNE; 
-// assign	ansnan = FmtE ? &ans[`FLEN-2:`NF] && |ans[`NF-1:0] : &ans[30:23] && |ans[22:0]; 
- 
-    if (`FPSIZES === 1) begin
-      assign ansnan = &ans[`FLEN-2:`NF]&(|ans[`NF-1:0]);
-      assign wnan = &FMAResM[`FLEN-2:`NF]&(|FMAResM[`NF-1:0]);
-    end else if (`FPSIZES === 2) begin                  
-      assign ansnan = FmtE ? &ans[`FLEN-2:`NF]&(|ans[`NF-1:0]) : &ans[`LEN1-2:`NF1]&(|ans[`NF1-1:0]);
-      assign wnan = FmtE ? &FMAResM[`FLEN-2:`NF]&(|FMAResM[`NF-1:0]) : &FMAResM[`LEN1-2:`NF1]&(|FMAResM[`NF1-1:0]);
-    end else if (`FPSIZES === 3) begin
-        always_comb begin
-            case (FmtE)
-                `FMT: begin                  
-                  assign ansnan = &ans[`FLEN-2:`NF]&(|ans[`NF-1:0]);
-                  assign wnan = &FMAResM[`FLEN-2:`NF]&(|FMAResM[`NF-1:0]);
-
-                end
-                `FMT1: begin                    
-                  assign ansnan = &ans[`LEN1-2:`NF1]&(|ans[`NF1-1:0]);
-                  assign wnan = &FMAResM[`LEN1-2:`NF1]&(|FMAResM[`NF1-1:0]);
-
-                end
-                `FMT2: begin
-                    assign ansnan = &ans[`LEN2-2:`NF2]&(|ans[`NF2-1:0]);
-                    assign wnan = &FMAResM[`LEN2-2:`NF2]&(|FMAResM[`NF2-1:0]);
-                end
-                default: begin
-                    assign ansnan = 0;
-                    assign wnan = 0;
-                end
-            endcase
-        end
-
-    end else begin
-        always_comb begin
-            case (FmtE)
-                `FMT: begin                  
-                  assign ansnan = &ans[`FLEN-2:`NF]&(|ans[`NF-1:0]);
-                  assign wnan = &FMAResM[`FLEN-2:`NF]&(|FMAResM[`NF-1:0]);
-
-                end
-                `FMT1: begin                    
-                  assign ansnan = &ans[`LEN1-2:`NF1]&(|ans[`NF1-1:0]);
-                  assign wnan = &FMAResM[`LEN1-2:`NF1]&(|FMAResM[`NF1-1:0]);
-
-                end
-                `FMT2: begin
-                    assign ansnan = &ans[`LEN2-2:`NF2]&(|ans[`NF2-1:0]);
-                    assign wnan = &FMAResM[`LEN2-2:`NF2]&(|FMAResM[`NF2-1:0]);
-                end
-                `FMT3: begin
-                    assign ansnan = &ans[`LEN3-2:`NF3]&(|ans[`NF3-1:0]);
-                    assign wnan = &FMAResM[`LEN3-2:`NF3]&(|FMAResM[`NF3-1:0]);
-                end
-            endcase
-        end
-    end
- // instantiate device under test
-
-    logic [3*`NF+5:0]	SumE, SumM;       
-    logic 			    InvZE, InvZM;
-    logic 			    NegSumE, NegSumM;
-    logic 			    ZSgnEffE, ZSgnEffM;
-    logic 			    PSgnE, PSgnM;
-    logic [$clog2(3*`NF+7)-1:0]			NormCntE, NormCntM;
-    
-    fma1 fma1 (.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE,
-                 .XDenormE, .YDenormE, .ZDenormE,  .XZeroE, .YZeroE, .ZZeroE,
-                .FOpCtrlE, .FmtE, .SumE, .NegSumE, .InvZE, .NormCntE, .ZSgnEffE, .PSgnE,
-                .ProdExpE, .AddendStickyE, .KillProdE); 
-fma2 UUT2(.XSgnM(XSgnE), .YSgnM(YSgnE), .XExpM(XExpE), .YExpM(YExpE), .ZExpM(ZExpE), .XManM(XManE), .YManM(YManE), .ZManM(ZManE), .XNaNM(XNaNE), .YNaNM(YNaNE), .ZNaNM(ZNaNE), .XZeroM(XZeroE), .YZeroM(YZeroE), .ZZeroM(ZZeroE), .XInfM(XInfE), .YInfM(YInfE), .ZInfM(ZInfE), .XSNaNM(XSNaNE), .YSNaNM(YSNaNE), .ZSNaNM(ZSNaNE),
-              //  .FSrcXE, .FSrcYE, .FSrcZE, .FSrcXM, .FSrcYM, .FSrcZM, 
-                .KillProdM(KillProdE), .AddendStickyM(AddendStickyE), .ProdExpM(ProdExpE), .SumM(SumE), .NegSumM(NegSumE), .InvZM(InvZE), .NormCntM(NormCntE), .ZSgnEffM(ZSgnEffE), .PSgnM(PSgnE),
-               .FmtM(FmtE), .FrmM(FrmE), .FMAFlgM, .FMAResM, .Mult);
-
-
- // produce clock
- always
- begin
- clk = 1; #5; clk = 0; #5;
- end
- // at start of test, load vectors
- // and pulse reset
- initial
- begin
-    $readmemh("testFloatNoSpace", testvectors);
- end
- // apply test vectors on rising edge of clk
-always @(posedge clk)
- begin
-  #1; 
-  if (`FPSIZES === 3 | `FPSIZES === 4) begin
-    if (FmtE==2'b11) {X, Y, Z, ans, flags} = testvectors[vectornum];
-    else if (FmtE==2'b01)	begin	  
-      X = {{`FLEN-64{1'b1}}, testvectors[vectornum][263:200]};
-      Y = {{`FLEN-64{1'b1}}, testvectors[vectornum][199:136]};
-      Z = {{`FLEN-64{1'b1}}, testvectors[vectornum][135:72]};
-      ans = {{`FLEN-64{1'b1}}, testvectors[vectornum][71:8]};
-      flags = testvectors[vectornum][7:0];
-    end
-    else if (FmtE==2'b00)	begin	  
-      X = {{`FLEN-32{1'b1}}, testvectors[vectornum][135:104]};
-      Y = {{`FLEN-32{1'b1}}, testvectors[vectornum][103:72]};
-      Z = {{`FLEN-32{1'b1}}, testvectors[vectornum][71:40]};
-      ans = {{`FLEN-32{1'b1}}, testvectors[vectornum][39:8]};
-      flags = testvectors[vectornum][7:0];
-    end
-    else	begin	  
-      X = {{`FLEN-16{1'b1}}, testvectors[vectornum][71:56]};
-      Y = {{`FLEN-16{1'b1}}, testvectors[vectornum][55:40]};
-      Z = {{`FLEN-16{1'b1}}, testvectors[vectornum][39:24]};
-      ans = {{`FLEN-16{1'b1}}, testvectors[vectornum][23:8]};
-      flags = testvectors[vectornum][7:0];
-    end
-  end
-  else begin
-    if (FmtE==1'b1) {X, Y, Z, ans, flags} = testvectors[vectornum];
-    else if (FmtE==1'b0)	begin	  
-      X = {{`FLEN-`LEN1{1'b1}}, testvectors[vectornum][8+4*(`LEN1)-1:8+3*(`LEN1)]};
-      Y = {{`FLEN-`LEN1{1'b1}}, testvectors[vectornum][8+3*(`LEN1)-1:8+2*(`LEN1)]};
-      Z = {{`FLEN-`LEN1{1'b1}}, testvectors[vectornum][8+2*(`LEN1)-1:8+(`LEN1)]};
-      ans = {{`FLEN-`LEN1{1'b1}}, testvectors[vectornum][8+(`LEN1-1):8]};
-      flags = testvectors[vectornum][7:0];
-    end
-  end
- end
- // check results on falling edge of clk
-  always @(negedge clk) begin
-      if (`FPSIZES === 1 | `FPSIZES === 2) begin
-        if((FmtE==1'b1) & (FMAFlgM !== flags[4:0] || (!wnan && (FMAResM !== ans)) || (wnan && ansnan && ~((XNaNE && (FMAResM[`FLEN-2:0] === {X[`FLEN-2:`NF],1'b1,X[`NF-2:0]})) || (YNaNE && (FMAResM[`FLEN-2:0] === {Y[`FLEN-2:`NF],1'b1,Y[`NF-2:0]}))  || (ZNaNE && (FMAResM[`FLEN-2:0] === {Z[`FLEN-2:`NF],1'b1,Z[`NF-2:0]})) || (FMAResM[`FLEN-2:0] === ans[`FLEN-2:0]))))) begin
-        //  fp = $fopen("/home/kparry/riscv-wally/pipelined/src/fpu/FMA/tbgen/results.dat","w");
-        // if((FmtE==1'b1) & (FMAFlgM !== flags[4:0] || (FMAResM !== ans))) begin
-              $display( "%h %h %h %h %h %h %h  Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags);
-          if(XDenormE) $display( "xdenorm ");
-          if(YDenormE) $display( "ydenorm ");
-          if(ZDenormE) $display( "zdenorm ");
-          if(FMAFlgM[4] !== 0) $display( "invld ");
-          if(FMAFlgM[2] !== 0) $display( "ovrflw ");
-          if(FMAFlgM[1] !== 0) $display( "unflw ");
-          if(FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] === 0) $display( "FMAResM=-inf ");
-          if(~FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] === 0) $display( "FMAResM=+inf ");
-          if(FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] !== 0 && ~FMAResM[`NF-1]) $display( "FMAResM=sigNaN ");
-          if(FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] !== 0 && FMAResM[`NF-1]) $display( "FMAResM=qutNaN ");
-          if(ans[`FLEN] && ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] === 0) $display( "ans=-inf ");
-          if(~ans[`FLEN] && ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] === 0) $display( "ans=+inf ");
-          if(ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] !== 0 && ~ans[`NF-1]) $display( "ans=sigNaN ");
-          if(ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] !== 0 && ans[`NF-1]) $display( "ans=qutNaN ");
-              errors = errors + 1;
-          //if (errors === 10)
-          $stop;
-          end
-          if((FmtE==1'b0)&(FMAFlgM !== flags[4:0] || (!wnan && (FMAResM !== ans)) || (wnan && ansnan && ~(((XNaNE && (FMAResM[`LEN1-2:0] === {X[`LEN1-2:`NF1],1'b1,X[`NF1-2:0]})) || (YNaNE && (FMAResM[`LEN1-2:0] === {Y[`LEN1-2:`NF1],1'b1,Y[`NF1-2:0]}))  || (ZNaNE && (FMAResM[`LEN1-2:0] === {Z[`LEN1-2:`NF1],1'b1,Z[`NF1-2:0]})) || (FMAResM[`LEN1-2:0] === ans[`LEN1-2:0]))) ))) begin
-              $display( "%h %h %h %h %h %h %h  Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags);
-          if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm ");
-          if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm ");
-          if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm ");
-          if(FMAFlgM[4] !== 0) $display( "invld ");
-          if(FMAFlgM[2] !== 0) $display( "ovrflw ");
-          if(FMAFlgM[1] !== 0) $display( "unflw ");
-          if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN ");
-          if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN ");
-          if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN ");
-          if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN ");
-              errors = errors + 1;
-        // if (errors === 9)
-          $stop;
-          end
- end else begin
-   
-        if((FmtE==2'b11) & (FMAFlgM !== flags[4:0] || (!wnan && (FMAResM !== ans)) || (wnan && ansnan && ~((XNaNE && (FMAResM[`FLEN-2:0] === {X[`FLEN-2:`NF],1'b1,X[`NF-2:0]})) || (YNaNE && (FMAResM[`FLEN-2:0] === {Y[`FLEN-2:`NF],1'b1,Y[`NF-2:0]}))  || (ZNaNE && (FMAResM[`FLEN-2:0] === {Z[`FLEN-2:`NF],1'b1,Z[`NF-2:0]})) || (FMAResM[`FLEN-2:0] === ans[`FLEN-2:0]))))) begin
-        //  fp = $fopen("/home/kparry/riscv-wally/pipelined/src/fpu/FMA/tbgen/results.dat","w");
-        // if((FmtE==1'b1) & (FMAFlgM !== flags[4:0] || (FMAResM !== ans))) begin
-              $display( "%h %h %h %h %h %h %h  Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags);
-          if(XDenormE) $display( "xdenorm ");
-          if(YDenormE) $display( "ydenorm ");
-          if(ZDenormE) $display( "zdenorm ");
-          if(FMAFlgM[4] !== 0) $display( "invld ");
-          if(FMAFlgM[2] !== 0) $display( "ovrflw ");
-          if(FMAFlgM[1] !== 0) $display( "unflw ");
-          if(FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] === 0) $display( "FMAResM=-inf ");
-          if(~FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] === 0) $display( "FMAResM=+inf ");
-          if(FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] !== 0 && ~FMAResM[`NF-1]) $display( "FMAResM=sigNaN ");
-          if(FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] !== 0 && FMAResM[`NF-1]) $display( "FMAResM=qutNaN ");
-          if(ans[`FLEN] && ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] === 0) $display( "ans=-inf ");
-          if(~ans[`FLEN] && ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] === 0) $display( "ans=+inf ");
-          if(ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] !== 0 && ~ans[`NF-1]) $display( "ans=sigNaN ");
-          if(ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] !== 0 && ans[`NF-1]) $display( "ans=qutNaN ");
-              errors = errors + 1;
-          //if (errors === 10)
-          $stop;
-          end
-          if((FmtE==1'b01)&(FMAFlgM !== flags[4:0] || (!wnan && (FMAResM !== ans)) || (wnan && ansnan && ~(((XNaNE && (FMAResM[64-2:0] === {X[64-2:52],1'b1,X[52-2:0]})) || (YNaNE && (FMAResM[64-2:0] === {Y[64-2:52],1'b1,Y[52-2:0]}))  || (ZNaNE && (FMAResM[64-2:0] === {Z[64-2:52],1'b1,Z[52-2:0]})) || (FMAResM[62:0] === ans[62:0]))) ))) begin
-              $display( "%h %h %h %h %h %h %h  Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags);
-          if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm ");
-          if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm ");
-          if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm ");
-          if(FMAFlgM[4] !== 0) $display( "invld ");
-          if(FMAFlgM[2] !== 0) $display( "ovrflw ");
-          if(FMAFlgM[1] !== 0) $display( "unflw ");
-          if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN ");
-          if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN ");
-          if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN ");
-          if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN ");
-              errors = errors + 1;
-        // if (errors === 9)
-          $stop;
-          end
-          if((FmtE==2'b00)&(FMAFlgM !== flags[4:0] || (!wnan && (FMAResM !== ans)) || (wnan && ansnan && ~(((XNaNE && (FMAResM[32-2:0] === {X[32-2:23],1'b1,X[23-2:0]})) || (YNaNE && (FMAResM[32-2:0] === {Y[32-2:23],1'b1,Y[23-2:0]}))  || (ZNaNE && (FMAResM[32-2:0] === {Z[32-2:23],1'b1,Z[23-2:0]})) || (FMAResM[30:0] === ans[30:0]))) ))) begin
-              $display( "%h %h %h %h %h %h %h  Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags);
-          if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm ");
-          if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm ");
-          if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm ");
-          if(FMAFlgM[4] !== 0) $display( "invld ");
-          if(FMAFlgM[2] !== 0) $display( "ovrflw ");
-          if(FMAFlgM[1] !== 0) $display( "unflw ");
-          if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN ");
-          if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN ");
-          if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN ");
-          if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN ");
-              errors = errors + 1;
-        // if (errors === 9)
-          $stop;
-          end
-          if((FmtE==2'b10)&(FMAFlgM !== flags[4:0] || (!wnan && (FMAResM !== ans)) || (wnan && ansnan && ~(((XNaNE && (FMAResM[16-2:0] === {X[16-2:10],1'b1,X[10-2:0]})) || (YNaNE && (FMAResM[16-2:0] === {Y[16-2:10],1'b1,Y[10-2:0]}))  || (ZNaNE && (FMAResM[16-2:0] === {Z[16-2:10],1'b1,Z[10-2:0]})) || (FMAResM[14:0] === ans[14:0]))) ))) begin
-              $display( "%h %h %h %h %h %h %h  Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags);
-          if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm ");
-          if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm ");
-          if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm ");
-          if(FMAFlgM[4] !== 0) $display( "invld ");
-          if(FMAFlgM[2] !== 0) $display( "ovrflw ");
-          if(FMAFlgM[1] !== 0) $display( "unflw ");
-          if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN ");
-          if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN ");
-          if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN ");
-          if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN ");
-              errors = errors + 1;
-        // if (errors === 9)
-          $stop;
-          end
- end
-	
- vectornum = vectornum + 1;
- if (testvectors[vectornum] === 194'bx) begin
- $display("%d tests completed with %d errors", vectornum, errors);
- $stop;
- end
- end
-endmodule

pipelined/fpu-testfloat/FMA/tbgen/test_gen.sh

@@ -1,3 +0,0 @@
-testfloat_gen f128_mulAdd -tininessafter -n 6133248 -rmin  -seed 113355 -level 1 > testFloat
-tr -d ' ' < testFloat > testFloatNoSpace
-

pipelined/regression/regression-wally

@@ -62,7 +62,7 @@ tc = TestCase(
       grepstr="400100000 instructions")
 configs.append(tc)
 
-tests64gc = ["arch64i", "arch64priv", "arch64c",  "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a",  "imperas64c", "wally64priv", "wally64periph"] # , "imperas64mmu" "wally64i", #,  "testsBP64"] 
+tests64gc = ["arch64i", "arch64priv", "arch64c",  "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a",  "imperas64c", "wally64periph"] # , "imperas64mmu" "wally64i", #,  "testsBP64"] 
 for test in tests64gc:
   tc = TestCase(
         name=test,

pipelined/regression/wally-pipelined-batch.do

@@ -41,7 +41,6 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     run -all
     run -all
     exec ./slack-notifier/slack-notifier.py
-    quit 
 } else {
     vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063
     # start and run simulation
@@ -52,11 +51,15 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     #vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
     #vsim -coverage -lib work_$2 workopt_$2
 
+    # power add generates the logging necessary for saif generation.
+    power add -r /dut/core/*
     run -all
-    quit
+    power off -r /dut/core/*
 } 
 
 #coverage report -file wally-pipelined-coverage.txt
 # These aren't doing anything helpful
 #coverage report -memory 
 #profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2
+power report -all -bsaif power.saif
+quit

pipelined/regression/wally-pipelined-fpga.do

@@ -30,7 +30,7 @@ vlib work
 # default to config/rv64ic, but allow this to be overridden at the command line.  For example:
 # do wally-pipelined.do ../config/rv32ic
 switch $argc {
-    0 {vlog +incdir+../config/fpga +incdir+../config/shared ../testbench/testbench-fpga.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../src/wally/wallypipelinedsocwrapper.v ../../fpga/sim/*.sv -suppress 2583}
+    0 {vlog +incdir+../config/fpga +incdir+../config/shared ../testbench/testbench-fpga.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../src/wally/wallypipelinedsocwrapper.v ../../fpga/sim/*.sv -suppress 2583}
     1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
 }
 # start and run simulation

pipelined/regression/wally-pipelined.do

@@ -57,12 +57,12 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     do wave.do
 
     # power add generates the logging necessary for saif generation.
-    #power add -r /dut/core/*
+    power add -r /dut/core/*
     #-- Run the Simulation 
 
     run -all
-    #power off -r /dut/core/*
+    power off -r /dut/core/*
-    #power report -all -bsaif power.saif
+    power report -all -bsaif power.saif
     noview ../testbench/testbench.sv
     view wave
 }

pipelined/src/fpu/fcmp.sv

@@ -70,6 +70,7 @@ module fcmp (
    if(`IEEE754) assign QNaN = FmtE ? {XSgnE, XExpE, 1'b1, XManE[`NF-2:0]} : {{32{1'b1}}, XSgnE, XExpE[7:0], 1'b1, XManE[50:29]};
    else         assign QNaN = FmtE ? {1'b0, XExpE, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, XExpE[7:0], 1'b1, 22'b0};
  
+ // when one input is a NaN -output the non-NaN
    always_comb begin
       case (FOpCtrlE[2:0])
          3'b111: CmpResE = XNaNE ? YNaNE ? QNaN : FSrcYE // Min

pipelined/src/generic/flop/bram2p1r1w.sv

@@ -78,9 +78,9 @@ module bram2p1r1w
   end
  -----/\----- EXCLUDED -----/\----- */
 
-  initial begin
+  if(PRELOAD_ENABLED) begin
-	if(PRELOAD_ENABLED) begin
+    initial begin
-      RAM[0] =  64'h94e1819300002197; 
+      RAM[0] =  64'h9581819300002197; 
       RAM[1] =  64'h4281420141014081; 
       RAM[2] =  64'h4481440143814301; 
       RAM[3] =  64'h4681460145814501; 
@@ -104,7 +104,7 @@ module bram2p1r1w
       RAM[21] = 64'h0010029b01260613; 
       RAM[22] = 64'h11010002806702fe; 
       RAM[23] = 64'h84b2842ae426e822; 
-      RAM[24] = 64'h892ee04aec064505; 
+      RAM[24] = 64'h892ee04aec064511; 
       RAM[25] = 64'h06e000ef07e000ef; 
       RAM[26] = 64'h979334fd02905563; 
       RAM[27] = 64'h07930177d4930204; 
@@ -120,9 +120,10 @@ module bram2p1r1w
       RAM[37] = 64'h05a1118737836749; 
       RAM[38] = 64'hfed59be3fef5bc23; 
       RAM[39] = 64'h1047278367498082; 
-      RAM[40] = 64'h67c98082dfed8b85; 
+      RAM[40] = 64'h47858082dfed8b85; 
-      RAM[41] = 64'h0000808210a7a023;   
+      RAM[41] = 64'h40a7853b4015551b;   
-	end
+	  RAM[42] = 64'h808210a7a02367c9;
+	end				
   end
 
   // Port-A Operation

pipelined/src/privileged/csr.sv

@@ -33,9 +33,8 @@
 `include "wally-config.vh"
 
 module csr #(parameter
-  // Constants
+    MIP = 12'h344,
-  UIP_REGW = 12'b0, // N user-mode exceptions not supported
+    SIP = 12'h144
-  UIE_REGW = 12'b0
   ) (
   input  logic             clk, reset,
   input  logic             FlushE, FlushM, FlushW,
@@ -76,8 +75,11 @@ module csr #(parameter
 );
 
   localparam NOP = 32'h13;
-  logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM, CSRReadValM;
+  logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM;
-  logic [`XLEN-1:0] CSRSrcM, CSRRWM, CSRRSM, CSRRCM, CSRWriteValM;
+(* mark_debug = "true" *)  logic [`XLEN-1:0] CSRReadValM;  
+(* mark_debug = "true" *)  logic [`XLEN-1:0] CSRSrcM;
+  logic [`XLEN-1:0] CSRRWM, CSRRSM, CSRRCM;  
+(* mark_debug = "true" *)  logic [`XLEN-1:0] CSRWriteValM;
  
 (* mark_debug = "true" *)  logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW;
   logic [31:0]     MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
@@ -92,6 +94,8 @@ module csr #(parameter
   //logic [11:0] UIP_REGW, UIE_REGW = 0; // N user-mode exceptions not supported
   logic        IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, InsufficientCSRPrivilegeM;
   logic IllegalCSRMWriteReadonlyM;
+  logic [`XLEN-1:0] CSRReadVal2M;
+  logic [11:0] IP_REGW_writeable;
   
   logic InstrValidNotFlushedM;
   assign InstrValidNotFlushedM = ~StallW & ~FlushW;
@@ -100,10 +104,15 @@ module csr #(parameter
   always_comb begin
     // Choose either rs1 or uimm[4:0] as source
     CSRSrcM = InstrM[14] ? {{(`XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM;
+
+    // CSR set and clear for MIP/SIP should only touch internal state, not interrupt inputs
+    if (CSRAdrM == MIP | CSRAdrM == SIP) CSRReadVal2M = {{(`XLEN-12){1'b0}}, IP_REGW_writeable};
+    else                                 CSRReadVal2M = CSRReadValM;
+
     // Compute AND/OR modification
     CSRRWM = CSRSrcM;
-    CSRRSM = CSRReadValM | CSRSrcM;
+    CSRRSM = CSRReadVal2M | CSRSrcM;
-    CSRRCM = CSRReadValM & ~CSRSrcM;
+    CSRRCM = CSRReadVal2M & ~CSRSrcM;
     case (InstrM[13:12])
       2'b01:  CSRWriteValM = CSRRWM;
       2'b10:  CSRWriteValM = CSRRSM;
@@ -125,7 +134,7 @@ module csr #(parameter
   csri   csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, 
               .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, 
               .MExtIntM, .SExtIntM, .TimerIntM, .SwIntM,
-              .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW);
+              .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW, .IP_REGW_writeable);
   csrsr csrsr(.clk, .reset, .StallW,
               .WriteMSTATUSM, .WriteSSTATUSM, 
               .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,

pipelined/src/privileged/csri.sv

@@ -37,17 +37,17 @@ module csri #(parameter
     SIE = 12'h104,
     SIP = 12'h144
   ) (
-    input  logic             clk, reset, 
+    input logic 			clk, reset, 
-    input  logic             InstrValidNotFlushedM, StallW,
+    input logic 			InstrValidNotFlushedM, StallW,
-    input  logic             CSRMWriteM, CSRSWriteM,
+    input logic 			CSRMWriteM, CSRSWriteM,
-    input  logic [`XLEN-1:0] CSRWriteValM,
+    input logic [`XLEN-1:0] CSRWriteValM,
-    input  logic [11:0]      CSRAdrM,
+    input logic [11:0] 		CSRAdrM,
-    input  logic             MExtIntM, SExtIntM, TimerIntM, SwIntM,
+    (* mark_debug = "true" *)    input logic MExtIntM, SExtIntM, TimerIntM, SwIntM,
-    input  logic [11:0]      MIDELEG_REGW,
+    input logic [11:0] 		MIDELEG_REGW,
-    output logic [11:0]      MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW
+    output logic [11:0] 	MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, 
+    (* mark_debug = "true" *) output logic [11:0]   IP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
   );
 
-  logic [11:0]     IP_REGW_writeable; // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
   logic [11:0]     IP_REGW, IE_REGW;
   logic [11:0]     MIP_WRITE_MASK, SIP_WRITE_MASK, MIE_WRITE_MASK;
   logic            WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM;

pipelined/src/privileged/csrm.sv

@@ -78,8 +78,8 @@ module csrm #(parameter
     output logic [`XLEN-1:0] CSRMReadValM, MTVEC_REGW,
     (* mark_debug = "true" *)  output logic [`XLEN-1:0] MEPC_REGW,    
     output logic [31:0]      MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, 
-    output logic [`XLEN-1:0] MEDELEG_REGW,
+(* mark_debug = "true" *)      output logic [`XLEN-1:0] MEDELEG_REGW,
-    output logic [11:0]      MIDELEG_REGW,
+(* mark_debug = "true" *)      output logic [11:0]      MIDELEG_REGW,
     // 64-bit registers in RV64, or two 32-bit registers in RV32
     //output var logic [63:0]      PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0],
     output 		     var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],

pipelined/src/uncore/clint.sv

@@ -32,25 +32,25 @@
 `include "wally-config.vh"
 
 module clint (
-  input  logic             HCLK, HRESETn, TIMECLK,
+  input logic 			   HCLK, HRESETn, TIMECLK,
-  input  logic             HSELCLINT,
+  input logic 			   HSELCLINT,
-  input  logic [15:0]      HADDR,
+  input logic [15:0] 	   HADDR,
-  input  logic [3:0]       HSIZED,
+  input logic [3:0] 	   HSIZED,
-  input  logic             HWRITE,
+  input logic 			   HWRITE,
-  input  logic [`XLEN-1:0] HWDATA,
+  input logic [`XLEN-1:0]  HWDATA,
-  input  logic             HREADY,
+  input logic 			   HREADY,
-  input  logic [1:0]       HTRANS,
+  input logic [1:0] 	   HTRANS,
   output logic [`XLEN-1:0] HREADCLINT,
-  output logic             HRESPCLINT, HREADYCLINT,
+  output logic 			   HRESPCLINT, HREADYCLINT,
-  output logic [63:0]      MTIME, 
+  (* mark_debug = "true" *) output logic [63:0] MTIME, 
-  output logic             TimerIntM, SwIntM);
+  output logic 			   TimerIntM, SwIntM);
 
   logic        MSIP;
 
   logic [15:0] entry, entryd;
   logic memwrite;
   logic initTrans;
-  logic [63:0] MTIMECMP;
+  (* mark_debug = "true" *)    logic [63:0] MTIMECMP;
   logic [`XLEN/8-1:0] ByteMaskM;
   integer             i;
 

pipelined/src/uncore/plic.sv

@@ -70,9 +70,9 @@ module plic (
   
   // context-dependent signals
   logic [`C-1:0][2:0]       intThreshold;
-  logic [`C-1:0][`N:1]      intEn;
+    (* mark_debug = "true" *)  logic [`C-1:0][`N:1]      intEn;
   logic [`C-1:0][5:0]       intClaim; // ID's are 6 bits if we stay within 63 sources
-  logic [`C-1:0][7:1][`N:1] irqMatrix;
+    (* mark_debug = "true" *)  logic [`C-1:0][7:1][`N:1] irqMatrix;
   logic [`C-1:0][7:1]       priorities_with_irqs;
   logic [`C-1:0][7:1]       max_priority_with_irqs;
   logic [`C-1:0][`N:1]      irqs_at_max_priority;

pipelined/src/uncore/ram.sv

@@ -43,6 +43,12 @@ module ram #(parameter BASE=0, RANGE = 65535) (
   output logic             HRESPRam, HREADYRam
 );
 
+  // Desired changes.
+  // 1. find a way to merge read and write address into 1 port.
+  // 2. remove all unnecessary latencies. (HREADY needs to be able to constant high.)
+  // 3. implement burst.
+  // 4. remove the configurable latency.
+
   logic [`XLEN/8-1:0] 		  ByteMaskM;
   logic [31:0]        HWADDR, A;
   logic				  prevHREADYRam, risingHREADYRam;

pipelined/src/uncore/sdc/SDC.sv

@@ -30,7 +30,7 @@
 
 `include "wally-config.vh"
 
-`define SDCCLKDIV -8'd2
+`define SDCCLKDIV -8'd3
 
 module SDC 
   (input  logic             HCLK, 
@@ -64,7 +64,7 @@ module SDC
 
 
   // Register outputs
-  logic [7:0] 		    CLKDiv;
+  logic signed [7:0] 		    CLKDiv;
   logic [2:0] 		    Command;
   logic [63:9] 		    Address;
   
@@ -330,15 +330,13 @@ module SDC
 			.ECLK(CLKGate));
 
 
-/* -----\/----- EXCLUDED -----\/-----
   clkdivider #(8) clkdivider(.i_COUNT_IN_MAX(CLKDiv),
-			     .i_EN(CLKDiv != 'b1),
+			     .i_EN(CLKDiv <= 0), // enable if < 0 (msb is 1)
 			     .i_CLK(CLKGate),
 			     .i_RST(~HRESETn | CLKDivUpdateEn),
 			     .o_CLK(SDCCLKIn));
- -----/\----- EXCLUDED -----/\----- */
 
-  assign SDCCLKIn = CLKGate;
+//  assign SDCCLKIn = CLKGate;
   
 
   sd_top sd_top(.CLK(SDCCLKIn),

pipelined/src/uncore/sdc/clkdivider.sv

@@ -52,6 +52,7 @@ module clkdivider #(parameter integer g_COUNT_WIDTH)
   logic 			   w_load;
 
   logic 			   resetD, resetDD, resetPulse;
+  logic 			   rstdd2, rstddn;
 
   assign  w_load = resetPulse | w_counter_overflowed;  // reload when zero occurs or when set by outside
 
@@ -82,7 +83,15 @@ module clkdivider #(parameter integer g_COUNT_WIDTH)
     .q(resetDD),
     .clk(i_CLK));
   
-  assign resetPulse = i_RST & ~resetDD;
+  //assign resetPulse = i_RST & ~resetDD;
+  assign resetPulse = ~i_RST & resetDD;
+
+  assign rstdd2 = i_RST | resetDD;
+  
+  flop #(1) fallingEdge
+	(.d(rstdd2),
+	 .q(rstddn),
+	 .clk(~i_CLK));
   
   flopenr #(1) toggle_flip_flop
     (.d(w_fd_D),
@@ -93,6 +102,11 @@ module clkdivider #(parameter integer g_COUNT_WIDTH)
 
   assign w_fd_D = ~ r_fd_Q;
 
+/* -----\/----- EXCLUDED -----\/-----
   if(`FPGA) BUFGMUX clkMux(.I1(r_fd_Q), .I0(i_CLK), .S(i_EN), .O(o_CLK)); 
   else  assign o_CLK = i_EN ? r_fd_Q : i_CLK;
+ -----/\----- EXCLUDED -----/\----- */
+
+  if(`FPGA) BUFGMUX clkMux(.I1(r_fd_Q), .I0(i_CLK), .S(i_EN & ~rstddn), .O(o_CLK)); 
+  else  assign o_CLK = i_EN & ~rstddn ? r_fd_Q : i_CLK;
 endmodule

pipelined/src/uncore/uartPC16550D.sv

@@ -143,7 +143,7 @@ module uartPC16550D(
       LSR <= #1 8'b01100000;
       MSR <= #1 4'b0;
       if (`FPGA) begin
-		DLL <= #1 8'd11;
+		DLL <= #1 8'd38;
 		DLM <= #1 8'b0;
       end else begin
 		DLL <= #1 8'd1; // this cannot be zero with DLM also zer0.
@@ -159,8 +159,9 @@ module uartPC16550D(
            3'b000: if (DLAB) DLL <= #1 Din; // else TXHR <= #1 Din; // TX handled in TX register/FIFO section
            3'b001: if (DLAB) DLM <= #1 Din; else IER <= #1 Din[3:0];
 		   -----/\----- EXCLUDED -----/\----- */
-		  // *** BUG FIX ME for now for the divider to be 11.  Our clock is 23 Mhz.  23Mhz /(25 * 16) = 57600 baud, which is close enough to 57600 baud
+		  // *** BUG FIX ME for now for the divider to be 38.  Our clock is 35 Mhz.  35Mhz /(38 * 16) ~= 57600 baud, which is close enough to 57600 baud
-          3'b000: if (DLAB) DLL <= #1 8'd11; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section
+		  // freq /baud / 16 = div
+          3'b000: if (DLAB) DLL <= #1 8'd38; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section
           3'b001: if (DLAB) DLM <= #1 8'b0; else IER <= #1 Din[3:0];
 
           3'b010: FCR <= #1 {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing
@@ -310,7 +311,7 @@ module uartPC16550D(
           if (rxfifohead == rxfifotail +1) rxdataready <= #1 0;
         end else begin
           rxdataready <= #1 0;
-          RXBR <= #1 {0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode)
+          RXBR <= #1 {1'b0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode)
         end
       end else if (~MEMWb & A == 3'b010)  // writes to FIFO Control Register
         if (Din[1] | ~Din[0]) begin // rx FIFO reset or FIFO disable clears FIFO contents

pipelined/src/wally/wallypipelinedcore.sv

@@ -66,7 +66,7 @@ module wallypipelinedcore (
   logic [1:0]             AtomicE;
   logic [1:0]             AtomicM;
   logic [`XLEN-1:0]     ForwardedSrcAE, ForwardedSrcBE; //, SrcAE, SrcBE;
-  logic [`XLEN-1:0]         SrcAM;
+(* mark_debug = "true" *)  logic [`XLEN-1:0]         SrcAM;
   logic [2:0]             Funct3E;
   //  logic [31:0] InstrF;
   logic [31:0]             InstrD, InstrW;

pipelined/testbench/fp/tests/fma-testbench.sv

@@ -1,279 +0,0 @@
-
-`include "wally-config.vh"
-`define PATH "../../../../tests/fp/vectors/"
-
-string tests[] = '{
-    "f16_mulAdd_rne.tv",
-    "f16_mulAdd_rz.tv",
-    "f16_mulAdd_ru.tv",
-    "f16_mulAdd_rd.tv",
-    "f16_mulAdd_rnm.tv",
-    "f32_mulAdd_rne.tv",
-    "f32_mulAdd_rz.tv",
-    "f32_mulAdd_ru.tv",
-    "f32_mulAdd_rd.tv",
-    "f32_mulAdd_rnm.tv",
-    "f64_mulAdd_rne.tv",
-    "f64_mulAdd_rz.tv",
-    "f64_mulAdd_ru.tv",
-    "f64_mulAdd_rd.tv",
-    "f64_mulAdd_rnm.tv",
-    "f128_mulAdd_rne.tv",
-    "f128_mulAdd_rz.tv",
-    "f128_mulAdd_ru.tv",
-    "f128_mulAdd_rd.tv",
-    "f128_mulAdd_rnm.tv"
-};
-
-// steps to run FMA tests
-//    1) create test vectors in riscv-wally/tests/fp with: ./run-all.sh
-//    2) go to riscv-wally/pipelined/testbench/fp/tests
-//    3) run ./sim-wally-batch
-
-module fmatestbench();
-
-  logic clk;
-  logic [31:0] errors=0;
-  logic [31:0] vectornum=0;
-  logic [`FLEN*4+7+4+4:0] testvectors[6133248:0];
-  int i = `ZFH_SUPPORTED ? 0 : `F_SUPPORTED ? 5 : `D_SUPPORTED ? 10 : 15; // set i to the first test that is run
-
-  logic [`FLEN-1:0]     X, Y, Z;  // inputs read from TestFloat
-  logic [`FLEN-1:0]	    ans;      // result from TestFloat
-  logic [7:0]	 	        flags;    // flags read form testfloat
-  logic [2:0]		        FrmE;     // rounding mode
-  logic	[`FPSIZES/3:0]  FmtE;     // format - 10 = half, 00 = single, 01 = double, 11 = quad
-  logic [3:0]		        FrmRead;  // rounding mode read from testfloat
-  logic	[3:0]			      FmtRead;  // format read from testfloat
-  logic [`FLEN-1:0]     FMAResM;  // FMA's outputed result
-  logic [4:0]           FMAFlgM;  // FMA's outputed flags
-  logic [2:0]		        FOpCtrlE; // which opperation
-  logic                 wnan;     // is the outputed result NaN
-  logic                 ansnan;   // is the correct answer NaN
-  
-  // signals needed to connect modules
-  logic [`NE+1:0]	  ProdExpE;
-  logic 				    AddendStickyE;
-  logic 					  KillProdE; 
-  logic             XSgnE, YSgnE, ZSgnE;
-  logic [`NE-1:0]   XExpE, YExpE, ZExpE;
-  logic [`NF:0]     XManE, YManE, ZManE;
-  logic             XNormE;
-  logic             XExpMaxE;
-  logic             XNaNE, YNaNE, ZNaNE;
-  logic             XSNaNE, YSNaNE, ZSNaNE;
-  logic             XDenormE, YDenormE, ZDenormE;
-  logic             XInfE, YInfE, ZInfE;
-  logic             XZeroE, YZeroE, ZZeroE;
-  logic             YExpMaxE, ZExpMaxE, Mult;
-  logic [3*`NF+5:0]	SumE;       
-  logic 			      InvZE;
-  logic 			      NegSumE;
-  logic 			      ZSgnEffE;
-  logic 			      PSgnE;
-  logic [$clog2(3*`NF+7)-1:0]	NormCntE;
-
-
-  assign FOpCtrlE = 3'b0; // set to 0 because test float only tests fMADD
-  assign Mult = 1'b0;     // set to zero because not testing multiplication
-
-  // check if the calculated result or correct answer is NaN
-  always_comb begin
-    case (FmtRead)
-        4'b11: begin // quad             
-          assign ansnan = &ans[`FLEN-2:`NF]&(|ans[`NF-1:0]);
-          assign wnan = &FMAResM[`FLEN-2:`NF]&(|FMAResM[`NF-1:0]);
-
-        end
-        4'b01: begin // double                 
-          assign ansnan = &ans[`LEN1-2:`NF1]&(|ans[`NF1-1:0]);
-          assign wnan = &FMAResM[`LEN1-2:`NF1]&(|FMAResM[`NF1-1:0]);
-
-        end
-        4'b00: begin // single
-            assign ansnan = &ans[`LEN2-2:`NF2]&(|ans[`NF2-1:0]);
-            assign wnan = &FMAResM[`LEN2-2:`NF2]&(|FMAResM[`NF2-1:0]);
-        end
-        4'b10: begin // half
-            assign ansnan = &ans[`H_LEN-2:`H_NF]&(|ans[`H_NF-1:0]);
-            assign wnan = &FMAResM[`H_LEN-2:`H_NF]&(|FMAResM[`H_NF-1:0]);
-        end
-    endcase
-  end
-
-  // instantiate devices under test
-  unpack unpack(.X, .Y, .Z, .FmtE, .FOpCtrlE, .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE,
-                .XManE, .YManE, .ZManE, .XNormE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE,
-                .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE,
-                .XExpMaxE);
-  fma1 fma1(.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE,
-            .XDenormE, .YDenormE, .ZDenormE,  .XZeroE, .YZeroE, .ZZeroE,
-            .FOpCtrlE, .FmtE, .SumE, .NegSumE, .InvZE, .NormCntE, .ZSgnEffE, .PSgnE,
-            .ProdExpE, .AddendStickyE, .KillProdE); 
-  fma2 fma2(.XSgnM(XSgnE), .YSgnM(YSgnE), .XExpM(XExpE), .YExpM(YExpE), .ZExpM(ZExpE), .XManM(XManE), .YManM(YManE), .ZManM(ZManE), 
-            .XNaNM(XNaNE), .YNaNM(YNaNE), .ZNaNM(ZNaNE), .XZeroM(XZeroE), .YZeroM(YZeroE), .ZZeroM(ZZeroE), .XInfM(XInfE), .YInfM(YInfE), .ZInfM(ZInfE), 
-            .XSNaNM(XSNaNE), .YSNaNM(YSNaNE), .ZSNaNM(ZSNaNE), .KillProdM(KillProdE), .AddendStickyM(AddendStickyE), .ProdExpM(ProdExpE), 
-            .SumM(SumE), .NegSumM(NegSumE), .InvZM(InvZE), .NormCntM(NormCntE), .ZSgnEffM(ZSgnEffE), .PSgnM(PSgnE), .FmtM(FmtE), .FrmM(FrmE), 
-            .FMAFlgM, .FMAResM, .Mult);
-
-
-  // produce clock
-  always begin
-    clk = 1; #5; clk = 0; #5;
-  end
-  
-  // Read first test
-  initial begin
-      $display("\n\nRunning %s vectors", tests[i]);
-      $readmemh({`PATH, tests[i]}, testvectors);
-  end
-
-  // apply test vectors on rising edge of clk
-  always @(posedge clk) begin
-    #1; 
-    flags = testvectors[vectornum][15:8];
-    FrmRead = testvectors[vectornum][7:4];
-    FmtRead = testvectors[vectornum][3:0];
-    if (FmtRead==4'b11 & `Q_SUPPORTED) 	begin       // quad
-      X = testvectors[vectornum][16+4*(`Q_LEN)-1:16+3*(`Q_LEN)];
-      Y = testvectors[vectornum][16+3*(`Q_LEN)-1:16+2*(`Q_LEN)];
-      Z = testvectors[vectornum][16+2*(`Q_LEN)-1:16+`Q_LEN];
-      ans = testvectors[vectornum][16+(`Q_LEN-1):16];
-    end
-    else if (FmtRead==4'b01 & `D_SUPPORTED)	begin	  // double
-      X = {{`FLEN-`D_LEN{1'b1}}, testvectors[vectornum][16+4*(`D_LEN)-1:16+3*(`D_LEN)]};
-      Y = {{`FLEN-`D_LEN{1'b1}}, testvectors[vectornum][16+3*(`D_LEN)-1:16+2*(`D_LEN)]};
-      Z = {{`FLEN-`D_LEN{1'b1}}, testvectors[vectornum][16+2*(`D_LEN)-1:16+`D_LEN]};
-      ans = {{`FLEN-`D_LEN{1'b1}}, testvectors[vectornum][16+(`D_LEN-1):16]};
-    end
-    else if (FmtRead==4'b00 & `F_SUPPORTED)	begin	  // single
-      X = {{`FLEN-`S_LEN{1'b1}}, testvectors[vectornum][16+4*(`S_LEN)-1:16+3*(`S_LEN)]};
-      Y = {{`FLEN-`S_LEN{1'b1}}, testvectors[vectornum][16+3*(`S_LEN)-1:16+2*(`S_LEN)]};
-      Z = {{`FLEN-`S_LEN{1'b1}}, testvectors[vectornum][16+2*(`S_LEN)-1:16+`S_LEN]};
-      ans = {{`FLEN-`S_LEN{1'b1}}, testvectors[vectornum][16+(`S_LEN-1):16]};
-    end
-    else if (FmtRead==4'b10 & `ZFH_SUPPORTED)	begin	  // half
-      X = {{`FLEN-`H_LEN{1'b1}}, testvectors[vectornum][16+4*(`H_LEN)-1:16+3*(`H_LEN)]};
-      Y = {{`FLEN-`H_LEN{1'b1}}, testvectors[vectornum][16+3*(`H_LEN)-1:16+2*(`H_LEN)]};
-      Z = {{`FLEN-`H_LEN{1'b1}}, testvectors[vectornum][16+2*(`H_LEN)-1:16+`H_LEN]};
-      ans = {{`FLEN-`H_LEN{1'b1}}, testvectors[vectornum][16+(`H_LEN-1):16]};
-    end
-    else begin	  
-      X = {`FLEN{1'bx}};
-      Y = {`FLEN{1'bx}};
-      Z = {`FLEN{1'bx}};
-      ans = {`FLEN{1'bx}};
-    end
-
-    // trim format and rounding mode to appropriate size
-    if (`FPSIZES <= 2) FmtE = FmtRead === `FMT; // rewrite format if 2 or less floating formats are supported
-    else FmtE = FmtRead[1:0];
-    FrmE = FrmRead[2:0];
-  end
-
-  // check results on falling edge of clk
-    always @(negedge clk) begin
-      // quad
-        if((FmtRead==4'b11) & ~((FMAFlgM === flags[4:0]) | (FMAResM === ans) | (wnan & (FMAResM[`FLEN-2:0] === ans[`FLEN-2:0] | (XNaNE&(FMAResM[`FLEN-2:0] === {X[`FLEN-2:`NF],1'b1,X[`NF-2:0]})) | (YNaNE&(FMAResM[`FLEN-2:0] === {Y[`FLEN-2:`NF],1'b1,Y[`NF-2:0]})) | (ZNaNE&(FMAResM[`FLEN-2:0] === {Z[`FLEN-2:`NF],1'b1,Z[`NF-2:0]})))))) begin
-          $display( "%h %h %h %h %h %h %h  Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags);
-          if(XDenormE) $display( "xdenorm ");
-          if(YDenormE) $display( "ydenorm ");
-          if(ZDenormE) $display( "zdenorm ");
-          if(FMAFlgM[4] !== 0) $display( "invld ");
-          if(FMAFlgM[2] !== 0) $display( "ovrflw ");
-          if(FMAFlgM[1] !== 0) $display( "unflw ");
-          if(FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] === 0) $display( "FMAResM=-inf ");
-          if(~FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] === 0) $display( "FMAResM=+inf ");
-          if(FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] !== 0 && ~FMAResM[`NF-1]) $display( "FMAResM=sigNaN ");
-          if(FMAResM[`FLEN-2:`NF] === {`NE{1'b1}} && FMAResM[`NF-1:0] !== 0 && FMAResM[`NF-1]) $display( "FMAResM=qutNaN ");
-          if(ans[`FLEN] && ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] === 0) $display( "ans=-inf ");
-          if(~ans[`FLEN] && ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] === 0) $display( "ans=+inf ");
-          if(ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] !== 0 && ~ans[`NF-1]) $display( "ans=sigNaN ");
-          if(ans[`FLEN-2:`NF] === {`NE{1'b1}} && ans[`NF-1:0] !== 0 && ans[`NF-1]) $display( "ans=qutNaN ");
-          errors = errors + 1;
-          if (errors === 1) $stop;
-        end
-      // double
-        if((FmtRead==4'b01) & ~((FMAFlgM === flags[4:0]) | (FMAResM === ans) | (wnan & (FMAResM[`D_LEN-2:0] === ans[`D_LEN-2:0] | (XNaNE&(FMAResM[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | (YNaNE&(FMAResM[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]})) | (ZNaNE&(FMAResM[`D_LEN-2:0] === {Z[`D_LEN-2:`D_NF],1'b1,Z[`D_NF-2:0]})))))) begin
-          $display( "%h %h %h %h %h %h %h  Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags);
-          if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm ");
-          if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm ");
-          if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm ");
-          if(FMAFlgM[4] !== 0) $display( "invld ");
-          if(FMAFlgM[2] !== 0) $display( "ovrflw ");
-          if(FMAFlgM[1] !== 0) $display( "unflw ");
-          if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN ");
-          if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN ");
-          if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN ");
-          if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN ");
-          errors = errors + 1;
-          if (errors === 1) $stop;
-        end
-      // single
-        if((FmtRead==4'b00) & ~((FMAFlgM === flags[4:0]) | (FMAResM === ans) | (wnan & (FMAResM[`S_LEN-2:0] === ans[`S_LEN-2:0] | (XNaNE&(FMAResM[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | (YNaNE&(FMAResM[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]})) | (ZNaNE&(FMAResM[`S_LEN-2:0] === {Z[`S_LEN-2:`S_NF],1'b1,Z[`S_NF-2:0]})))))) begin
-          $display( "%h %h %h %h %h %h %h  Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags);
-          if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm ");
-          if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm ");
-          if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm ");
-          if(FMAFlgM[4] !== 0) $display( "invld ");
-          if(FMAFlgM[2] !== 0) $display( "ovrflw ");
-          if(FMAFlgM[1] !== 0) $display( "unflw ");
-          if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN ");
-          if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN ");
-          if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN ");
-          if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN ");
-          errors = errors + 1;
-          if (errors === 1) $stop;
-        end
-      // half
-        if((FmtRead==4'b01) & ~((FMAFlgM === flags[4:0]) | (FMAResM === ans) | (wnan & (FMAResM[`H_LEN-2:0] === ans[`H_LEN-2:0] | (XNaNE&(FMAResM[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | (YNaNE&(FMAResM[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]})) | (ZNaNE&(FMAResM[`H_LEN-2:0] === {Z[`H_LEN-2:`H_NF],1'b1,Z[`H_NF-2:0]})))))) begin
-          $display( "%h %h %h %h %h %h %h  Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags);
-          if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm ");
-          if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm ");
-          if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm ");
-          if(FMAFlgM[4] !== 0) $display( "invld ");
-          if(FMAFlgM[2] !== 0) $display( "ovrflw ");
-          if(FMAFlgM[1] !== 0) $display( "unflw ");
-          if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN ");
-          if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN ");
-          if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN ");
-          if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN ");
-          errors = errors + 1;
-          if (errors === 1) $stop;
-        end
-        
-	    // if ( vectornum === 3165862) $stop; // uncomment for specific test
-      vectornum = vectornum + 1; // increment test
-      if (testvectors[vectornum][0] === 1'bx) begin // if reached the end of file
-        if (errors) begin // if there were errors
-          $display("%s completed with %d tests and %d errors", tests[i], vectornum, errors);
-          $stop;
-        end
-        else begin // if no errors
-          if(tests[i] === "") begin // if no more tests
-            $display("\nAll tests completed with %d errors\n", errors);
-            $stop;
-          end
-
-          $display("%s completed successfully with %d tests and %d errors (across all tests)\n", tests[i], vectornum, errors);
-
-          // increment tests - skip some precisions if needed
-          if ((i === 4 & ~`F_SUPPORTED) | (i === 9 & ~`D_SUPPORTED) | (i === 14 & ~`Q_SUPPORTED)) i = i+5;
-          if ((i === 9 & ~`D_SUPPORTED) | (i === 14 & ~`Q_SUPPORTED)) i = i+5;
-          if ((i === 14 & ~`Q_SUPPORTED)) i = i+5;
-          i = i+1;
-
-          // if no more tests - finish
-          if(tests[i] === "") begin
-            $display("\nAll tests completed with %d errors\n", errors);
-            $stop;
-          end 
-
-          // read next files
-          $display("Running %s vectors", tests[i]);
-          $readmemh({`PATH, tests[i]}, testvectors);
-          vectornum = 0;
-        end
-      end
-  end
-endmodule

pipelined/testbench/fp/tests/fma.do

@@ -1,50 +0,0 @@
-# wally-pipelined.do 
-#
-# Modification by Oklahoma State University & Harvey Mudd College
-# Use with Testbench 
-# James Stine, 2008; David Harris 2021
-# Go Cowboys!!!!!!
-#
-# Takes 1:10 to run RV64IC tests using gui
-
-# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
-
-# Use this wally-pipelined.do file to run this example.
-# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
-#     do wally-pipelined.do
-# or, to run from a shell, type the following at the shell prompt:
-#     vsim -do wally-pipelined.do -c
-# (omit the "-c" to see the GUI while running from the shell)
-
-onbreak {resume}
-
-# create library
-if [file exists work] {
-    vdel -all
-}
-vlib work
-
-# compile source files
-# suppress spurious warnngs about 
-# "Extra checking for conflicts with always_comb done at vopt time"
-# because vsim will run vopt
-
-# start and run simulation
-# remove +acc flag for faster sim during regressions if there is no need to access internal signals
-# $num = the added words after the call
-vlog +incdir+../../../config/$1 +incdir+../../../config/shared fma-testbench.sv ../../../src/fpu/fma.sv ../../../src/fpu/unpack.sv -suppress 2583 -suppress 7063
-
-vsim -voptargs=+acc work.fmatestbench
-
-view wave
-#-- display input and output signals as hexidecimal values
-#do ./wave-dos/peripheral-waves.do
-#add log -recursive /*
-#do wave.do deal with when ready
-
-#-- Run the Simulation 
-#run 3600 
-run -all
-noview fma-testbench.sv
-view wave
-

pipelined/testbench/fp/tests/sim-fma

@@ -1 +0,0 @@
-vsim -do "do fma.do rv64fp"

pipelined/testbench/fp/tests/sim-fma-batch

@@ -1 +0,0 @@
-vsim -c -do "do fma.do rv64fp"

pipelined/testbench/tests.vh

@@ -1450,30 +1450,30 @@ string imperas32f[] = '{
 
  string wally64priv[] = '{
     `WALLYTEST,
-    "rv64i_m/privilege/WALLY-CSR-permission-s-01", "0050a0",
+    "rv64i_m/privilege/WALLY-CSR-permission-s-01", "0060a0",
-    //"rv64i_m/privilege/WALLY-CSR-PERMISSIONS-M", "005070",
+    //"rv64i_m/privilege/WALLY-CSR-PERMISSIONS-M", "005090",
-    //"rv64i_m/privilege/WALLY-CSR-PERMISSIONS-S", "003070",
+    //"rv64i_m/privilege/WALLY-CSR-PERMISSIONS-S", "003090",
-    "rv64i_m/privilege/WALLY-CSR-permission-u-01", "0050a0",
+    "rv64i_m/privilege/WALLY-CSR-permission-u-01", "0060a0",
-   // "rv64i_m/privilege/WALLY-MARCHID", "003070",
+   // "rv64i_m/privilege/WALLY-MARCHID", "004090",
-/*    "rv64i_m/privilege/WALLY-MCAUSE", "003070",
+/*    "rv64i_m/privilege/WALLY-MCAUSE", "003090",
-    "rv64i_m/privilege/WALLY-MEDELEG", "003070",
+    "rv64i_m/privilege/WALLY-MEDELEG", "004090",
-    "rv64i_m/privilege/WALLY-MHARTID", "003070",
+    "rv64i_m/privilege/WALLY-MHARTID", "004090",
-    "rv64i_m/privilege/WALLY-MIMPID", "003070",*/
+    "rv64i_m/privilege/WALLY-MIMPID", "004090",*/
-    "rv64i_m/privilege/WALLY-minfo-01", "0040a0",
+    "rv64i_m/privilege/WALLY-minfo-01", "0050a0",
-    "rv64i_m/privilege/WALLY-misa-01", "0040a0",
+    "rv64i_m/privilege/WALLY-misa-01", "0050a0",
-    "rv64i_m/privilege/WALLY-MMU-SV39", "0040a0",
+    "rv64i_m/privilege/WALLY-MMU-SV39", "0050a0",
-    "rv64i_m/privilege/WALLY-MMU-SV48", "0040a0",
+    "rv64i_m/privilege/WALLY-MMU-SV48", "0050a0",
-/*    "rv64i_m/privilege/WALLY-MSTATUS", "002070",
+/*    "rv64i_m/privilege/WALLY-MSTATUS", "002090",
-    "rv64i_m/privilege/WALLY-MTVEC", "002070",
+    "rv64i_m/privilege/WALLY-MTVEC", "002090",
-    "rv64i_m/privilege/WALLY-MVENDORID", "003070", */
+    "rv64i_m/privilege/WALLY-MVENDORID", "004090", */
-    "rv64i_m/privilege/WALLY-PMA", "0040a0",
+    "rv64i_m/privilege/WALLY-PMA", "0050a0",
-    "rv64i_m/privilege/WALLY-PMP", "0040a0",
+    "rv64i_m/privilege/WALLY-PMP", "0050a0",
-//    "rv64i_m/privilege/WALLY-SCAUSE", "002070",
+//    "rv64i_m/privilege/WALLY-SCAUSE", "002090",
-    "rv64i_m/privilege/WALLY-scratch-01", "0040a0",
+//    "rv64i_m/privilege/WALLY-scratch-01", "0040a0",
-    "rv64i_m/privilege/WALLY-sscratch-s-01", "0040a0"
+//    "rv64i_m/privilege/WALLY-sscratch-s-01", "0040a0",
-//    "rv64i_m/privilege/WALLY-trap-01", "0040a0"
+//    "rv64i_m/privilege/WALLY-trap-01", "0050a0"
-//    "rv64i_m/privilege/WALLY-STVEC", "002070",
+//    "rv64i_m/privilege/WALLY-STVEC", "002090",
-//    "rv64i_m/privilege/WALLY-UCAUSE", "002070",
+//    "rv64i_m/privilege/WALLY-UCAUSE", "002090",
 
  };
 

tests/fp/append_ctrlSig.sh

@@ -0,0 +1,484 @@
+#!/bin/sh
+BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
+OUTPUT="./vectors"
+echo "Editing ui32_to_f16 test vectors"
+sed -ie 's/$/_0_2_2/' $OUTPUT/ui32_to_f16_rne.tv
+sed -ie 's/$/_1_2_2/' $OUTPUT/ui32_to_f16_rz.tv
+sed -ie 's/$/_3_2_2/' $OUTPUT/ui32_to_f16_ru.tv
+sed -ie 's/$/_2_2_2/' $OUTPUT/ui32_to_f16_rd.tv
+sed -ie 's/$/_4_2_2/' $OUTPUT/ui32_to_f16_rnm.tv
+echo "Editing ui32_to_f32 test vectors"
+sed -ie 's/$/_0_0_2/' $OUTPUT/ui32_to_f32_rne.tv
+sed -ie 's/$/_1_0_2/' $OUTPUT/ui32_to_f32_rz.tv
+sed -ie 's/$/_3_0_2/' $OUTPUT/ui32_to_f32_ru.tv
+sed -ie 's/$/_2_0_2/' $OUTPUT/ui32_to_f32_rd.tv
+sed -ie 's/$/_4_0_2/' $OUTPUT/ui32_to_f32_rnm.tv
+echo "Editing ui32_to_f64 test vectors"
+sed -ie 's/$/_0_1_2/' $OUTPUT/ui32_to_f64_rne.tv
+sed -ie 's/$/_1_1_2/' $OUTPUT/ui32_to_f64_rz.tv
+sed -ie 's/$/_3_1_2/' $OUTPUT/ui32_to_f64_ru.tv
+sed -ie 's/$/_2_1_2/' $OUTPUT/ui32_to_f64_rd.tv
+sed -ie 's/$/_4_1_2/' $OUTPUT/ui32_to_f64_rnm.tv
+echo "Editing ui32_to_f128 test vectors"
+sed -ie 's/$/_0_3_2/' $OUTPUT/ui32_to_f128_rne.tv
+sed -ie 's/$/_1_3_2/' $OUTPUT/ui32_to_f128_rz.tv
+sed -ie 's/$/_3_3_2/' $OUTPUT/ui32_to_f128_ru.tv
+sed -ie 's/$/_2_3_2/' $OUTPUT/ui32_to_f128_rd.tv
+sed -ie 's/$/_4_3_2/' $OUTPUT/ui32_to_f128_rnm.tv
+echo "Editing ui64_to_f16 test vectors"
+sed -ie 's/$/_0_2_6/' $OUTPUT/ui64_to_f16_rne.tv
+sed -ie 's/$/_1_2_6/' $OUTPUT/ui64_to_f16_rz.tv
+sed -ie 's/$/_3_2_6/' $OUTPUT/ui64_to_f16_ru.tv
+sed -ie 's/$/_2_2_6/' $OUTPUT/ui64_to_f16_rd.tv
+sed -ie 's/$/_4_2_6/' $OUTPUT/ui64_to_f16_rnm.tv
+echo "Editing ui64_to_f32 test vectors"
+sed -ie 's/$/_0_0_6/' $OUTPUT/ui64_to_f32_rne.tv
+sed -ie 's/$/_1_0_6/' $OUTPUT/ui64_to_f32_rz.tv
+sed -ie 's/$/_3_0_6/' $OUTPUT/ui64_to_f32_ru.tv
+sed -ie 's/$/_2_0_6/' $OUTPUT/ui64_to_f32_rd.tv
+sed -ie 's/$/_4_0_6/' $OUTPUT/ui64_to_f32_rnm.tv
+echo "Editing ui64_to_f64 test vectors"
+sed -ie 's/$/_0_1_6/' $OUTPUT/ui64_to_f64_rne.tv
+sed -ie 's/$/_1_1_6/' $OUTPUT/ui64_to_f64_rz.tv
+sed -ie 's/$/_3_1_6/' $OUTPUT/ui64_to_f64_ru.tv
+sed -ie 's/$/_2_1_6/' $OUTPUT/ui64_to_f64_rd.tv
+sed -ie 's/$/_4_1_6/' $OUTPUT/ui64_to_f64_rnm.tv
+echo "Editing ui64_to_f128 test vectors"
+sed -ie 's/$/_0_3_6/' $OUTPUT/ui64_to_f128_rne.tv
+sed -ie 's/$/_1_3_6/' $OUTPUT/ui64_to_f128_rz.tv
+sed -ie 's/$/_3_3_6/' $OUTPUT/ui64_to_f128_ru.tv
+sed -ie 's/$/_2_3_6/' $OUTPUT/ui64_to_f128_rd.tv
+sed -ie 's/$/_4_3_6/' $OUTPUT/ui64_to_f128_rnm.tv
+echo "Editing i32_to_f16 test vectors"
+sed -ie 's/$/_0_2_0/' $OUTPUT/i32_to_f16_rne.tv
+sed -ie 's/$/_1_2_0/' $OUTPUT/i32_to_f16_rz.tv
+sed -ie 's/$/_3_2_0/' $OUTPUT/i32_to_f16_ru.tv
+sed -ie 's/$/_2_2_0/' $OUTPUT/i32_to_f16_rd.tv
+sed -ie 's/$/_4_2_0/' $OUTPUT/i32_to_f16_rnm.tv
+echo "Editing i32_to_f32 test vectors"
+sed -ie 's/$/_0_0_0/' $OUTPUT/i32_to_f32_rne.tv
+sed -ie 's/$/_1_0_0/' $OUTPUT/i32_to_f32_rz.tv
+sed -ie 's/$/_3_0_0/' $OUTPUT/i32_to_f32_ru.tv
+sed -ie 's/$/_2_0_0/' $OUTPUT/i32_to_f32_rd.tv
+sed -ie 's/$/_4_0_0/' $OUTPUT/i32_to_f32_rnm.tv
+echo "Editing i32_to_f64 test vectors"
+sed -ie 's/$/_0_1_0/' $OUTPUT/i32_to_f64_rne.tv
+sed -ie 's/$/_1_1_0/' $OUTPUT/i32_to_f64_rz.tv
+sed -ie 's/$/_3_1_0/' $OUTPUT/i32_to_f64_ru.tv
+sed -ie 's/$/_2_1_0/' $OUTPUT/i32_to_f64_rd.tv
+sed -ie 's/$/_4_1_0/' $OUTPUT/i32_to_f64_rnm.tv
+echo "Editing i32_to_f128 test vectors"
+sed -ie 's/$/_0_3_0/' $OUTPUT/i32_to_f128_rne.tv
+sed -ie 's/$/_1_3_0/' $OUTPUT/i32_to_f128_rz.tv
+sed -ie 's/$/_3_3_0/' $OUTPUT/i32_to_f128_ru.tv
+sed -ie 's/$/_2_3_0/' $OUTPUT/i32_to_f128_rd.tv
+sed -ie 's/$/_4_3_0/' $OUTPUT/i32_to_f128_rnm.tv
+echo "Editing i64_to_f16 test vectors"
+sed -ie 's/$/_0_2_4/' $OUTPUT/i64_to_f16_rne.tv
+sed -ie 's/$/_1_2_4/' $OUTPUT/i64_to_f16_rz.tv
+sed -ie 's/$/_3_2_4/' $OUTPUT/i64_to_f16_ru.tv
+sed -ie 's/$/_2_2_4/' $OUTPUT/i64_to_f16_rd.tv
+sed -ie 's/$/_4_2_4/' $OUTPUT/i64_to_f16_rnm.tv
+echo "Editing i64_to_f32 test vectors"
+sed -ie 's/$/_0_0_4/' $OUTPUT/i64_to_f32_rne.tv
+sed -ie 's/$/_1_0_4/' $OUTPUT/i64_to_f32_rz.tv
+sed -ie 's/$/_3_0_4/' $OUTPUT/i64_to_f32_ru.tv
+sed -ie 's/$/_2_0_4/' $OUTPUT/i64_to_f32_rd.tv
+sed -ie 's/$/_4_0_4/' $OUTPUT/i64_to_f32_rnm.tv
+echo "Editing i64_to_f64 test vectors"
+sed -ie 's/$/_0_1_4/' $OUTPUT/i64_to_f64_rne.tv
+sed -ie 's/$/_1_1_4/' $OUTPUT/i64_to_f64_rz.tv
+sed -ie 's/$/_3_1_4/' $OUTPUT/i64_to_f64_ru.tv
+sed -ie 's/$/_2_1_4/' $OUTPUT/i64_to_f64_rd.tv
+sed -ie 's/$/_4_1_4/' $OUTPUT/i64_to_f64_rnm.tv
+echo "Editing i64_to_f128 test vectors"
+sed -ie 's/$/_0_3_4/' $OUTPUT/i64_to_f128_rne.tv
+sed -ie 's/$/_1_3_4/' $OUTPUT/i64_to_f128_rz.tv
+sed -ie 's/$/_3_3_4/' $OUTPUT/i64_to_f128_ru.tv
+sed -ie 's/$/_2_3_4/' $OUTPUT/i64_to_f128_rd.tv
+sed -ie 's/$/_4_3_4/' $OUTPUT/i64_to_f128_rnm.tv
+echo "Editing f16_to_ui32 test vectors"
+sed -ie 's/$/_0_2_3/' $OUTPUT/f16_to_ui32_rne.tv
+sed -ie 's/$/_1_2_3/' $OUTPUT/f16_to_ui32_rz.tv
+sed -ie 's/$/_3_2_3/' $OUTPUT/f16_to_ui32_ru.tv
+sed -ie 's/$/_2_2_3/' $OUTPUT/f16_to_ui32_rd.tv
+sed -ie 's/$/_4_2_3/' $OUTPUT/f16_to_ui32_rnm.tv
+echo "Editing f32_to_ui32 test vectors"
+sed -ie 's/$/_0_0_3/' $OUTPUT/f32_to_ui32_rne.tv
+sed -ie 's/$/_1_0_3/' $OUTPUT/f32_to_ui32_rz.tv
+sed -ie 's/$/_3_0_3/' $OUTPUT/f32_to_ui32_ru.tv
+sed -ie 's/$/_2_0_3/' $OUTPUT/f32_to_ui32_rd.tv
+sed -ie 's/$/_4_0_3/' $OUTPUT/f32_to_ui32_rnm.tv
+echo "Editing f64_to_ui32 test vectors"
+sed -ie 's/$/_0_1_3/' $OUTPUT/f64_to_ui32_rne.tv
+sed -ie 's/$/_1_1_3/' $OUTPUT/f64_to_ui32_rz.tv
+sed -ie 's/$/_3_1_3/' $OUTPUT/f64_to_ui32_ru.tv
+sed -ie 's/$/_2_1_3/' $OUTPUT/f64_to_ui32_rd.tv
+sed -ie 's/$/_4_1_3/' $OUTPUT/f64_to_ui32_rnm.tv
+echo "Editing f128_to_ui32 test vectors"
+sed -ie 's/$/_0_3_3/' $OUTPUT/f128_to_ui32_rne.tv
+sed -ie 's/$/_1_3_3/' $OUTPUT/f128_to_ui32_rz.tv
+sed -ie 's/$/_3_3_3/' $OUTPUT/f128_to_ui32_ru.tv
+sed -ie 's/$/_2_3_3/' $OUTPUT/f128_to_ui32_rd.tv
+sed -ie 's/$/_4_3_3/' $OUTPUT/f128_to_ui32_rnm.tv
+echo "Editing f16_to_ui64 test vectors"
+sed -ie 's/$/_0_2_7/' $OUTPUT/f16_to_ui64_rne.tv
+sed -ie 's/$/_1_2_7/' $OUTPUT/f16_to_ui64_rz.tv
+sed -ie 's/$/_3_2_7/' $OUTPUT/f16_to_ui64_ru.tv
+sed -ie 's/$/_2_2_7/' $OUTPUT/f16_to_ui64_rd.tv
+sed -ie 's/$/_4_2_7/' $OUTPUT/f16_to_ui64_rnm.tv
+echo "Editing f32_to_ui64 test vectors"
+sed -ie 's/$/_0_0_7/' $OUTPUT/f32_to_ui64_rne.tv
+sed -ie 's/$/_1_0_7/' $OUTPUT/f32_to_ui64_rz.tv
+sed -ie 's/$/_3_0_7/' $OUTPUT/f32_to_ui64_ru.tv
+sed -ie 's/$/_2_0_7/' $OUTPUT/f32_to_ui64_rd.tv
+sed -ie 's/$/_4_0_7/' $OUTPUT/f32_to_ui64_rnm.tv
+echo "Editing f64_to_ui64 test vectors"
+sed -ie 's/$/_0_1_7/' $OUTPUT/f64_to_ui64_rne.tv
+sed -ie 's/$/_1_1_7/' $OUTPUT/f64_to_ui64_rz.tv
+sed -ie 's/$/_3_1_7/' $OUTPUT/f64_to_ui64_ru.tv
+sed -ie 's/$/_2_1_7/' $OUTPUT/f64_to_ui64_rd.tv
+sed -ie 's/$/_4_1_7/' $OUTPUT/f64_to_ui64_rnm.tv
+echo "Editing f128_to_ui64 test vectors"
+sed -ie 's/$/_0_3_7/' $OUTPUT/f128_to_ui64_rne.tv
+sed -ie 's/$/_1_3_7/' $OUTPUT/f128_to_ui64_rz.tv
+sed -ie 's/$/_3_3_7/' $OUTPUT/f128_to_ui64_ru.tv
+sed -ie 's/$/_2_3_7/' $OUTPUT/f128_to_ui64_rd.tv
+sed -ie 's/$/_4_3_7/' $OUTPUT/f128_to_ui64_rnm.tv
+echo "Editing f16_to_i32 test vectors"
+sed -ie 's/$/_0_2_1/' $OUTPUT/f16_to_i32_rne.tv
+sed -ie 's/$/_1_2_1/' $OUTPUT/f16_to_i32_rz.tv
+sed -ie 's/$/_3_2_1/' $OUTPUT/f16_to_i32_ru.tv
+sed -ie 's/$/_2_2_1/' $OUTPUT/f16_to_i32_rd.tv
+sed -ie 's/$/_4_2_1/' $OUTPUT/f16_to_i32_rnm.tv
+echo "Editing f32_to_i32 test vectors"
+sed -ie 's/$/_0_0_1/' $OUTPUT/f32_to_i32_rne.tv
+sed -ie 's/$/_1_0_1/' $OUTPUT/f32_to_i32_rz.tv
+sed -ie 's/$/_3_0_1/' $OUTPUT/f32_to_i32_ru.tv
+sed -ie 's/$/_2_0_1/' $OUTPUT/f32_to_i32_rd.tv
+sed -ie 's/$/_4_0_1/' $OUTPUT/f32_to_i32_rnm.tv
+echo "Editing f64_to_i32 test vectors"
+sed -ie 's/$/_0_1_1/' $OUTPUT/f64_to_i32_rne.tv
+sed -ie 's/$/_1_1_1/' $OUTPUT/f64_to_i32_rz.tv
+sed -ie 's/$/_3_1_1/' $OUTPUT/f64_to_i32_ru.tv
+sed -ie 's/$/_2_1_1/' $OUTPUT/f64_to_i32_rd.tv
+sed -ie 's/$/_4_1_1/' $OUTPUT/f64_to_i32_rnm.tv
+echo "Editing f128_to_i32 test vectors"
+sed -ie 's/$/_0_3_1/' $OUTPUT/f128_to_i32_rne.tv
+sed -ie 's/$/_1_3_1/' $OUTPUT/f128_to_i32_rz.tv
+sed -ie 's/$/_3_3_1/' $OUTPUT/f128_to_i32_ru.tv
+sed -ie 's/$/_2_3_1/' $OUTPUT/f128_to_i32_rd.tv
+sed -ie 's/$/_4_3_1/' $OUTPUT/f128_to_i32_rnm.tv
+echo "Editing f16_to_i64 test vectors"
+sed -ie 's/$/_0_2_5/' $OUTPUT/f16_to_i64_rne.tv
+sed -ie 's/$/_1_2_5/' $OUTPUT/f16_to_i64_rz.tv
+sed -ie 's/$/_3_2_5/' $OUTPUT/f16_to_i64_ru.tv
+sed -ie 's/$/_2_2_5/' $OUTPUT/f16_to_i64_rd.tv
+sed -ie 's/$/_4_2_5/' $OUTPUT/f16_to_i64_rnm.tv
+echo "Editing f32_to_i64 test vectors"
+sed -ie 's/$/_0_0_5/' $OUTPUT/f32_to_i64_rne.tv
+sed -ie 's/$/_1_0_5/' $OUTPUT/f32_to_i64_rz.tv
+sed -ie 's/$/_3_0_5/' $OUTPUT/f32_to_i64_ru.tv
+sed -ie 's/$/_2_0_5/' $OUTPUT/f32_to_i64_rd.tv
+sed -ie 's/$/_4_0_5/' $OUTPUT/f32_to_i64_rnm.tv
+echo "Editing f64_to_i64 test vectors"
+sed -ie 's/$/_0_1_5/' $OUTPUT/f64_to_i64_rne.tv
+sed -ie 's/$/_1_1_5/' $OUTPUT/f64_to_i64_rz.tv
+sed -ie 's/$/_3_1_5/' $OUTPUT/f64_to_i64_ru.tv
+sed -ie 's/$/_2_1_5/' $OUTPUT/f64_to_i64_rd.tv
+sed -ie 's/$/_4_1_5/' $OUTPUT/f64_to_i64_rnm.tv
+echo "Editing f128_to_i64 test vectors"
+sed -ie 's/$/_0_3_5/' $OUTPUT/f128_to_i64_rne.tv
+sed -ie 's/$/_1_3_5/' $OUTPUT/f128_to_i64_rz.tv
+sed -ie 's/$/_3_3_5/' $OUTPUT/f128_to_i64_ru.tv
+sed -ie 's/$/_2_3_5/' $OUTPUT/f128_to_i64_rd.tv
+sed -ie 's/$/_4_3_5/' $OUTPUT/f128_to_i64_rnm.tv
+echo "Editing f16_to_f32 test vectors"
+sed -ie 's/$/_0_2_2/' $OUTPUT/f16_to_f32_rne.tv
+sed -ie 's/$/_1_2_2/' $OUTPUT/f16_to_f32_rz.tv
+sed -ie 's/$/_3_2_2/' $OUTPUT/f16_to_f32_ru.tv
+sed -ie 's/$/_2_2_2/' $OUTPUT/f16_to_f32_rd.tv
+sed -ie 's/$/_4_2_2/' $OUTPUT/f16_to_f32_rnm.tv
+echo "Editing f16_to_f64 test vectors"
+sed -ie 's/$/_0_2_2/' $OUTPUT/f16_to_f64_rne.tv
+sed -ie 's/$/_1_2_2/' $OUTPUT/f16_to_f64_rz.tv
+sed -ie 's/$/_3_2_2/' $OUTPUT/f16_to_f64_ru.tv
+sed -ie 's/$/_2_2_2/' $OUTPUT/f16_to_f64_rd.tv
+sed -ie 's/$/_4_2_2/' $OUTPUT/f16_to_f64_rnm.tv
+echo "Editing f16_to_f128 test vectors"
+sed -ie 's/$/_0_2_2/' $OUTPUT/f16_to_f128_rne.tv
+sed -ie 's/$/_1_2_2/' $OUTPUT/f16_to_f128_rz.tv
+sed -ie 's/$/_3_2_2/' $OUTPUT/f16_to_f128_ru.tv
+sed -ie 's/$/_2_2_2/' $OUTPUT/f16_to_f128_rd.tv
+sed -ie 's/$/_4_2_2/' $OUTPUT/f16_to_f128_rnm.tv
+echo "Editing f32_to_f16 test vectors"
+sed -ie 's/$/_0_0_0/' $OUTPUT/f32_to_f16_rne.tv
+sed -ie 's/$/_1_0_0/' $OUTPUT/f32_to_f16_rz.tv
+sed -ie 's/$/_3_0_0/' $OUTPUT/f32_to_f16_ru.tv
+sed -ie 's/$/_2_0_0/' $OUTPUT/f32_to_f16_rd.tv
+sed -ie 's/$/_4_0_0/' $OUTPUT/f32_to_f16_rnm.tv
+echo "Editing f32_to_f64 test vectors"
+sed -ie 's/$/_0_0_0/' $OUTPUT/f32_to_f64_rne.tv
+sed -ie 's/$/_1_0_0/' $OUTPUT/f32_to_f64_rz.tv
+sed -ie 's/$/_3_0_0/' $OUTPUT/f32_to_f64_ru.tv
+sed -ie 's/$/_2_0_0/' $OUTPUT/f32_to_f64_rd.tv
+sed -ie 's/$/_4_0_0/' $OUTPUT/f32_to_f64_rnm.tv
+echo "Editing f32_to_f128 test vectors"
+sed -ie 's/$/_0_0_0/' $OUTPUT/f32_to_f128_rne.tv
+sed -ie 's/$/_1_0_0/' $OUTPUT/f32_to_f128_rz.tv
+sed -ie 's/$/_3_0_0/' $OUTPUT/f32_to_f128_ru.tv
+sed -ie 's/$/_2_0_0/' $OUTPUT/f32_to_f128_rd.tv
+sed -ie 's/$/_4_0_0/' $OUTPUT/f32_to_f128_rnm.tv
+echo "Editing f64_to_f16 test vectors"
+sed -ie 's/$/_0_1_1/' $OUTPUT/f64_to_f16_rne.tv
+sed -ie 's/$/_1_1_1/' $OUTPUT/f64_to_f16_rz.tv
+sed -ie 's/$/_3_1_1/' $OUTPUT/f64_to_f16_ru.tv
+sed -ie 's/$/_2_1_1/' $OUTPUT/f64_to_f16_rd.tv
+sed -ie 's/$/_4_1_1/' $OUTPUT/f64_to_f16_rnm.tv
+echo "Editing f64_to_f32 test vectors"
+sed -ie 's/$/_0_1_1/' $OUTPUT/f64_to_f32_rne.tv
+sed -ie 's/$/_1_1_1/' $OUTPUT/f64_to_f32_rz.tv
+sed -ie 's/$/_3_1_1/' $OUTPUT/f64_to_f32_ru.tv
+sed -ie 's/$/_2_1_1/' $OUTPUT/f64_to_f32_rd.tv
+sed -ie 's/$/_4_1_1/' $OUTPUT/f64_to_f32_rnm.tv
+echo "Editing f64_to_f128 test vectors"
+sed -ie 's/$/_0_1_1/' $OUTPUT/f64_to_f128_rne.tv
+sed -ie 's/$/_1_1_1/' $OUTPUT/f64_to_f128_rz.tv
+sed -ie 's/$/_3_1_1/' $OUTPUT/f64_to_f128_ru.tv
+sed -ie 's/$/_2_1_1/' $OUTPUT/f64_to_f128_rd.tv
+sed -ie 's/$/_4_1_1/' $OUTPUT/f64_to_f128_rnm.tv
+echo "Editing f128_to_f16 test vectors"
+sed -ie 's/$/_0_3_3/' $OUTPUT/f128_to_f16_rne.tv
+sed -ie 's/$/_1_3_3/' $OUTPUT/f128_to_f16_rz.tv
+sed -ie 's/$/_3_3_3/' $OUTPUT/f128_to_f16_ru.tv
+sed -ie 's/$/_2_3_3/' $OUTPUT/f128_to_f16_rd.tv
+sed -ie 's/$/_4_3_3/' $OUTPUT/f128_to_f16_rnm.tv
+echo "Editing f128_to_f32 test vectors"
+sed -ie 's/$/_0_3_3/' $OUTPUT/f128_to_f32_rne.tv
+sed -ie 's/$/_1_3_3/' $OUTPUT/f128_to_f32_rz.tv
+sed -ie 's/$/_3_3_3/' $OUTPUT/f128_to_f32_ru.tv
+sed -ie 's/$/_2_3_3/' $OUTPUT/f128_to_f32_rd.tv
+sed -ie 's/$/_4_3_3/' $OUTPUT/f128_to_f32_rnm.tv
+echo "Editing f128_to_f64 test vectors"
+sed -ie 's/$/_0_3_3/' $OUTPUT/f128_to_f64_rne.tv
+sed -ie 's/$/_1_3_3/' $OUTPUT/f128_to_f64_rz.tv
+sed -ie 's/$/_3_3_3/' $OUTPUT/f128_to_f64_ru.tv
+sed -ie 's/$/_2_3_3/' $OUTPUT/f128_to_f64_rd.tv
+sed -ie 's/$/_4_3_3/' $OUTPUT/f128_to_f64_rnm.tv
+echo "Editing f16_add test vectors"
+sed -ie 's/$/_0_2_6/' $OUTPUT/f16_add_rne.tv
+sed -ie 's/$/_1_2_6/' $OUTPUT/f16_add_rz.tv
+sed -ie 's/$/_3_2_6/' $OUTPUT/f16_add_ru.tv
+sed -ie 's/$/_2_2_6/' $OUTPUT/f16_add_rd.tv
+sed -ie 's/$/_4_2_6/' $OUTPUT/f16_add_rnm.tv
+echo "Editing f32_add test vectors"
+sed -ie 's/$/_0_0_6/' $OUTPUT/f32_add_rne.tv
+sed -ie 's/$/_1_0_6/' $OUTPUT/f32_add_rz.tv
+sed -ie 's/$/_3_0_6/' $OUTPUT/f32_add_ru.tv
+sed -ie 's/$/_2_0_6/' $OUTPUT/f32_add_rd.tv
+sed -ie 's/$/_4_0_6/' $OUTPUT/f32_add_rnm.tv
+echo "Editing f64_add test vectors"
+sed -ie 's/$/_0_1_6/' $OUTPUT/f64_add_rne.tv
+sed -ie 's/$/_1_1_6/' $OUTPUT/f64_add_rz.tv
+sed -ie 's/$/_3_1_6/' $OUTPUT/f64_add_ru.tv
+sed -ie 's/$/_2_1_6/' $OUTPUT/f64_add_rd.tv
+sed -ie 's/$/_4_1_6/' $OUTPUT/f64_add_rnm.tv
+echo "Editing f128_add test vectors"
+sed -ie 's/$/_0_3_6/' $OUTPUT/f128_add_rne.tv
+sed -ie 's/$/_1_3_6/' $OUTPUT/f128_add_rz.tv
+sed -ie 's/$/_3_3_6/' $OUTPUT/f128_add_ru.tv
+sed -ie 's/$/_2_3_6/' $OUTPUT/f128_add_rd.tv
+sed -ie 's/$/_4_3_6/' $OUTPUT/f128_add_rnm.tv
+echo "Editing f16_sub test vectors"
+sed -ie 's/$/_0_2_7/' $OUTPUT/f16_sub_rne.tv
+sed -ie 's/$/_1_2_7/' $OUTPUT/f16_sub_rz.tv
+sed -ie 's/$/_3_2_7/' $OUTPUT/f16_sub_ru.tv
+sed -ie 's/$/_2_2_7/' $OUTPUT/f16_sub_rd.tv
+sed -ie 's/$/_4_2_7/' $OUTPUT/f16_sub_rnm.tv
+echo "Editing f32_sub test vectors"
+sed -ie 's/$/_0_0_7/' $OUTPUT/f32_sub_rne.tv
+sed -ie 's/$/_1_0_7/' $OUTPUT/f32_sub_rz.tv
+sed -ie 's/$/_3_0_7/' $OUTPUT/f32_sub_ru.tv
+sed -ie 's/$/_2_0_7/' $OUTPUT/f32_sub_rd.tv
+sed -ie 's/$/_4_0_7/' $OUTPUT/f32_sub_rnm.tv
+echo "Editing f64_sub test vectors"
+sed -ie 's/$/_0_1_7/' $OUTPUT/f64_sub_rne.tv
+sed -ie 's/$/_1_1_7/' $OUTPUT/f64_sub_rz.tv
+sed -ie 's/$/_3_1_7/' $OUTPUT/f64_sub_ru.tv
+sed -ie 's/$/_2_1_7/' $OUTPUT/f64_sub_rd.tv
+sed -ie 's/$/_4_1_7/' $OUTPUT/f64_sub_rnm.tv
+echo "Editing f128_sub test vectors"
+sed -ie 's/$/_0_3_7/' $OUTPUT/f128_sub_rne.tv
+sed -ie 's/$/_1_3_7/' $OUTPUT/f128_sub_rz.tv
+sed -ie 's/$/_3_3_7/' $OUTPUT/f128_sub_ru.tv
+sed -ie 's/$/_2_3_7/' $OUTPUT/f128_sub_rd.tv
+sed -ie 's/$/_4_3_7/' $OUTPUT/f128_sub_rnm.tv
+echo "Editing f16_mul test vectors"
+sed -ie 's/$/_0_2_4/' $OUTPUT/f16_mul_rne.tv
+sed -ie 's/$/_1_2_4/' $OUTPUT/f16_mul_rz.tv
+sed -ie 's/$/_3_2_4/' $OUTPUT/f16_mul_ru.tv
+sed -ie 's/$/_2_2_4/' $OUTPUT/f16_mul_rd.tv
+sed -ie 's/$/_4_2_4/' $OUTPUT/f16_mul_rnm.tv
+echo "Editing f32_mul test vectors"
+sed -ie 's/$/_0_0_4/' $OUTPUT/f32_mul_rne.tv
+sed -ie 's/$/_1_0_4/' $OUTPUT/f32_mul_rz.tv
+sed -ie 's/$/_3_0_4/' $OUTPUT/f32_mul_ru.tv
+sed -ie 's/$/_2_0_4/' $OUTPUT/f32_mul_rd.tv
+sed -ie 's/$/_4_0_4/' $OUTPUT/f32_mul_rnm.tv
+echo "Editing f64_mul test vectors"
+sed -ie 's/$/_0_1_4/' $OUTPUT/f64_mul_rne.tv
+sed -ie 's/$/_1_1_4/' $OUTPUT/f64_mul_rz.tv
+sed -ie 's/$/_3_1_4/' $OUTPUT/f64_mul_ru.tv
+sed -ie 's/$/_2_1_4/' $OUTPUT/f64_mul_rd.tv
+sed -ie 's/$/_4_1_4/' $OUTPUT/f64_mul_rnm.tv
+echo "Editing f128_mul test vectors"
+sed -ie 's/$/_0_3_4/' $OUTPUT/f128_mul_rne.tv
+sed -ie 's/$/_1_3_4/' $OUTPUT/f128_mul_rz.tv
+sed -ie 's/$/_3_3_4/' $OUTPUT/f128_mul_ru.tv
+sed -ie 's/$/_2_3_4/' $OUTPUT/f128_mul_rd.tv
+sed -ie 's/$/_4_3_4/' $OUTPUT/f128_mul_rnm.tv
+echo "Editing f16_div test vectors"
+sed -ie 's/$/_0_2_0/' $OUTPUT/f16_div_rne.tv
+sed -ie 's/$/_1_2_0/' $OUTPUT/f16_div_rz.tv
+sed -ie 's/$/_3_2_0/' $OUTPUT/f16_div_ru.tv
+sed -ie 's/$/_2_2_0/' $OUTPUT/f16_div_rd.tv
+sed -ie 's/$/_4_2_0/' $OUTPUT/f16_div_rnm.tv
+echo "Editing f32_div test vectors"
+sed -ie 's/$/_0_0_0/' $OUTPUT/f32_div_rne.tv
+sed -ie 's/$/_1_0_0/' $OUTPUT/f32_div_rz.tv
+sed -ie 's/$/_3_0_0/' $OUTPUT/f32_div_ru.tv
+sed -ie 's/$/_2_0_0/' $OUTPUT/f32_div_rd.tv
+sed -ie 's/$/_4_0_0/' $OUTPUT/f32_div_rnm.tv
+echo "Editing f64_div test vectors"
+sed -ie 's/$/_0_1_0/' $OUTPUT/f64_div_rne.tv
+sed -ie 's/$/_1_1_0/' $OUTPUT/f64_div_rz.tv
+sed -ie 's/$/_3_1_0/' $OUTPUT/f64_div_ru.tv
+sed -ie 's/$/_2_1_0/' $OUTPUT/f64_div_rd.tv
+sed -ie 's/$/_4_1_0/' $OUTPUT/f64_div_rnm.tv
+echo "Editing f128_div test vectors"
+sed -ie 's/$/_0_3_0/' $OUTPUT/f128_div_rne.tv
+sed -ie 's/$/_1_3_0/' $OUTPUT/f128_div_rz.tv
+sed -ie 's/$/_3_3_0/' $OUTPUT/f128_div_ru.tv
+sed -ie 's/$/_2_3_0/' $OUTPUT/f128_div_rd.tv
+sed -ie 's/$/_4_3_0/' $OUTPUT/f128_div_rnm.tv
+echo "Editing f16_sqrt test vectors"
+sed -ie 's/$/_0_2_1/' $OUTPUT/f16_sqrt_rne.tv
+sed -ie 's/$/_1_2_1/' $OUTPUT/f16_sqrt_rz.tv
+sed -ie 's/$/_3_2_1/' $OUTPUT/f16_sqrt_ru.tv
+sed -ie 's/$/_2_2_1/' $OUTPUT/f16_sqrt_rd.tv
+sed -ie 's/$/_4_2_1/' $OUTPUT/f16_sqrt_rnm.tv
+echo "Editing f32_sqrt test vectors"
+sed -ie 's/$/_0_0_1/' $OUTPUT/f32_sqrt_rne.tv
+sed -ie 's/$/_1_0_1/' $OUTPUT/f32_sqrt_rz.tv
+sed -ie 's/$/_3_0_1/' $OUTPUT/f32_sqrt_ru.tv
+sed -ie 's/$/_2_0_1/' $OUTPUT/f32_sqrt_rd.tv
+sed -ie 's/$/_4_0_1/' $OUTPUT/f32_sqrt_rnm.tv
+echo "Editing f64_sqrt test vectors"
+sed -ie 's/$/_0_1_1/' $OUTPUT/f64_sqrt_rne.tv
+sed -ie 's/$/_1_1_1/' $OUTPUT/f64_sqrt_rz.tv
+sed -ie 's/$/_3_1_1/' $OUTPUT/f64_sqrt_ru.tv
+sed -ie 's/$/_2_1_1/' $OUTPUT/f64_sqrt_rd.tv
+sed -ie 's/$/_4_1_1/' $OUTPUT/f64_sqrt_rnm.tv
+echo "Editing f128_sqrt test vectors"
+sed -ie 's/$/_0_3_1/' $OUTPUT/f128_sqrt_rne.tv
+sed -ie 's/$/_1_3_1/' $OUTPUT/f128_sqrt_rz.tv
+sed -ie 's/$/_3_3_1/' $OUTPUT/f128_sqrt_ru.tv
+sed -ie 's/$/_2_3_1/' $OUTPUT/f128_sqrt_rd.tv
+sed -ie 's/$/_4_3_1/' $OUTPUT/f128_sqrt_rnm.tv
+echo "Editing f16_eq test vectors"
+sed -ie 's/$/_0_2_2/' $OUTPUT/f16_eq_rne.tv
+sed -ie 's/$/_1_2_2/' $OUTPUT/f16_eq_rz.tv
+sed -ie 's/$/_3_2_2/' $OUTPUT/f16_eq_ru.tv
+sed -ie 's/$/_2_2_2/' $OUTPUT/f16_eq_rd.tv
+sed -ie 's/$/_4_2_2/' $OUTPUT/f16_eq_rnm.tv
+echo "Editing f32_eq test vectors"
+sed -ie 's/$/_0_0_2/' $OUTPUT/f32_eq_rne.tv
+sed -ie 's/$/_1_0_2/' $OUTPUT/f32_eq_rz.tv
+sed -ie 's/$/_3_0_2/' $OUTPUT/f32_eq_ru.tv
+sed -ie 's/$/_2_0_2/' $OUTPUT/f32_eq_rd.tv
+sed -ie 's/$/_4_0_2/' $OUTPUT/f32_eq_rnm.tv
+echo "Editing f64_eq test vectors"
+sed -ie 's/$/_0_1_2/' $OUTPUT/f64_eq_rne.tv
+sed -ie 's/$/_1_1_2/' $OUTPUT/f64_eq_rz.tv
+sed -ie 's/$/_3_1_2/' $OUTPUT/f64_eq_ru.tv
+sed -ie 's/$/_2_1_2/' $OUTPUT/f64_eq_rd.tv
+sed -ie 's/$/_4_1_2/' $OUTPUT/f64_eq_rnm.tv
+echo "Editing f128_eq test vectors"
+sed -ie 's/$/_0_3_2/' $OUTPUT/f128_eq_rne.tv
+sed -ie 's/$/_1_3_2/' $OUTPUT/f128_eq_rz.tv
+sed -ie 's/$/_3_3_2/' $OUTPUT/f128_eq_ru.tv
+sed -ie 's/$/_2_3_2/' $OUTPUT/f128_eq_rd.tv
+sed -ie 's/$/_4_3_2/' $OUTPUT/f128_eq_rnm.tv
+echo "Editing f16_le test vectors"
+sed -ie 's/$/_0_2_3/' $OUTPUT/f16_le_rne.tv
+sed -ie 's/$/_1_2_3/' $OUTPUT/f16_le_rz.tv
+sed -ie 's/$/_3_2_3/' $OUTPUT/f16_le_ru.tv
+sed -ie 's/$/_2_2_3/' $OUTPUT/f16_le_rd.tv
+sed -ie 's/$/_4_2_3/' $OUTPUT/f16_le_rnm.tv
+echo "Editing f32_le test vectors"
+sed -ie 's/$/_0_0_3/' $OUTPUT/f32_le_rne.tv
+sed -ie 's/$/_1_0_3/' $OUTPUT/f32_le_rz.tv
+sed -ie 's/$/_3_0_3/' $OUTPUT/f32_le_ru.tv
+sed -ie 's/$/_2_0_3/' $OUTPUT/f32_le_rd.tv
+sed -ie 's/$/_4_0_3/' $OUTPUT/f32_le_rnm.tv
+echo "Editing f64_le test vectors"
+sed -ie 's/$/_0_1_3/' $OUTPUT/f64_le_rne.tv
+sed -ie 's/$/_1_1_3/' $OUTPUT/f64_le_rz.tv
+sed -ie 's/$/_3_1_3/' $OUTPUT/f64_le_ru.tv
+sed -ie 's/$/_2_1_3/' $OUTPUT/f64_le_rd.tv
+sed -ie 's/$/_4_1_3/' $OUTPUT/f64_le_rnm.tv
+echo "Editing f128_le test vectors"
+sed -ie 's/$/_0_3_3/' $OUTPUT/f128_le_rne.tv
+sed -ie 's/$/_1_3_3/' $OUTPUT/f128_le_rz.tv
+sed -ie 's/$/_3_3_3/' $OUTPUT/f128_le_ru.tv
+sed -ie 's/$/_2_3_3/' $OUTPUT/f128_le_rd.tv
+sed -ie 's/$/_4_3_3/' $OUTPUT/f128_le_rnm.tv
+echo "Editing f16_lt test vectors"
+sed -ie 's/$/_0_2_1/' $OUTPUT/f16_lt_rne.tv
+sed -ie 's/$/_1_2_1/' $OUTPUT/f16_lt_rz.tv
+sed -ie 's/$/_3_2_1/' $OUTPUT/f16_lt_ru.tv
+sed -ie 's/$/_2_2_1/' $OUTPUT/f16_lt_rd.tv
+sed -ie 's/$/_4_2_1/' $OUTPUT/f16_lt_rnm.tv
+echo "Editing f32_lt test vectors"
+sed -ie 's/$/_0_0_1/' $OUTPUT/f32_lt_rne.tv
+sed -ie 's/$/_1_0_1/' $OUTPUT/f32_lt_rz.tv
+sed -ie 's/$/_3_0_1/' $OUTPUT/f32_lt_ru.tv
+sed -ie 's/$/_2_0_1/' $OUTPUT/f32_lt_rd.tv
+sed -ie 's/$/_4_0_1/' $OUTPUT/f32_lt_rnm.tv
+echo "Editing f64_lt test vectors"
+sed -ie 's/$/_0_1_1/' $OUTPUT/f64_lt_rne.tv
+sed -ie 's/$/_1_1_1/' $OUTPUT/f64_lt_rz.tv
+sed -ie 's/$/_3_1_1/' $OUTPUT/f64_lt_ru.tv
+sed -ie 's/$/_2_1_1/' $OUTPUT/f64_lt_rd.tv
+sed -ie 's/$/_4_1_1/' $OUTPUT/f64_lt_rnm.tv
+echo "Editing f128_lt test vectors"
+sed -ie 's/$/_0_3_1/' $OUTPUT/f128_lt_rne.tv
+sed -ie 's/$/_1_3_1/' $OUTPUT/f128_lt_rz.tv
+sed -ie 's/$/_3_3_1/' $OUTPUT/f128_lt_ru.tv
+sed -ie 's/$/_2_3_1/' $OUTPUT/f128_lt_rd.tv
+sed -ie 's/$/_4_3_1/' $OUTPUT/f128_lt_rnm.tv
+echo "Editing f16_mulAdd test vectors"
+sed -ie 's/$/_0_2_0/' $OUTPUT/f16_mulAdd_rne.tv
+sed -ie 's/$/_1_2_0/' $OUTPUT/f16_mulAdd_rz.tv
+sed -ie 's/$/_3_2_0/' $OUTPUT/f16_mulAdd_ru.tv
+sed -ie 's/$/_2_2_0/' $OUTPUT/f16_mulAdd_rd.tv
+sed -ie 's/$/_4_2_0/' $OUTPUT/f16_mulAdd_rnm.tv
+echo "Editing f32_mulAdd test vectors"
+sed -ie 's/$/_0_0_0/' $OUTPUT/f32_mulAdd_rne.tv
+sed -ie 's/$/_1_0_0/' $OUTPUT/f32_mulAdd_rz.tv
+sed -ie 's/$/_3_0_0/' $OUTPUT/f32_mulAdd_ru.tv
+sed -ie 's/$/_2_0_0/' $OUTPUT/f32_mulAdd_rd.tv
+sed -ie 's/$/_4_0_0/' $OUTPUT/f32_mulAdd_rnm.tv
+echo "Editing f64_mulAdd test vectors"
+sed -ie 's/$/_0_1_0/' $OUTPUT/f64_mulAdd_rne.tv
+sed -ie 's/$/_1_1_0/' $OUTPUT/f64_mulAdd_rz.tv
+sed -ie 's/$/_3_1_0/' $OUTPUT/f64_mulAdd_ru.tv
+sed -ie 's/$/_2_1_0/' $OUTPUT/f64_mulAdd_rd.tv
+sed -ie 's/$/_4_1_0/' $OUTPUT/f64_mulAdd_rnm.tv
+echo "Editing f128_mulAdd test vectors"
+sed -ie 's/$/_0_3_0/' $OUTPUT/f128_mulAdd_rne.tv
+sed -ie 's/$/_1_3_0/' $OUTPUT/f128_mulAdd_rz.tv
+sed -ie 's/$/_3_3_0/' $OUTPUT/f128_mulAdd_ru.tv
+sed -ie 's/$/_2_3_0/' $OUTPUT/f128_mulAdd_rd.tv
+sed -ie 's/$/_4_3_0/' $OUTPUT/f128_mulAdd_rnm.tv
+rm vectors/*.tve

tests/fp/create_vectors.sh

@@ -0,0 +1,483 @@
+#!/bin/sh
+BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
+OUTPUT="./vectors"
+echo "Creating ui32_to_f16 convert vectors"
+$BUILD/testfloat_gen -rnear_even ui32_to_f16 > $OUTPUT/ui32_to_f16_rne.tv
+$BUILD/testfloat_gen -rminMag ui32_to_f16 > $OUTPUT/ui32_to_f16_rz.tv
+$BUILD/testfloat_gen -rmax ui32_to_f16 > $OUTPUT/ui32_to_f16_ru.tv
+$BUILD/testfloat_gen -rmin ui32_to_f16 > $OUTPUT/ui32_to_f16_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag ui32_to_f16 > $OUTPUT/ui32_to_f16_rnm.tv
+echo "Creating ui32_to_f32 convert vectors"
+$BUILD/testfloat_gen -rnear_even ui32_to_f32 > $OUTPUT/ui32_to_f32_rne.tv
+$BUILD/testfloat_gen -rminMag ui32_to_f32 > $OUTPUT/ui32_to_f32_rz.tv
+$BUILD/testfloat_gen -rmax ui32_to_f32 > $OUTPUT/ui32_to_f32_ru.tv
+$BUILD/testfloat_gen -rmin ui32_to_f32 > $OUTPUT/ui32_to_f32_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag ui32_to_f32 > $OUTPUT/ui32_to_f32_rnm.tv
+echo "Creating ui32_to_f64 convert vectors"
+$BUILD/testfloat_gen -rnear_even ui32_to_f64 > $OUTPUT/ui32_to_f64_rne.tv
+$BUILD/testfloat_gen -rminMag ui32_to_f64 > $OUTPUT/ui32_to_f64_rz.tv
+$BUILD/testfloat_gen -rmax ui32_to_f64 > $OUTPUT/ui32_to_f64_ru.tv
+$BUILD/testfloat_gen -rmin ui32_to_f64 > $OUTPUT/ui32_to_f64_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag ui32_to_f64 > $OUTPUT/ui32_to_f64_rnm.tv
+echo "Creating ui32_to_f128 convert vectors"
+$BUILD/testfloat_gen -rnear_even ui32_to_f128 > $OUTPUT/ui32_to_f128_rne.tv
+$BUILD/testfloat_gen -rminMag ui32_to_f128 > $OUTPUT/ui32_to_f128_rz.tv
+$BUILD/testfloat_gen -rmax ui32_to_f128 > $OUTPUT/ui32_to_f128_ru.tv
+$BUILD/testfloat_gen -rmin ui32_to_f128 > $OUTPUT/ui32_to_f128_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag ui32_to_f128 > $OUTPUT/ui32_to_f128_rnm.tv
+echo "Creating ui64_to_f16 convert vectors"
+$BUILD/testfloat_gen -rnear_even ui64_to_f16 > $OUTPUT/ui64_to_f16_rne.tv
+$BUILD/testfloat_gen -rminMag ui64_to_f16 > $OUTPUT/ui64_to_f16_rz.tv
+$BUILD/testfloat_gen -rmax ui64_to_f16 > $OUTPUT/ui64_to_f16_ru.tv
+$BUILD/testfloat_gen -rmin ui64_to_f16 > $OUTPUT/ui64_to_f16_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag ui64_to_f16 > $OUTPUT/ui64_to_f16_rnm.tv
+echo "Creating ui64_to_f32 convert vectors"
+$BUILD/testfloat_gen -rnear_even ui64_to_f32 > $OUTPUT/ui64_to_f32_rne.tv
+$BUILD/testfloat_gen -rminMag ui64_to_f32 > $OUTPUT/ui64_to_f32_rz.tv
+$BUILD/testfloat_gen -rmax ui64_to_f32 > $OUTPUT/ui64_to_f32_ru.tv
+$BUILD/testfloat_gen -rmin ui64_to_f32 > $OUTPUT/ui64_to_f32_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag ui64_to_f32 > $OUTPUT/ui64_to_f32_rnm.tv
+echo "Creating ui64_to_f64 convert vectors"
+$BUILD/testfloat_gen -rnear_even ui64_to_f64 > $OUTPUT/ui64_to_f64_rne.tv
+$BUILD/testfloat_gen -rminMag ui64_to_f64 > $OUTPUT/ui64_to_f64_rz.tv
+$BUILD/testfloat_gen -rmax ui64_to_f64 > $OUTPUT/ui64_to_f64_ru.tv
+$BUILD/testfloat_gen -rmin ui64_to_f64 > $OUTPUT/ui64_to_f64_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag ui64_to_f64 > $OUTPUT/ui64_to_f64_rnm.tv
+echo "Creating ui64_to_f128 convert vectors"
+$BUILD/testfloat_gen -rnear_even ui64_to_f128 > $OUTPUT/ui64_to_f128_rne.tv
+$BUILD/testfloat_gen -rminMag ui64_to_f128 > $OUTPUT/ui64_to_f128_rz.tv
+$BUILD/testfloat_gen -rmax ui64_to_f128 > $OUTPUT/ui64_to_f128_ru.tv
+$BUILD/testfloat_gen -rmin ui64_to_f128 > $OUTPUT/ui64_to_f128_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag ui64_to_f128 > $OUTPUT/ui64_to_f128_rnm.tv
+echo "Creating i32_to_f16 convert vectors"
+$BUILD/testfloat_gen -rnear_even i32_to_f16 > $OUTPUT/i32_to_f16_rne.tv
+$BUILD/testfloat_gen -rminMag i32_to_f16 > $OUTPUT/i32_to_f16_rz.tv
+$BUILD/testfloat_gen -rmax i32_to_f16 > $OUTPUT/i32_to_f16_ru.tv
+$BUILD/testfloat_gen -rmin i32_to_f16 > $OUTPUT/i32_to_f16_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag i32_to_f16 > $OUTPUT/i32_to_f16_rnm.tv
+echo "Creating i32_to_f32 convert vectors"
+$BUILD/testfloat_gen -rnear_even i32_to_f32 > $OUTPUT/i32_to_f32_rne.tv
+$BUILD/testfloat_gen -rminMag i32_to_f32 > $OUTPUT/i32_to_f32_rz.tv
+$BUILD/testfloat_gen -rmax i32_to_f32 > $OUTPUT/i32_to_f32_ru.tv
+$BUILD/testfloat_gen -rmin i32_to_f32 > $OUTPUT/i32_to_f32_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag i32_to_f32 > $OUTPUT/i32_to_f32_rnm.tv
+echo "Creating i32_to_f64 convert vectors"
+$BUILD/testfloat_gen -rnear_even i32_to_f64 > $OUTPUT/i32_to_f64_rne.tv
+$BUILD/testfloat_gen -rminMag i32_to_f64 > $OUTPUT/i32_to_f64_rz.tv
+$BUILD/testfloat_gen -rmax i32_to_f64 > $OUTPUT/i32_to_f64_ru.tv
+$BUILD/testfloat_gen -rmin i32_to_f64 > $OUTPUT/i32_to_f64_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag i32_to_f64 > $OUTPUT/i32_to_f64_rnm.tv
+echo "Creating i32_to_f128 convert vectors"
+$BUILD/testfloat_gen -rnear_even i32_to_f128 > $OUTPUT/i32_to_f128_rne.tv
+$BUILD/testfloat_gen -rminMag i32_to_f128 > $OUTPUT/i32_to_f128_rz.tv
+$BUILD/testfloat_gen -rmax i32_to_f128 > $OUTPUT/i32_to_f128_ru.tv
+$BUILD/testfloat_gen -rmin i32_to_f128 > $OUTPUT/i32_to_f128_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag i32_to_f128 > $OUTPUT/i32_to_f128_rnm.tv
+echo "Creating i64_to_f16 convert vectors"
+$BUILD/testfloat_gen -rnear_even i64_to_f16 > $OUTPUT/i64_to_f16_rne.tv
+$BUILD/testfloat_gen -rminMag i64_to_f16 > $OUTPUT/i64_to_f16_rz.tv
+$BUILD/testfloat_gen -rmax i64_to_f16 > $OUTPUT/i64_to_f16_ru.tv
+$BUILD/testfloat_gen -rmin i64_to_f16 > $OUTPUT/i64_to_f16_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag i64_to_f16 > $OUTPUT/i64_to_f16_rnm.tv
+echo "Creating i64_to_f32 convert vectors"
+$BUILD/testfloat_gen -rnear_even i64_to_f32 > $OUTPUT/i64_to_f32_rne.tv
+$BUILD/testfloat_gen -rminMag i64_to_f32 > $OUTPUT/i64_to_f32_rz.tv
+$BUILD/testfloat_gen -rmax i64_to_f32 > $OUTPUT/i64_to_f32_ru.tv
+$BUILD/testfloat_gen -rmin i64_to_f32 > $OUTPUT/i64_to_f32_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag i64_to_f32 > $OUTPUT/i64_to_f32_rnm.tv
+echo "Creating i64_to_f64 convert vectors"
+$BUILD/testfloat_gen -rnear_even i64_to_f64 > $OUTPUT/i64_to_f64_rne.tv
+$BUILD/testfloat_gen -rminMag i64_to_f64 > $OUTPUT/i64_to_f64_rz.tv
+$BUILD/testfloat_gen -rmax i64_to_f64 > $OUTPUT/i64_to_f64_ru.tv
+$BUILD/testfloat_gen -rmin i64_to_f64 > $OUTPUT/i64_to_f64_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag i64_to_f64 > $OUTPUT/i64_to_f64_rnm.tv
+echo "Creating i64_to_f128 convert vectors"
+$BUILD/testfloat_gen -rnear_even i64_to_f128 > $OUTPUT/i64_to_f128_rne.tv
+$BUILD/testfloat_gen -rminMag i64_to_f128 > $OUTPUT/i64_to_f128_rz.tv
+$BUILD/testfloat_gen -rmax i64_to_f128 > $OUTPUT/i64_to_f128_ru.tv
+$BUILD/testfloat_gen -rmin i64_to_f128 > $OUTPUT/i64_to_f128_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag i64_to_f128 > $OUTPUT/i64_to_f128_rnm.tv
+echo "Creating f16_to_ui32 convert vectors"
+$BUILD/testfloat_gen -rnear_even f16_to_ui32 > $OUTPUT/f16_to_ui32_rne.tv
+$BUILD/testfloat_gen -rminMag f16_to_ui32 > $OUTPUT/f16_to_ui32_rz.tv
+$BUILD/testfloat_gen -rmax f16_to_ui32 > $OUTPUT/f16_to_ui32_ru.tv
+$BUILD/testfloat_gen -rmin f16_to_ui32 > $OUTPUT/f16_to_ui32_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f16_to_ui32 > $OUTPUT/f16_to_ui32_rnm.tv
+echo "Creating f32_to_ui32 convert vectors"
+$BUILD/testfloat_gen -rnear_even f32_to_ui32 > $OUTPUT/f32_to_ui32_rne.tv
+$BUILD/testfloat_gen -rminMag f32_to_ui32 > $OUTPUT/f32_to_ui32_rz.tv
+$BUILD/testfloat_gen -rmax f32_to_ui32 > $OUTPUT/f32_to_ui32_ru.tv
+$BUILD/testfloat_gen -rmin f32_to_ui32 > $OUTPUT/f32_to_ui32_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f32_to_ui32 > $OUTPUT/f32_to_ui32_rnm.tv
+echo "Creating f64_to_ui32 convert vectors"
+$BUILD/testfloat_gen -rnear_even f64_to_ui32 > $OUTPUT/f64_to_ui32_rne.tv
+$BUILD/testfloat_gen -rminMag f64_to_ui32 > $OUTPUT/f64_to_ui32_rz.tv
+$BUILD/testfloat_gen -rmax f64_to_ui32 > $OUTPUT/f64_to_ui32_ru.tv
+$BUILD/testfloat_gen -rmin f64_to_ui32 > $OUTPUT/f64_to_ui32_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f64_to_ui32 > $OUTPUT/f64_to_ui32_rnm.tv
+echo "Creating f128_to_ui32 convert vectors"
+$BUILD/testfloat_gen -rnear_even f128_to_ui32 > $OUTPUT/f128_to_ui32_rne.tv
+$BUILD/testfloat_gen -rminMag f128_to_ui32 > $OUTPUT/f128_to_ui32_rz.tv
+$BUILD/testfloat_gen -rmax f128_to_ui32 > $OUTPUT/f128_to_ui32_ru.tv
+$BUILD/testfloat_gen -rmin f128_to_ui32 > $OUTPUT/f128_to_ui32_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f128_to_ui32 > $OUTPUT/f128_to_ui32_rnm.tv
+echo "Creating f16_to_ui64 convert vectors"
+$BUILD/testfloat_gen -rnear_even f16_to_ui64 > $OUTPUT/f16_to_ui64_rne.tv
+$BUILD/testfloat_gen -rminMag f16_to_ui64 > $OUTPUT/f16_to_ui64_rz.tv
+$BUILD/testfloat_gen -rmax f16_to_ui64 > $OUTPUT/f16_to_ui64_ru.tv
+$BUILD/testfloat_gen -rmin f16_to_ui64 > $OUTPUT/f16_to_ui64_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f16_to_ui64 > $OUTPUT/f16_to_ui64_rnm.tv
+echo "Creating f32_to_ui64 convert vectors"
+$BUILD/testfloat_gen -rnear_even f32_to_ui64 > $OUTPUT/f32_to_ui64_rne.tv
+$BUILD/testfloat_gen -rminMag f32_to_ui64 > $OUTPUT/f32_to_ui64_rz.tv
+$BUILD/testfloat_gen -rmax f32_to_ui64 > $OUTPUT/f32_to_ui64_ru.tv
+$BUILD/testfloat_gen -rmin f32_to_ui64 > $OUTPUT/f32_to_ui64_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f32_to_ui64 > $OUTPUT/f32_to_ui64_rnm.tv
+echo "Creating f64_to_ui64 convert vectors"
+$BUILD/testfloat_gen -rnear_even f64_to_ui64 > $OUTPUT/f64_to_ui64_rne.tv
+$BUILD/testfloat_gen -rminMag f64_to_ui64 > $OUTPUT/f64_to_ui64_rz.tv
+$BUILD/testfloat_gen -rmax f64_to_ui64 > $OUTPUT/f64_to_ui64_ru.tv
+$BUILD/testfloat_gen -rmin f64_to_ui64 > $OUTPUT/f64_to_ui64_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f64_to_ui64 > $OUTPUT/f64_to_ui64_rnm.tv
+echo "Creating f128_to_ui64 convert vectors"
+$BUILD/testfloat_gen -rnear_even f128_to_ui64 > $OUTPUT/f128_to_ui64_rne.tv
+$BUILD/testfloat_gen -rminMag f128_to_ui64 > $OUTPUT/f128_to_ui64_rz.tv
+$BUILD/testfloat_gen -rmax f128_to_ui64 > $OUTPUT/f128_to_ui64_ru.tv
+$BUILD/testfloat_gen -rmin f128_to_ui64 > $OUTPUT/f128_to_ui64_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f128_to_ui64 > $OUTPUT/f128_to_ui64_rnm.tv
+echo "Creating f16_to_i32 convert vectors"
+$BUILD/testfloat_gen -rnear_even f16_to_i32 > $OUTPUT/f16_to_i32_rne.tv
+$BUILD/testfloat_gen -rminMag f16_to_i32 > $OUTPUT/f16_to_i32_rz.tv
+$BUILD/testfloat_gen -rmax f16_to_i32 > $OUTPUT/f16_to_i32_ru.tv
+$BUILD/testfloat_gen -rmin f16_to_i32 > $OUTPUT/f16_to_i32_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f16_to_i32 > $OUTPUT/f16_to_i32_rnm.tv
+echo "Creating f32_to_i32 convert vectors"
+$BUILD/testfloat_gen -rnear_even f32_to_i32 > $OUTPUT/f32_to_i32_rne.tv
+$BUILD/testfloat_gen -rminMag f32_to_i32 > $OUTPUT/f32_to_i32_rz.tv
+$BUILD/testfloat_gen -rmax f32_to_i32 > $OUTPUT/f32_to_i32_ru.tv
+$BUILD/testfloat_gen -rmin f32_to_i32 > $OUTPUT/f32_to_i32_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f32_to_i32 > $OUTPUT/f32_to_i32_rnm.tv
+echo "Creating f64_to_i32 convert vectors"
+$BUILD/testfloat_gen -rnear_even f64_to_i32 > $OUTPUT/f64_to_i32_rne.tv
+$BUILD/testfloat_gen -rminMag f64_to_i32 > $OUTPUT/f64_to_i32_rz.tv
+$BUILD/testfloat_gen -rmax f64_to_i32 > $OUTPUT/f64_to_i32_ru.tv
+$BUILD/testfloat_gen -rmin f64_to_i32 > $OUTPUT/f64_to_i32_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f64_to_i32 > $OUTPUT/f64_to_i32_rnm.tv
+echo "Creating f128_to_i32 convert vectors"
+$BUILD/testfloat_gen -rnear_even f128_to_i32 > $OUTPUT/f128_to_i32_rne.tv
+$BUILD/testfloat_gen -rminMag f128_to_i32 > $OUTPUT/f128_to_i32_rz.tv
+$BUILD/testfloat_gen -rmax f128_to_i32 > $OUTPUT/f128_to_i32_ru.tv
+$BUILD/testfloat_gen -rmin f128_to_i32 > $OUTPUT/f128_to_i32_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f128_to_i32 > $OUTPUT/f128_to_i32_rnm.tv
+echo "Creating f16_to_i64 convert vectors"
+$BUILD/testfloat_gen -rnear_even f16_to_i64 > $OUTPUT/f16_to_i64_rne.tv
+$BUILD/testfloat_gen -rminMag f16_to_i64 > $OUTPUT/f16_to_i64_rz.tv
+$BUILD/testfloat_gen -rmax f16_to_i64 > $OUTPUT/f16_to_i64_ru.tv
+$BUILD/testfloat_gen -rmin f16_to_i64 > $OUTPUT/f16_to_i64_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f16_to_i64 > $OUTPUT/f16_to_i64_rnm.tv
+echo "Creating f32_to_i64 convert vectors"
+$BUILD/testfloat_gen -rnear_even f32_to_i64 > $OUTPUT/f32_to_i64_rne.tv
+$BUILD/testfloat_gen -rminMag f32_to_i64 > $OUTPUT/f32_to_i64_rz.tv
+$BUILD/testfloat_gen -rmax f32_to_i64 > $OUTPUT/f32_to_i64_ru.tv
+$BUILD/testfloat_gen -rmin f32_to_i64 > $OUTPUT/f32_to_i64_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f32_to_i64 > $OUTPUT/f32_to_i64_rnm.tv
+echo "Creating f64_to_i64 convert vectors"
+$BUILD/testfloat_gen -rnear_even f64_to_i64 > $OUTPUT/f64_to_i64_rne.tv
+$BUILD/testfloat_gen -rminMag f64_to_i64 > $OUTPUT/f64_to_i64_rz.tv
+$BUILD/testfloat_gen -rmax f64_to_i64 > $OUTPUT/f64_to_i64_ru.tv
+$BUILD/testfloat_gen -rmin f64_to_i64 > $OUTPUT/f64_to_i64_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f64_to_i64 > $OUTPUT/f64_to_i64_rnm.tv
+echo "Creating f128_to_i64 convert vectors"
+$BUILD/testfloat_gen -rnear_even f128_to_i64 > $OUTPUT/f128_to_i64_rne.tv
+$BUILD/testfloat_gen -rminMag f128_to_i64 > $OUTPUT/f128_to_i64_rz.tv
+$BUILD/testfloat_gen -rmax f128_to_i64 > $OUTPUT/f128_to_i64_ru.tv
+$BUILD/testfloat_gen -rmin f128_to_i64 > $OUTPUT/f128_to_i64_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f128_to_i64 > $OUTPUT/f128_to_i64_rnm.tv
+echo "Creating f16_to_f32 convert vectors"
+$BUILD/testfloat_gen -rnear_even f16_to_f32 > $OUTPUT/f16_to_f32_rne.tv
+$BUILD/testfloat_gen -rminMag f16_to_f32 > $OUTPUT/f16_to_f32_rz.tv
+$BUILD/testfloat_gen -rmax f16_to_f32 > $OUTPUT/f16_to_f32_ru.tv
+$BUILD/testfloat_gen -rmin f16_to_f32 > $OUTPUT/f16_to_f32_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f16_to_f32 > $OUTPUT/f16_to_f32_rnm.tv
+echo "Creating f16_to_f64 convert vectors"
+$BUILD/testfloat_gen -rnear_even f16_to_f64 > $OUTPUT/f16_to_f64_rne.tv
+$BUILD/testfloat_gen -rminMag f16_to_f64 > $OUTPUT/f16_to_f64_rz.tv
+$BUILD/testfloat_gen -rmax f16_to_f64 > $OUTPUT/f16_to_f64_ru.tv
+$BUILD/testfloat_gen -rmin f16_to_f64 > $OUTPUT/f16_to_f64_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f16_to_f64 > $OUTPUT/f16_to_f64_rnm.tv
+echo "Creating f16_to_f128 convert vectors"
+$BUILD/testfloat_gen -rnear_even f16_to_f128 > $OUTPUT/f16_to_f128_rne.tv
+$BUILD/testfloat_gen -rminMag f16_to_f128 > $OUTPUT/f16_to_f128_rz.tv
+$BUILD/testfloat_gen -rmax f16_to_f128 > $OUTPUT/f16_to_f128_ru.tv
+$BUILD/testfloat_gen -rmin f16_to_f128 > $OUTPUT/f16_to_f128_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f16_to_f128 > $OUTPUT/f16_to_f128_rnm.tv
+echo "Creating f32_to_f16 convert vectors"
+$BUILD/testfloat_gen -rnear_even f32_to_f16 > $OUTPUT/f32_to_f16_rne.tv
+$BUILD/testfloat_gen -rminMag f32_to_f16 > $OUTPUT/f32_to_f16_rz.tv
+$BUILD/testfloat_gen -rmax f32_to_f16 > $OUTPUT/f32_to_f16_ru.tv
+$BUILD/testfloat_gen -rmin f32_to_f16 > $OUTPUT/f32_to_f16_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f32_to_f16 > $OUTPUT/f32_to_f16_rnm.tv
+echo "Creating f32_to_f64 convert vectors"
+$BUILD/testfloat_gen -rnear_even f32_to_f64 > $OUTPUT/f32_to_f64_rne.tv
+$BUILD/testfloat_gen -rminMag f32_to_f64 > $OUTPUT/f32_to_f64_rz.tv
+$BUILD/testfloat_gen -rmax f32_to_f64 > $OUTPUT/f32_to_f64_ru.tv
+$BUILD/testfloat_gen -rmin f32_to_f64 > $OUTPUT/f32_to_f64_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f32_to_f64 > $OUTPUT/f32_to_f64_rnm.tv
+echo "Creating f32_to_f128 convert vectors"
+$BUILD/testfloat_gen -rnear_even f32_to_f128 > $OUTPUT/f32_to_f128_rne.tv
+$BUILD/testfloat_gen -rminMag f32_to_f128 > $OUTPUT/f32_to_f128_rz.tv
+$BUILD/testfloat_gen -rmax f32_to_f128 > $OUTPUT/f32_to_f128_ru.tv
+$BUILD/testfloat_gen -rmin f32_to_f128 > $OUTPUT/f32_to_f128_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f32_to_f128 > $OUTPUT/f32_to_f128_rnm.tv
+echo "Creating f64_to_f16 convert vectors"
+$BUILD/testfloat_gen -rnear_even f64_to_f16 > $OUTPUT/f64_to_f16_rne.tv
+$BUILD/testfloat_gen -rminMag f64_to_f16 > $OUTPUT/f64_to_f16_rz.tv
+$BUILD/testfloat_gen -rmax f64_to_f16 > $OUTPUT/f64_to_f16_ru.tv
+$BUILD/testfloat_gen -rmin f64_to_f16 > $OUTPUT/f64_to_f16_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f64_to_f16 > $OUTPUT/f64_to_f16_rnm.tv
+echo "Creating f64_to_f32 convert vectors"
+$BUILD/testfloat_gen -rnear_even f64_to_f32 > $OUTPUT/f64_to_f32_rne.tv
+$BUILD/testfloat_gen -rminMag f64_to_f32 > $OUTPUT/f64_to_f32_rz.tv
+$BUILD/testfloat_gen -rmax f64_to_f32 > $OUTPUT/f64_to_f32_ru.tv
+$BUILD/testfloat_gen -rmin f64_to_f32 > $OUTPUT/f64_to_f32_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f64_to_f32 > $OUTPUT/f64_to_f32_rnm.tv
+echo "Creating f64_to_f128 convert vectors"
+$BUILD/testfloat_gen -rnear_even f64_to_f128 > $OUTPUT/f64_to_f128_rne.tv
+$BUILD/testfloat_gen -rminMag f64_to_f128 > $OUTPUT/f64_to_f128_rz.tv
+$BUILD/testfloat_gen -rmax f64_to_f128 > $OUTPUT/f64_to_f128_ru.tv
+$BUILD/testfloat_gen -rmin f64_to_f128 > $OUTPUT/f64_to_f128_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f64_to_f128 > $OUTPUT/f64_to_f128_rnm.tv
+echo "Creating f128_to_f16 convert vectors"
+$BUILD/testfloat_gen -rnear_even f128_to_f16 > $OUTPUT/f128_to_f16_rne.tv
+$BUILD/testfloat_gen -rminMag f128_to_f16 > $OUTPUT/f128_to_f16_rz.tv
+$BUILD/testfloat_gen -rmax f128_to_f16 > $OUTPUT/f128_to_f16_ru.tv
+$BUILD/testfloat_gen -rmin f128_to_f16 > $OUTPUT/f128_to_f16_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f128_to_f16 > $OUTPUT/f128_to_f16_rnm.tv
+echo "Creating f128_to_f32 convert vectors"
+$BUILD/testfloat_gen -rnear_even f128_to_f32 > $OUTPUT/f128_to_f32_rne.tv
+$BUILD/testfloat_gen -rminMag f128_to_f32 > $OUTPUT/f128_to_f32_rz.tv
+$BUILD/testfloat_gen -rmax f128_to_f32 > $OUTPUT/f128_to_f32_ru.tv
+$BUILD/testfloat_gen -rmin f128_to_f32 > $OUTPUT/f128_to_f32_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f128_to_f32 > $OUTPUT/f128_to_f32_rnm.tv
+echo "Creating f128_to_f64 convert vectors"
+$BUILD/testfloat_gen -rnear_even f128_to_f64 > $OUTPUT/f128_to_f64_rne.tv
+$BUILD/testfloat_gen -rminMag f128_to_f64 > $OUTPUT/f128_to_f64_rz.tv
+$BUILD/testfloat_gen -rmax f128_to_f64 > $OUTPUT/f128_to_f64_ru.tv
+$BUILD/testfloat_gen -rmin f128_to_f64 > $OUTPUT/f128_to_f64_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f128_to_f64 > $OUTPUT/f128_to_f64_rnm.tv
+echo "Creating f16_add vectors"
+$BUILD/testfloat_gen -rnear_even f16_add > $OUTPUT/f16_add_rne.tv
+$BUILD/testfloat_gen -rminMag f16_add > $OUTPUT/f16_add_rz.tv
+$BUILD/testfloat_gen -rmax f16_add > $OUTPUT/f16_add_ru.tv
+$BUILD/testfloat_gen -rmin f16_add > $OUTPUT/f16_add_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f16_add > $OUTPUT/f16_add_rnm.tv
+echo "Creating f32_add vectors"
+$BUILD/testfloat_gen -rnear_even f32_add > $OUTPUT/f32_add_rne.tv
+$BUILD/testfloat_gen -rminMag f32_add > $OUTPUT/f32_add_rz.tv
+$BUILD/testfloat_gen -rmax f32_add > $OUTPUT/f32_add_ru.tv
+$BUILD/testfloat_gen -rmin f32_add > $OUTPUT/f32_add_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f32_add > $OUTPUT/f32_add_rnm.tv
+echo "Creating f64_add vectors"
+$BUILD/testfloat_gen -rnear_even f64_add > $OUTPUT/f64_add_rne.tv
+$BUILD/testfloat_gen -rminMag f64_add > $OUTPUT/f64_add_rz.tv
+$BUILD/testfloat_gen -rmax f64_add > $OUTPUT/f64_add_ru.tv
+$BUILD/testfloat_gen -rmin f64_add > $OUTPUT/f64_add_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f64_add > $OUTPUT/f64_add_rnm.tv
+echo "Creating f128_add vectors"
+$BUILD/testfloat_gen -rnear_even f128_add > $OUTPUT/f128_add_rne.tv
+$BUILD/testfloat_gen -rminMag f128_add > $OUTPUT/f128_add_rz.tv
+$BUILD/testfloat_gen -rmax f128_add > $OUTPUT/f128_add_ru.tv
+$BUILD/testfloat_gen -rmin f128_add > $OUTPUT/f128_add_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f128_add > $OUTPUT/f128_add_rnm.tv
+echo "Creating f16_sub vectors"
+$BUILD/testfloat_gen -rnear_even f16_sub > $OUTPUT/f16_sub_rne.tv
+$BUILD/testfloat_gen -rminMag f16_sub > $OUTPUT/f16_sub_rz.tv
+$BUILD/testfloat_gen -rmax f16_sub > $OUTPUT/f16_sub_ru.tv
+$BUILD/testfloat_gen -rmin f16_sub > $OUTPUT/f16_sub_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f16_sub > $OUTPUT/f16_sub_rnm.tv
+echo "Creating f32_sub vectors"
+$BUILD/testfloat_gen -rnear_even f32_sub > $OUTPUT/f32_sub_rne.tv
+$BUILD/testfloat_gen -rminMag f32_sub > $OUTPUT/f32_sub_rz.tv
+$BUILD/testfloat_gen -rmax f32_sub > $OUTPUT/f32_sub_ru.tv
+$BUILD/testfloat_gen -rmin f32_sub > $OUTPUT/f32_sub_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f32_sub > $OUTPUT/f32_sub_rnm.tv
+echo "Creating f64_sub vectors"
+$BUILD/testfloat_gen -rnear_even f64_sub > $OUTPUT/f64_sub_rne.tv
+$BUILD/testfloat_gen -rminMag f64_sub > $OUTPUT/f64_sub_rz.tv
+$BUILD/testfloat_gen -rmax f64_sub > $OUTPUT/f64_sub_ru.tv
+$BUILD/testfloat_gen -rmin f64_sub > $OUTPUT/f64_sub_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f64_sub > $OUTPUT/f64_sub_rnm.tv
+echo "Creating f128_sub vectors"
+$BUILD/testfloat_gen -rnear_even f128_sub > $OUTPUT/f128_sub_rne.tv
+$BUILD/testfloat_gen -rminMag f128_sub > $OUTPUT/f128_sub_rz.tv
+$BUILD/testfloat_gen -rmax f128_sub > $OUTPUT/f128_sub_ru.tv
+$BUILD/testfloat_gen -rmin f128_sub > $OUTPUT/f128_sub_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f128_sub > $OUTPUT/f128_sub_rnm.tv
+echo "Creating f16_mul vectors"
+$BUILD/testfloat_gen -rnear_even f16_mul > $OUTPUT/f16_mul_rne.tv
+$BUILD/testfloat_gen -rminMag f16_mul > $OUTPUT/f16_mul_rz.tv
+$BUILD/testfloat_gen -rmax f16_mul > $OUTPUT/f16_mul_ru.tv
+$BUILD/testfloat_gen -rmin f16_mul > $OUTPUT/f16_mul_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f16_mul > $OUTPUT/f16_mul_rnm.tv
+echo "Creating f32_mul vectors"
+$BUILD/testfloat_gen -rnear_even f32_mul > $OUTPUT/f32_mul_rne.tv
+$BUILD/testfloat_gen -rminMag f32_mul > $OUTPUT/f32_mul_rz.tv
+$BUILD/testfloat_gen -rmax f32_mul > $OUTPUT/f32_mul_ru.tv
+$BUILD/testfloat_gen -rmin f32_mul > $OUTPUT/f32_mul_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f32_mul > $OUTPUT/f32_mul_rnm.tv
+echo "Creating f64_mul vectors"
+$BUILD/testfloat_gen -rnear_even f64_mul > $OUTPUT/f64_mul_rne.tv
+$BUILD/testfloat_gen -rminMag f64_mul > $OUTPUT/f64_mul_rz.tv
+$BUILD/testfloat_gen -rmax f64_mul > $OUTPUT/f64_mul_ru.tv
+$BUILD/testfloat_gen -rmin f64_mul > $OUTPUT/f64_mul_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f64_mul > $OUTPUT/f64_mul_rnm.tv
+echo "Creating f128_mul vectors"
+$BUILD/testfloat_gen -rnear_even f128_mul > $OUTPUT/f128_mul_rne.tv
+$BUILD/testfloat_gen -rminMag f128_mul > $OUTPUT/f128_mul_rz.tv
+$BUILD/testfloat_gen -rmax f128_mul > $OUTPUT/f128_mul_ru.tv
+$BUILD/testfloat_gen -rmin f128_mul > $OUTPUT/f128_mul_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f128_mul > $OUTPUT/f128_mul_rnm.tv
+echo "Creating f16_div vectors"
+$BUILD/testfloat_gen -rnear_even f16_div > $OUTPUT/f16_div_rne.tv
+$BUILD/testfloat_gen -rminMag f16_div > $OUTPUT/f16_div_rz.tv
+$BUILD/testfloat_gen -rmax f16_div > $OUTPUT/f16_div_ru.tv
+$BUILD/testfloat_gen -rmin f16_div > $OUTPUT/f16_div_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f16_div > $OUTPUT/f16_div_rnm.tv
+echo "Creating f32_div vectors"
+$BUILD/testfloat_gen -rnear_even f32_div > $OUTPUT/f32_div_rne.tv
+$BUILD/testfloat_gen -rminMag f32_div > $OUTPUT/f32_div_rz.tv
+$BUILD/testfloat_gen -rmax f32_div > $OUTPUT/f32_div_ru.tv
+$BUILD/testfloat_gen -rmin f32_div > $OUTPUT/f32_div_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f32_div > $OUTPUT/f32_div_rnm.tv
+echo "Creating f64_div vectors"
+$BUILD/testfloat_gen -rnear_even f64_div > $OUTPUT/f64_div_rne.tv
+$BUILD/testfloat_gen -rminMag f64_div > $OUTPUT/f64_div_rz.tv
+$BUILD/testfloat_gen -rmax f64_div > $OUTPUT/f64_div_ru.tv
+$BUILD/testfloat_gen -rmin f64_div > $OUTPUT/f64_div_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f64_div > $OUTPUT/f64_div_rnm.tv
+echo "Creating f128_div vectors"
+$BUILD/testfloat_gen -rnear_even f128_div > $OUTPUT/f128_div_rne.tv
+$BUILD/testfloat_gen -rminMag f128_div > $OUTPUT/f128_div_rz.tv
+$BUILD/testfloat_gen -rmax f128_div > $OUTPUT/f128_div_ru.tv
+$BUILD/testfloat_gen -rmin f128_div > $OUTPUT/f128_div_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f128_div > $OUTPUT/f128_div_rnm.tv
+echo "Creating f16_sqrt vectors"
+$BUILD/testfloat_gen -rnear_even f16_sqrt > $OUTPUT/f16_sqrt_rne.tv
+$BUILD/testfloat_gen -rminMag f16_sqrt > $OUTPUT/f16_sqrt_rz.tv
+$BUILD/testfloat_gen -rmax f16_sqrt > $OUTPUT/f16_sqrt_ru.tv
+$BUILD/testfloat_gen -rmin f16_sqrt > $OUTPUT/f16_sqrt_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f16_sqrt > $OUTPUT/f16_sqrt_rnm.tv
+echo "Creating f32_sqrt vectors"
+$BUILD/testfloat_gen -rnear_even f32_sqrt > $OUTPUT/f32_sqrt_rne.tv
+$BUILD/testfloat_gen -rminMag f32_sqrt > $OUTPUT/f32_sqrt_rz.tv
+$BUILD/testfloat_gen -rmax f32_sqrt > $OUTPUT/f32_sqrt_ru.tv
+$BUILD/testfloat_gen -rmin f32_sqrt > $OUTPUT/f32_sqrt_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f32_sqrt > $OUTPUT/f32_sqrt_rnm.tv
+echo "Creating f64_sqrt vectors"
+$BUILD/testfloat_gen -rnear_even f64_sqrt > $OUTPUT/f64_sqrt_rne.tv
+$BUILD/testfloat_gen -rminMag f64_sqrt > $OUTPUT/f64_sqrt_rz.tv
+$BUILD/testfloat_gen -rmax f64_sqrt > $OUTPUT/f64_sqrt_ru.tv
+$BUILD/testfloat_gen -rmin f64_sqrt > $OUTPUT/f64_sqrt_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f64_sqrt > $OUTPUT/f64_sqrt_rnm.tv
+echo "Creating f128_sqrt vectors"
+$BUILD/testfloat_gen -rnear_even f128_sqrt > $OUTPUT/f128_sqrt_rne.tv
+$BUILD/testfloat_gen -rminMag f128_sqrt > $OUTPUT/f128_sqrt_rz.tv
+$BUILD/testfloat_gen -rmax f128_sqrt > $OUTPUT/f128_sqrt_ru.tv
+$BUILD/testfloat_gen -rmin f128_sqrt > $OUTPUT/f128_sqrt_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f128_sqrt > $OUTPUT/f128_sqrt_rnm.tv
+echo "Creating f16_eq vectors"
+$BUILD/testfloat_gen -rnear_even f16_eq > $OUTPUT/f16_eq_rne.tv
+$BUILD/testfloat_gen -rminMag f16_eq > $OUTPUT/f16_eq_rz.tv
+$BUILD/testfloat_gen -rmax f16_eq > $OUTPUT/f16_eq_ru.tv
+$BUILD/testfloat_gen -rmin f16_eq > $OUTPUT/f16_eq_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f16_eq > $OUTPUT/f16_eq_rnm.tv
+echo "Creating f32_eq vectors"
+$BUILD/testfloat_gen -rnear_even f32_eq > $OUTPUT/f32_eq_rne.tv
+$BUILD/testfloat_gen -rminMag f32_eq > $OUTPUT/f32_eq_rz.tv
+$BUILD/testfloat_gen -rmax f32_eq > $OUTPUT/f32_eq_ru.tv
+$BUILD/testfloat_gen -rmin f32_eq > $OUTPUT/f32_eq_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f32_eq > $OUTPUT/f32_eq_rnm.tv
+echo "Creating f64_eq vectors"
+$BUILD/testfloat_gen -rnear_even f64_eq > $OUTPUT/f64_eq_rne.tv
+$BUILD/testfloat_gen -rminMag f64_eq > $OUTPUT/f64_eq_rz.tv
+$BUILD/testfloat_gen -rmax f64_eq > $OUTPUT/f64_eq_ru.tv
+$BUILD/testfloat_gen -rmin f64_eq > $OUTPUT/f64_eq_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f64_eq > $OUTPUT/f64_eq_rnm.tv
+echo "Creating f128_eq vectors"
+$BUILD/testfloat_gen -rnear_even f128_eq > $OUTPUT/f128_eq_rne.tv
+$BUILD/testfloat_gen -rminMag f128_eq > $OUTPUT/f128_eq_rz.tv
+$BUILD/testfloat_gen -rmax f128_eq > $OUTPUT/f128_eq_ru.tv
+$BUILD/testfloat_gen -rmin f128_eq > $OUTPUT/f128_eq_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f128_eq > $OUTPUT/f128_eq_rnm.tv
+echo "Creating f16_le vectors"
+$BUILD/testfloat_gen -rnear_even f16_le > $OUTPUT/f16_le_rne.tv
+$BUILD/testfloat_gen -rminMag f16_le > $OUTPUT/f16_le_rz.tv
+$BUILD/testfloat_gen -rmax f16_le > $OUTPUT/f16_le_ru.tv
+$BUILD/testfloat_gen -rmin f16_le > $OUTPUT/f16_le_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f16_le > $OUTPUT/f16_le_rnm.tv
+echo "Creating f32_le vectors"
+$BUILD/testfloat_gen -rnear_even f32_le > $OUTPUT/f32_le_rne.tv
+$BUILD/testfloat_gen -rminMag f32_le > $OUTPUT/f32_le_rz.tv
+$BUILD/testfloat_gen -rmax f32_le > $OUTPUT/f32_le_ru.tv
+$BUILD/testfloat_gen -rmin f32_le > $OUTPUT/f32_le_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f32_le > $OUTPUT/f32_le_rnm.tv
+echo "Creating f64_le vectors"
+$BUILD/testfloat_gen -rnear_even f64_le > $OUTPUT/f64_le_rne.tv
+$BUILD/testfloat_gen -rminMag f64_le > $OUTPUT/f64_le_rz.tv
+$BUILD/testfloat_gen -rmax f64_le > $OUTPUT/f64_le_ru.tv
+$BUILD/testfloat_gen -rmin f64_le > $OUTPUT/f64_le_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f64_le > $OUTPUT/f64_le_rnm.tv
+echo "Creating f128_le vectors"
+$BUILD/testfloat_gen -rnear_even f128_le > $OUTPUT/f128_le_rne.tv
+$BUILD/testfloat_gen -rminMag f128_le > $OUTPUT/f128_le_rz.tv
+$BUILD/testfloat_gen -rmax f128_le > $OUTPUT/f128_le_ru.tv
+$BUILD/testfloat_gen -rmin f128_le > $OUTPUT/f128_le_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f128_le > $OUTPUT/f128_le_rnm.tv
+echo "Creating f16_lt vectors"
+$BUILD/testfloat_gen -rnear_even f16_lt > $OUTPUT/f16_lt_rne.tv
+$BUILD/testfloat_gen -rminMag f16_lt > $OUTPUT/f16_lt_rz.tv
+$BUILD/testfloat_gen -rmax f16_lt > $OUTPUT/f16_lt_ru.tv
+$BUILD/testfloat_gen -rmin f16_lt > $OUTPUT/f16_lt_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f16_lt > $OUTPUT/f16_lt_rnm.tv
+echo "Creating f32_lt vectors"
+$BUILD/testfloat_gen -rnear_even f32_lt > $OUTPUT/f32_lt_rne.tv
+$BUILD/testfloat_gen -rminMag f32_lt > $OUTPUT/f32_lt_rz.tv
+$BUILD/testfloat_gen -rmax f32_lt > $OUTPUT/f32_lt_ru.tv
+$BUILD/testfloat_gen -rmin f32_lt > $OUTPUT/f32_lt_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f32_lt > $OUTPUT/f32_lt_rnm.tv
+echo "Creating f64_lt vectors"
+$BUILD/testfloat_gen -rnear_even f64_lt > $OUTPUT/f64_lt_rne.tv
+$BUILD/testfloat_gen -rminMag f64_lt > $OUTPUT/f64_lt_rz.tv
+$BUILD/testfloat_gen -rmax f64_lt > $OUTPUT/f64_lt_ru.tv
+$BUILD/testfloat_gen -rmin f64_lt > $OUTPUT/f64_lt_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f64_lt > $OUTPUT/f64_lt_rnm.tv
+echo "Creating f128_lt vectors"
+$BUILD/testfloat_gen -rnear_even f128_lt > $OUTPUT/f128_lt_rne.tv
+$BUILD/testfloat_gen -rminMag f128_lt > $OUTPUT/f128_lt_rz.tv
+$BUILD/testfloat_gen -rmax f128_lt > $OUTPUT/f128_lt_ru.tv
+$BUILD/testfloat_gen -rmin f128_lt > $OUTPUT/f128_lt_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f128_lt > $OUTPUT/f128_lt_rnm.tv
+echo "Creating f16_mulAdd vectors"
+$BUILD/testfloat_gen -rnear_even f16_mulAdd > $OUTPUT/f16_mulAdd_rne.tv
+$BUILD/testfloat_gen -rminMag f16_mulAdd > $OUTPUT/f16_mulAdd_rz.tv
+$BUILD/testfloat_gen -rmax f16_mulAdd > $OUTPUT/f16_mulAdd_ru.tv
+$BUILD/testfloat_gen -rmin f16_mulAdd > $OUTPUT/f16_mulAdd_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f16_mulAdd > $OUTPUT/f16_mulAdd_rnm.tv
+echo "Creating f32_mulAdd vectors"
+$BUILD/testfloat_gen -rnear_even f32_mulAdd > $OUTPUT/f32_mulAdd_rne.tv
+$BUILD/testfloat_gen -rminMag f32_mulAdd > $OUTPUT/f32_mulAdd_rz.tv
+$BUILD/testfloat_gen -rmax f32_mulAdd > $OUTPUT/f32_mulAdd_ru.tv
+$BUILD/testfloat_gen -rmin f32_mulAdd > $OUTPUT/f32_mulAdd_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f32_mulAdd > $OUTPUT/f32_mulAdd_rnm.tv
+echo "Creating f64_mulAdd vectors"
+$BUILD/testfloat_gen -rnear_even f64_mulAdd > $OUTPUT/f64_mulAdd_rne.tv
+$BUILD/testfloat_gen -rminMag f64_mulAdd > $OUTPUT/f64_mulAdd_rz.tv
+$BUILD/testfloat_gen -rmax f64_mulAdd > $OUTPUT/f64_mulAdd_ru.tv
+$BUILD/testfloat_gen -rmin f64_mulAdd > $OUTPUT/f64_mulAdd_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f64_mulAdd > $OUTPUT/f64_mulAdd_rnm.tv
+echo "Creating f128_mulAdd vectors"
+$BUILD/testfloat_gen -rnear_even f128_mulAdd > $OUTPUT/f128_mulAdd_rne.tv
+$BUILD/testfloat_gen -rminMag f128_mulAdd > $OUTPUT/f128_mulAdd_rz.tv
+$BUILD/testfloat_gen -rmax f128_mulAdd > $OUTPUT/f128_mulAdd_ru.tv
+$BUILD/testfloat_gen -rmin f128_mulAdd > $OUTPUT/f128_mulAdd_rd.tv
+$BUILD/testfloat_gen -rnear_maxMag f128_mulAdd > $OUTPUT/f128_mulAdd_rnm.tv

tests/fp/create_vectors128fma.sh

@@ -1,31 +0,0 @@
-#!/bin/sh
-
-BUILD="./TestFloat-3e/build/Linux-x86_64-GCC"
-OUTPUT="./vectors"
-
-$BUILD/testfloat_gen -rnear_even f128_mulAdd > $OUTPUT/f128_mulAdd_rne.tv
-$BUILD/testfloat_gen -rminMag f128_mulAdd > $OUTPUT/f128_mulAdd_rz.tv
-$BUILD/testfloat_gen -rmax f128_mulAdd > $OUTPUT/f128_mulAdd_ru.tv
-$BUILD/testfloat_gen -rmin f128_mulAdd > $OUTPUT/f128_mulAdd_rd.tv
-$BUILD/testfloat_gen -rnear_maxMag f128_mulAdd > $OUTPUT/f128_mulAdd_rnm.tv
-
-# format: X_Y_Z_answer_flags_Frm_Fmt
-sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rne.tv
-sed -ie 's/$/_0/' $OUTPUT/f128_mulAdd_rne.tv
-sed -ie 's/$/_3/' $OUTPUT/f128_mulAdd_rne.tv
-
-sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rz.tv
-sed -ie 's/$/_1/' $OUTPUT/f128_mulAdd_rz.tv
-sed -ie 's/$/_3/' $OUTPUT/f128_mulAdd_rz.tv
-
-sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_ru.tv
-sed -ie 's/$/_3/' $OUTPUT/f128_mulAdd_ru.tv
-sed -ie 's/$/_3/' $OUTPUT/f128_mulAdd_ru.tv
-
-sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rd.tv
-sed -ie 's/$/_2/' $OUTPUT/f128_mulAdd_rd.tv
-sed -ie 's/$/_3/' $OUTPUT/f128_mulAdd_rd.tv
-
-sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rnm.tv
-sed -ie 's/$/_4/' $OUTPUT/f128_mulAdd_rnm.tv
-sed -ie 's/$/_3/' $OUTPUT/f128_mulAdd_rnm.tv

tests/fp/create_vectors16.sh

@@ -1,31 +0,0 @@
-#!/bin/sh
-
-BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
-OUTPUT="./vectors"
-
-$BUILD/testfloat_gen -rnear_even f16_add > $OUTPUT/f16_add_rne.tv
-$BUILD/testfloat_gen -rminMag f16_add > $OUTPUT/f16_add_rz.tv
-$BUILD/testfloat_gen -rmin f16_add > $OUTPUT/f16_add_ru.tv
-$BUILD/testfloat_gen -rmax f16_add > $OUTPUT/f16_add_rd.tv
-
-$BUILD/testfloat_gen -rnear_even f16_sub > $OUTPUT/f16_sub_rne.tv
-$BUILD/testfloat_gen -rminMag f16_sub > $OUTPUT/f16_sub_rz.tv
-$BUILD/testfloat_gen -rmin f16_sub > $OUTPUT/f16_sub_ru.tv
-$BUILD/testfloat_gen -rmax f16_sub > $OUTPUT/f16_sub_rd.tv
-
-$BUILD/testfloat_gen -rnear_even f16_div > $OUTPUT/f16_div_rne.tv
-$BUILD/testfloat_gen -rminMag f16_div > $OUTPUT/f16_div_rz.tv
-$BUILD/testfloat_gen -rmin f16_div > $OUTPUT/f16_div_ru.tv
-$BUILD/testfloat_gen -rmax f16_div > $OUTPUT/f16_div_rd.tv
-
-$BUILD/testfloat_gen -rnear_even f16_sqrt > $OUTPUT/f16_sqrt_rne.tv
-$BUILD/testfloat_gen -rminMag f16_sqrt > $OUTPUT/f16_sqrt_rz.tv
-$BUILD/testfloat_gen -rmin f16_sqrt > $OUTPUT/f16_sqrt_ru.tv
-$BUILD/testfloat_gen -rmax f16_sqrt > $OUTPUT/f16_sqrt_rd.tv
-
-$BUILD/testfloat_gen -rnear_even f16_mul > $OUTPUT/f16_mul_rne.tv
-$BUILD/testfloat_gen -rminMag f16_mul > $OUTPUT/f16_mul_rz.tv
-$BUILD/testfloat_gen -rmax f16_mul > $OUTPUT/f16_mul_ru.tv
-$BUILD/testfloat_gen -rmin f16_mul > $OUTPUT/f16_mul_rd.tv
-
-

tests/fp/create_vectors16fma.sh

@@ -1,31 +0,0 @@
-#!/bin/sh
-
-BUILD="./TestFloat-3e/build/Linux-x86_64-GCC"
-OUTPUT="./vectors"
-
-$BUILD/testfloat_gen -rnear_even f16_mulAdd > $OUTPUT/f16_mulAdd_rne.tv
-$BUILD/testfloat_gen -rminMag f16_mulAdd > $OUTPUT/f16_mulAdd_rz.tv
-$BUILD/testfloat_gen -rmax f16_mulAdd > $OUTPUT/f16_mulAdd_ru.tv
-$BUILD/testfloat_gen -rmin f16_mulAdd > $OUTPUT/f16_mulAdd_rd.tv
-$BUILD/testfloat_gen -rnear_maxMag f16_mulAdd > $OUTPUT/f16_mulAdd_rnm.tv
-
-# format: X_Y_Z_answer_flags_Frm_Fmt
-sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rne.tv
-sed -ie 's/$/_0/' $OUTPUT/f16_mulAdd_rne.tv
-sed -ie 's/$/_2/' $OUTPUT/f16_mulAdd_rne.tv
-
-sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rz.tv
-sed -ie 's/$/_1/' $OUTPUT/f16_mulAdd_rz.tv
-sed -ie 's/$/_2/' $OUTPUT/f16_mulAdd_rz.tv
-
-sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_ru.tv
-sed -ie 's/$/_3/' $OUTPUT/f16_mulAdd_ru.tv
-sed -ie 's/$/_2/' $OUTPUT/f16_mulAdd_ru.tv
-
-sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rd.tv
-sed -ie 's/$/_2/' $OUTPUT/f16_mulAdd_rd.tv
-sed -ie 's/$/_2/' $OUTPUT/f16_mulAdd_rd.tv
-
-sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rnm.tv
-sed -ie 's/$/_4/' $OUTPUT/f16_mulAdd_rnm.tv
-sed -ie 's/$/_2/' $OUTPUT/f16_mulAdd_rnm.tv

tests/fp/create_vectors32.sh

@@ -1,29 +0,0 @@
-#!/bin/sh
-
-BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
-OUTPUT="./vectors"
-
-$BUILD/testfloat_gen -rnear_even f32_add > $OUTPUT/f32_add_rne.tv
-$BUILD/testfloat_gen -rminMag f32_add > $OUTPUT/f32_add_rz.tv
-$BUILD/testfloat_gen -rmax f32_add > $OUTPUT/f32_add_ru.tv
-$BUILD/testfloat_gen -rmin f32_add > $OUTPUT/f32_add_rd.tv
-
-$BUILD/testfloat_gen -rnear_even f32_sub > $OUTPUT/f32_sub_rne.tv
-$BUILD/testfloat_gen -rminMag f32_sub > $OUTPUT/f32_sub_rz.tv
-$BUILD/testfloat_gen -rmax f32_sub > $OUTPUT/f32_sub_ru.tv
-$BUILD/testfloat_gen -rmin f32_sub > $OUTPUT/f32_sub_rd.tv
-
-$BUILD/testfloat_gen -rnear_even f32_div > $OUTPUT/f32_div_rne.tv
-$BUILD/testfloat_gen -rminMag f32_div > $OUTPUT/f32_div_rz.tv
-$BUILD/testfloat_gen -rmax f32_div > $OUTPUT/f32_div_ru.tv
-$BUILD/testfloat_gen -rmin f32_div > $OUTPUT/f32_div_rd.tv
-
-$BUILD/testfloat_gen -rnear_even f32_sqrt > $OUTPUT/f32_sqrt_rne.tv
-$BUILD/testfloat_gen -rminMag f32_sqrt > $OUTPUT/f32_sqrt_rz.tv
-$BUILD/testfloat_gen -rmax f32_sqrt > $OUTPUT/f32_sqrt_ru.tv
-$BUILD/testfloat_gen -rmin f32_sqrt > $OUTPUT/f32_sqrt_rd.tv
-
-$BUILD/testfloat_gen -rnear_even f32_mul > $OUTPUT/f32_mul_rne.tv
-$BUILD/testfloat_gen -rminMag f32_mul > $OUTPUT/f32_mul_rz.tv
-$BUILD/testfloat_gen -rmax f32_mul > $OUTPUT/f32_mul_ru.tv
-$BUILD/testfloat_gen -rmin f32_mul > $OUTPUT/f32_mul_rd.tv

tests/fp/create_vectors32_64.sh

@@ -1,20 +0,0 @@
-#!/bin/sh
-
-BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
-OUTPUT="./vectors"
-
-$BUILD/testfloat_gen -rnear_even f32_to_f64 > $OUTPUT/f32_f64_rne.tv
-$BUILD/testfloat_gen -rminMag f32_to_f64 > $OUTPUT/f32_f64_rz.tv
-$BUILD/testfloat_gen -rmax f32_to_f64 > $OUTPUT/f32_f64_ru.tv
-$BUILD/testfloat_gen -rmin f32_to_f64 > $OUTPUT/f32_f64_rd.tv
-
-$BUILD/testfloat_gen -rnear_even f32_to_i64 > $OUTPUT/f32_i64_rne.tv
-$BUILD/testfloat_gen -rminMag f32_to_i64 > $OUTPUT/f32_i64_rz.tv
-$BUILD/testfloat_gen -rmax f32_to_i64 > $OUTPUT/f32_i64_ru.tv
-$BUILD/testfloat_gen -rmin f32_to_i64 > $OUTPUT/f32_i64_rd.tv
-
-$BUILD/testfloat_gen -rnear_even f32_to_ui64 > $OUTPUT/f32_ui64_rne.tv
-$BUILD/testfloat_gen -rminMag f32_to_ui64 > $OUTPUT/f32_ui64_rz.tv
-$BUILD/testfloat_gen -rmax f32_to_ui64 > $OUTPUT/f32_ui64_ru.tv
-$BUILD/testfloat_gen -rmin f32_to_ui64 > $OUTPUT/f32_ui64_rd.tv
-

tests/fp/create_vectors32cmp.sh

@@ -1,13 +0,0 @@
-#!/bin/sh
-
-BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
-OUTPUT="./vectors"
-
-$BUILD/testfloat_gen f32_eq > $OUTPUT/f32_cmp_eq.tv
-$BUILD/testfloat_gen f32_le > $OUTPUT/f32_cmp_le.tv
-$BUILD/testfloat_gen f32_lt > $OUTPUT/f32_cmp_lt.tv
-
-$BUILD/testfloat_gen f32_eq_signaling > $OUTPUT/f32_cmp_eq_signaling.tv
-$BUILD/testfloat_gen f32_le_quiet > $OUTPUT/f32_cmp_le_quiet.tv
-$BUILD/testfloat_gen f32_lt_quiet > $OUTPUT/f32_cmp_lt_quiet.tv
-

tests/fp/create_vectors32fma.sh

@@ -1,31 +0,0 @@
-#!/bin/sh
-
-BUILD="./TestFloat-3e/build/Linux-x86_64-GCC"
-OUTPUT="./vectors"
-
-$BUILD/testfloat_gen -rnear_even f32_mulAdd > $OUTPUT/f32_mulAdd_rne.tv
-$BUILD/testfloat_gen -rminMag f32_mulAdd > $OUTPUT/f32_mulAdd_rz.tv
-$BUILD/testfloat_gen -rmax f32_mulAdd > $OUTPUT/f32_mulAdd_ru.tv
-$BUILD/testfloat_gen -rmin f32_mulAdd > $OUTPUT/f32_mulAdd_rd.tv
-$BUILD/testfloat_gen -rnear_maxMag f32_mulAdd > $OUTPUT/f32_mulAdd_rnm.tv
-
-# format: X_Y_Z_answer_flags_Frm_Fmt
-sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rne.tv
-sed -ie 's/$/_0/' $OUTPUT/f32_mulAdd_rne.tv
-sed -ie 's/$/_0/' $OUTPUT/f32_mulAdd_rne.tv
-
-sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rz.tv
-sed -ie 's/$/_1/' $OUTPUT/f32_mulAdd_rz.tv
-sed -ie 's/$/_0/' $OUTPUT/f32_mulAdd_rz.tv
-
-sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_ru.tv
-sed -ie 's/$/_3/' $OUTPUT/f32_mulAdd_ru.tv
-sed -ie 's/$/_0/' $OUTPUT/f32_mulAdd_ru.tv
-
-sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rd.tv
-sed -ie 's/$/_2/' $OUTPUT/f32_mulAdd_rd.tv
-sed -ie 's/$/_0/' $OUTPUT/f32_mulAdd_rd.tv
-
-sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rnm.tv
-sed -ie 's/$/_4/' $OUTPUT/f32_mulAdd_rnm.tv
-sed -ie 's/$/_0/' $OUTPUT/f32_mulAdd_rnm.tv

tests/fp/create_vectors64.sh

@@ -1,30 +0,0 @@
-#!/bin/sh
-
-BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
-OUTPUT="./vectors"
-
-$BUILD/testfloat_gen -rnear_even f64_add > $OUTPUT/f64_add_rne.tv
-$BUILD/testfloat_gen -rminMag f64_add > $OUTPUT/f64_add_rz.tv
-$BUILD/testfloat_gen -rmax f64_add > $OUTPUT/f64_add_ru.tv
-$BUILD/testfloat_gen -rmin f64_add > $OUTPUT/f64_add_rd.tv
-
-$BUILD/testfloat_gen -rnear_even f64_sub > $OUTPUT/f64_sub_rne.tv
-$BUILD/testfloat_gen -rminMag f64_sub > $OUTPUT/f64_sub_rz.tv
-$BUILD/testfloat_gen -rmax f64_sub > $OUTPUT/f64_sub_ru.tv
-$BUILD/testfloat_gen -rmin f64_sub > $OUTPUT/f64_sub_rd.tv
-
-$BUILD/testfloat_gen -rnear_even f64_div > $OUTPUT/f64_div_rne.tv
-$BUILD/testfloat_gen -rminMag f64_div > $OUTPUT/f64_div_rz.tv
-$BUILD/testfloat_gen -rmax f64_div > $OUTPUT/f64_div_ru.tv
-$BUILD/testfloat_gen -rmin f64_div > $OUTPUT/f64_div_rd.tv
-
-$BUILD/testfloat_gen -rnear_even f64_sqrt > $OUTPUT/f64_sqrt_rne.tv
-$BUILD/testfloat_gen -rminMag f64_sqrt > $OUTPUT/f64_sqrt_rz.tv
-$BUILD/testfloat_gen -rmax f64_sqrt > $OUTPUT/f64_sqrt_ru.tv
-$BUILD/testfloat_gen -rmin f64_sqrt > $OUTPUT/f64_sqrt_rd.tv
-
-$BUILD/testfloat_gen -rnear_even f64_mul > $OUTPUT/f64_mul_rne.tv
-$BUILD/testfloat_gen -rminMag f64_mul > $OUTPUT/f64_mul_rz.tv
-$BUILD/testfloat_gen -rmax f64_mul > $OUTPUT/f64_mul_ru.tv
-$BUILD/testfloat_gen -rmin f64_mul > $OUTPUT/f64_mul_rd.tv
-

tests/fp/create_vectors64_32.sh

@@ -1,22 +0,0 @@
-#!/bin/sh
-
-BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
-OUTPUT="./vectors"
-
-$BUILD/testfloat_gen -rnear_even f64_to_f32 > $OUTPUT/f64_f32_rne.tv
-$BUILD/testfloat_gen -rminMag f64_to_f32 > $OUTPUT/f64_f32_rz.tv
-$BUILD/testfloat_gen -rmax f64_to_f32 > $OUTPUT/f64_f32_ru.tv
-$BUILD/testfloat_gen -rmin f64_to_f32 > $OUTPUT/f64_f32_rd.tv
-
-$BUILD/testfloat_gen -rnear_even f64_to_i32 > $OUTPUT/f64_i32_rne.tv
-$BUILD/testfloat_gen -rminMag f64_to_i32 > $OUTPUT/f64_i32_rz.tv
-$BUILD/testfloat_gen -rmax f64_to_i32 > $OUTPUT/f64_i32_ru.tv
-$BUILD/testfloat_gen -rmin f64_to_i32 > $OUTPUT/f64_i32_rd.tv
-
-$BUILD/testfloat_gen -rnear_even f64_to_ui32 > $OUTPUT/f64_ui32_rne.tv
-$BUILD/testfloat_gen -rminMag f64_to_ui32 > $OUTPUT/f64_ui32_rz.tv
-$BUILD/testfloat_gen -rmax f64_to_ui32 > $OUTPUT/f64_ui32_ru.tv
-$BUILD/testfloat_gen -rmin f64_to_ui32 > $OUTPUT/f64_ui32_rd.tv
-
-
-

tests/fp/create_vectors64cmp.sh

@@ -1,13 +0,0 @@
-#!/bin/sh
-
-BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
-OUTPUT="./vectors"
-
-$BUILD/testfloat_gen f64_eq > $OUTPUT/f64_cmp_eq.tv
-$BUILD/testfloat_gen f64_le > $OUTPUT/f64_cmp_le.tv
-$BUILD/testfloat_gen f64_lt > $OUTPUT/f64_cmp_lt.tv
-
-$BUILD/testfloat_gen f64_eq_signaling > $OUTPUT/f64_cmp_eq_signaling.tv
-$BUILD/testfloat_gen f64_le_quiet > $OUTPUT/f64_cmp_le_quiet.tv
-$BUILD/testfloat_gen f64_lt_quiet > $OUTPUT/f64_cmp_lt_quiet.tv
-

tests/fp/create_vectors64fma.sh

@@ -1,31 +0,0 @@
-#!/bin/sh
-
-BUILD="./TestFloat-3e/build/Linux-x86_64-GCC"
-OUTPUT="./vectors"
-
-$BUILD/testfloat_gen -rnear_even f64_mulAdd > $OUTPUT/f64_mulAdd_rne.tv
-$BUILD/testfloat_gen -rminMag f64_mulAdd > $OUTPUT/f64_mulAdd_rz.tv
-$BUILD/testfloat_gen -rmax f64_mulAdd > $OUTPUT/f64_mulAdd_ru.tv
-$BUILD/testfloat_gen -rmin f64_mulAdd > $OUTPUT/f64_mulAdd_rd.tv
-$BUILD/testfloat_gen -rnear_maxMag f64_mulAdd > $OUTPUT/f64_mulAdd_rnm.tv
-
-# format: X_Y_Z_answer_flags_Frm_Fmt
-sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rne.tv
-sed -ie 's/$/_0/' $OUTPUT/f64_mulAdd_rne.tv
-sed -ie 's/$/_1/' $OUTPUT/f64_mulAdd_rne.tv
-
-sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rz.tv
-sed -ie 's/$/_1/' $OUTPUT/f64_mulAdd_rz.tv
-sed -ie 's/$/_1/' $OUTPUT/f64_mulAdd_rz.tv
-
-sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_ru.tv
-sed -ie 's/$/_3/' $OUTPUT/f64_mulAdd_ru.tv
-sed -ie 's/$/_1/' $OUTPUT/f64_mulAdd_ru.tv
-
-sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rd.tv
-sed -ie 's/$/_2/' $OUTPUT/f64_mulAdd_rd.tv
-sed -ie 's/$/_1/' $OUTPUT/f64_mulAdd_rd.tv
-
-sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rnm.tv
-sed -ie 's/$/_4/' $OUTPUT/f64_mulAdd_rnm.tv
-sed -ie 's/$/_1/' $OUTPUT/f64_mulAdd_rnm.tv

tests/fp/create_vectorsi.sh

@@ -1,64 +0,0 @@
-#!/bin/sh
-
-BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
-OUTPUT="./vectors"
-
-$BUILD/testfloat_gen -rnear_even -i32_to_f64 > $OUTPUT/i32_f64_rne.tv
-$BUILD/testfloat_gen -rminMag -i32_to_f64 > $OUTPUT/i32_f64_rz.tv
-$BUILD/testfloat_gen -rmax -i32_to_f64 > $OUTPUT/i32_f64_ru.tv
-$BUILD/testfloat_gen -rmin -i32_to_f64 > $OUTPUT/i32_f64_rd.tv
-
-$BUILD/testfloat_gen -rnear_even -i64_to_f64 > $OUTPUT/i64_f64_rne.tv
-$BUILD/testfloat_gen -rminMag -i64_to_f64 > $OUTPUT/i64_f64_rz.tv
-$BUILD/testfloat_gen -rmax -i64_to_f64 > $OUTPUT/i64_f64_ru.tv
-$BUILD/testfloat_gen -rmin -i64_to_f64 > $OUTPUT/i64_f64_rd.tv
-
-$BUILD/testfloat_gen -rnear_even -i32_to_f32 > $OUTPUT/i32_f32_rne.tv
-$BUILD/testfloat_gen -rminMag -i32_to_f32 > $OUTPUT/i32_f32_rz.tv
-$BUILD/testfloat_gen -rmax -i32_to_f32 > $OUTPUT/i32_f32_ru.tv
-$BUILD/testfloat_gen -rmin -i32_to_f32 > $OUTPUT/i32_f32_rd.tv
-
-$BUILD/testfloat_gen -rnear_even -f32_to_i32 > $OUTPUT/f32_i32_rne.tv
-$BUILD/testfloat_gen -rminMag -f32_to_i32 > $OUTPUT/f32_i32_rz.tv
-$BUILD/testfloat_gen -rmax -f32_to_i32 > $OUTPUT/f32_i32_ru.tv
-$BUILD/testfloat_gen -rmin -f32_to_i32 > $OUTPUT/f32_i32_rd.tv
-
-$BUILD/testfloat_gen -rnear_even -f32_to_ui32 > $OUTPUT/f32_ui32_rne.tv
-$BUILD/testfloat_gen -rminMag -f32_to_ui32 > $OUTPUT/f32_ui32_rz.tv
-$BUILD/testfloat_gen -rmax -f32_to_ui32 > $OUTPUT/f32_ui32_ru.tv
-$BUILD/testfloat_gen -rmin -f32_to_ui32 > $OUTPUT/f32_ui32_rd.tv
-
-$BUILD/testfloat_gen -rnear_even -i64_to_f32 > $OUTPUT/i64_f32_rne.tv
-$BUILD/testfloat_gen -rminMag -i64_to_f32 > $OUTPUT/i64_f32_rz.tv
-$BUILD/testfloat_gen -rmax -i64_to_f32 > $OUTPUT/i64_f32_ru.tv
-$BUILD/testfloat_gen -rmin -i64_to_f32 > $OUTPUT/i64_f32_rd.tv
-
-$BUILD/testfloat_gen -rnear_even -ui32_to_f64 > $OUTPUT/ui32_f64_rne.tv
-$BUILD/testfloat_gen -rminMag -ui32_to_f64 > $OUTPUT/ui32_f64_rz.tv
-$BUILD/testfloat_gen -rmax -ui32_to_f64 > $OUTPUT/ui32_f64_ru.tv
-$BUILD/testfloat_gen -rmin -ui32_to_f64 > $OUTPUT/ui32_f64_rd.tv
-
-$BUILD/testfloat_gen -rnear_even -ui64_to_f64 > $OUTPUT/ui64_f64_rne.tv
-$BUILD/testfloat_gen -rminMag -ui64_to_f64 > $OUTPUT/ui64_f64_rz.tv
-$BUILD/testfloat_gen -rmax -ui64_to_f64 > $OUTPUT/ui64_f64_ru.tv
-$BUILD/testfloat_gen -rmin -ui64_to_f64 > $OUTPUT/ui64_f64_rd.tv
-
-$BUILD/testfloat_gen -rnear_even -ui32_to_f32 > $OUTPUT/ui32_f32_rne.tv
-$BUILD/testfloat_gen -rminMag -ui32_to_f32 > $OUTPUT/ui32_f32_rz.tv
-$BUILD/testfloat_gen -rmax -ui32_to_f32 > $OUTPUT/ui32_f32_ru.tv
-$BUILD/testfloat_gen -rmin -ui32_to_f32 > $OUTPUT/ui32_f32_rd.tv
-
-$BUILD/testfloat_gen -rnear_even -ui64_to_f32 > $OUTPUT/ui64_f32_rne.tv
-$BUILD/testfloat_gen -rminMag -ui64_to_f32 > $OUTPUT/ui64_f32_rz.tv
-$BUILD/testfloat_gen -rmax -ui64_to_f32 > $OUTPUT/ui64_f32_ru.tv
-$BUILD/testfloat_gen -rmin -ui64_to_f32 > $OUTPUT/ui64_f32_rd.tv
-
-$BUILD/testfloat_gen -rnear_even -f64_to_i64 > $OUTPUT/f64_i64_rne.tv
-$BUILD/testfloat_gen -rminMag -f64_to_i64 > $OUTPUT/f64_i64_rz.tv
-$BUILD/testfloat_gen -rmax -f64_to_i64 > $OUTPUT/f64_i64_ru.tv
-$BUILD/testfloat_gen -rmin -f64_to_i64 > $OUTPUT/f64_i64_rd.tv
-
-$BUILD/testfloat_gen -rnear_even -f64_to_ui64 > $OUTPUT/f64_ui64_rne.tv
-$BUILD/testfloat_gen -rminMag -f64_to_ui64 > $OUTPUT/f64_ui64_rz.tv
-$BUILD/testfloat_gen -rmax -f64_to_ui64 > $OUTPUT/f64_ui64_ru.tv
-$BUILD/testfloat_gen -rmin -f64_to_ui64 > $OUTPUT/f64_ui64_rd.tv

tests/fp/remove_spaces.sh

@@ -0,0 +1,483 @@
+#!/bin/sh
+BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
+OUTPUT="./vectors"
+echo "Editing ui32_to_f16 test vectors"
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rne.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rz.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_ru.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rd.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rnm.tv
+echo "Editing ui32_to_f32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rnm.tv
+echo "Editing ui32_to_f64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rnm.tv
+echo "Editing ui32_to_f128 test vectors"
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rne.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rz.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_ru.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rd.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rnm.tv
+echo "Editing ui64_to_f16 test vectors"
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rne.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rz.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_ru.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rd.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rnm.tv
+echo "Editing ui64_to_f32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rnm.tv
+echo "Editing ui64_to_f64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rnm.tv
+echo "Editing ui64_to_f128 test vectors"
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rne.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rz.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_ru.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rd.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rnm.tv
+echo "Editing i32_to_f16 test vectors"
+sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rne.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rz.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f16_ru.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rd.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rnm.tv
+echo "Editing i32_to_f32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rnm.tv
+echo "Editing i32_to_f64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rnm.tv
+echo "Editing i32_to_f128 test vectors"
+sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rne.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rz.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f128_ru.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rd.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rnm.tv
+echo "Editing i64_to_f16 test vectors"
+sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rne.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rz.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f16_ru.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rd.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rnm.tv
+echo "Editing i64_to_f32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rnm.tv
+echo "Editing i64_to_f64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rnm.tv
+echo "Editing i64_to_f128 test vectors"
+sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rne.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rz.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f128_ru.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rd.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rnm.tv
+echo "Editing f16_to_ui32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rnm.tv
+echo "Editing f32_to_ui32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rnm.tv
+echo "Editing f64_to_ui32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rnm.tv
+echo "Editing f128_to_ui32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rnm.tv
+echo "Editing f16_to_ui64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rnm.tv
+echo "Editing f32_to_ui64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rnm.tv
+echo "Editing f64_to_ui64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rnm.tv
+echo "Editing f128_to_ui64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rnm.tv
+echo "Editing f16_to_i32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_i32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rnm.tv
+echo "Editing f32_to_i32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_i32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rnm.tv
+echo "Editing f64_to_i32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_i32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rnm.tv
+echo "Editing f128_to_i32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_i32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rnm.tv
+echo "Editing f16_to_i64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_i64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rnm.tv
+echo "Editing f32_to_i64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_i64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rnm.tv
+echo "Editing f64_to_i64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_i64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rnm.tv
+echo "Editing f128_to_i64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_i64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rnm.tv
+echo "Editing f16_to_f32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rnm.tv
+echo "Editing f16_to_f64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rnm.tv
+echo "Editing f16_to_f128 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f128_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rnm.tv
+echo "Editing f32_to_f16 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f16_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rnm.tv
+echo "Editing f32_to_f64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rnm.tv
+echo "Editing f32_to_f128 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f128_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rnm.tv
+echo "Editing f64_to_f16 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f16_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rnm.tv
+echo "Editing f64_to_f32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rnm.tv
+echo "Editing f64_to_f128 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f128_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rnm.tv
+echo "Editing f128_to_f16 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f16_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rnm.tv
+echo "Editing f128_to_f32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rnm.tv
+echo "Editing f128_to_f64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rnm.tv
+echo "Editing f16_add test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_add_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_add_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_add_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_add_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_add_rnm.tv
+echo "Editing f32_add test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_add_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_add_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_add_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_add_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_add_rnm.tv
+echo "Editing f64_add test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_add_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_add_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_add_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_add_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_add_rnm.tv
+echo "Editing f128_add test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_add_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_add_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_add_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_add_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_add_rnm.tv
+echo "Editing f16_sub test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_sub_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_sub_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_sub_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_sub_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_sub_rnm.tv
+echo "Editing f32_sub test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_sub_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_sub_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_sub_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_sub_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_sub_rnm.tv
+echo "Editing f64_sub test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_sub_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_sub_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_sub_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_sub_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_sub_rnm.tv
+echo "Editing f128_sub test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_sub_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_sub_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_sub_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_sub_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_sub_rnm.tv
+echo "Editing f16_mul test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_mul_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_mul_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_mul_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_mul_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_mul_rnm.tv
+echo "Editing f32_mul test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_mul_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_mul_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_mul_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_mul_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_mul_rnm.tv
+echo "Editing f64_mul test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_mul_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_mul_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_mul_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_mul_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_mul_rnm.tv
+echo "Editing f128_mul test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_mul_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_mul_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_mul_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_mul_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_mul_rnm.tv
+echo "Editing f16_div test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_div_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_div_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_div_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_div_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_div_rnm.tv
+echo "Editing f32_div test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_div_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_div_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_div_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_div_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_div_rnm.tv
+echo "Editing f64_div test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_div_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_div_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_div_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_div_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_div_rnm.tv
+echo "Editing f128_div test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_div_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_div_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_div_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_div_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_div_rnm.tv
+echo "Editing f16_sqrt test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_sqrt_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rnm.tv
+echo "Editing f32_sqrt test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_sqrt_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rnm.tv
+echo "Editing f64_sqrt test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_sqrt_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rnm.tv
+echo "Editing f128_sqrt test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_sqrt_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rnm.tv
+echo "Editing f16_eq test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_eq_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_eq_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_eq_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_eq_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_eq_rnm.tv
+echo "Editing f32_eq test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_eq_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_eq_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_eq_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_eq_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_eq_rnm.tv
+echo "Editing f64_eq test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_eq_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_eq_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_eq_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_eq_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_eq_rnm.tv
+echo "Editing f128_eq test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_eq_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_eq_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_eq_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_eq_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_eq_rnm.tv
+echo "Editing f16_le test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_le_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_le_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_le_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_le_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_le_rnm.tv
+echo "Editing f32_le test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_le_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_le_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_le_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_le_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_le_rnm.tv
+echo "Editing f64_le test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_le_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_le_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_le_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_le_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_le_rnm.tv
+echo "Editing f128_le test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_le_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_le_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_le_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_le_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_le_rnm.tv
+echo "Editing f16_lt test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_lt_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_lt_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_lt_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_lt_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_lt_rnm.tv
+echo "Editing f32_lt test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_lt_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_lt_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_lt_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_lt_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_lt_rnm.tv
+echo "Editing f64_lt test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_lt_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_lt_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_lt_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_lt_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_lt_rnm.tv
+echo "Editing f128_lt test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_lt_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_lt_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_lt_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_lt_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_lt_rnm.tv
+echo "Editing f16_mulAdd test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rnm.tv
+echo "Editing f32_mulAdd test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rnm.tv
+echo "Editing f64_mulAdd test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rnm.tv
+echo "Editing f128_mulAdd test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rnm.tv

tests/fp/run_all.sh

@@ -1,14 +1,5 @@
 #!/bin/sh
 
-./create_vectors16.sh
+./create_vectors.sh
-./create_vectors32_64.sh
+./remove_spaces.sh
-./create_vectors32cmp.sh
+./append_ctrlSig.sh
-./create_vectors32.sh
-./create_vectors64_32.sh
-./create_vectors64cmp.sh
-./create_vectors64.sh
-./create_vectorsi.sh
-./create_vectors16fma.sh
-./create_vectors32fma.sh
-./create_vectors64fma.sh
-./create_vectors128fma.sh

tests/fp/sample/Makefile

@@ -1,19 +0,0 @@
-# Makefile
-
-CC     = gcc
-CFLAGS = -O3
-LIBS   = -lm
-LFLAGS = -L. 
-IFLAGS = -I../../../addins/SoftFloat-3e/source/include/
-LIBS   = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a
-SRCS   = $(wildcard *.c)
-
-PROGS = $(patsubst %.c,%,$(SRCS))
-
-all:	$(PROGS)
-
-%: %.c
-	$(CC) $(CFLAGS) $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
-
-clean: 
-	rm -f $(PROGS)

tests/fp/sample/div.c

@@ -1,52 +0,0 @@
-#include <stdio.h>
-#include <stdint.h>
-#include "softfloat.h"
-#include "softfloat_types.h"
-
-int float_rounding_mode = 0;
-
-union dp {
-  unsigned short x[4];
-  double y;
-} X;
-
-
-int main()
-{
-    uint8_t rounding_mode;
-    uint8_t exceptions;
-
-    uint64_t n, d, result;
-    float64_t   d_n, d_d, d_result;
-
-    n = 0x3feffffffefffff6;
-    d = 0xffeffffffffffffe;
-    //n = 0x00000000400001ff;
-    //d = 0x3ffffdfffffffbfe;    
-
-    d_n.v = n;
-    d_d.v = d;
-
-    softfloat_roundingMode = rounding_mode;
-    softfloat_exceptionFlags = 0;
-    softfloat_detectTininess = softfloat_tininess_beforeRounding;
-
-    d_result = f64_div(d_n, d_d);
-
-    //result = d_result.v;    
-    //exceptions = softfloat_exceptionFlags & 0x1f;
-
-    X.x[3] = (d_result.v & 0xffff000000000000) >> 48;
-    X.x[2] = (d_result.v & 0x0000ffff00000000) >> 32;    
-    X.x[1] = (d_result.v & 0x00000000ffff0000) >> 16;
-    X.x[0] = (d_result.v & 0x000000000000ffff);
-
-    printf("Number = %.4x\n", X.x[3]);
-    printf("Number = %.4x\n", X.x[2]);
-    printf("Number = %.4x\n", X.x[1]);
-    printf("Number = %.4x\n", X.x[0]);
-    printf("Number = %1.25lg\n", X.y);    
-    
-
-    return 0;
-}

tests/fp/sample/fma.c

@@ -1,47 +0,0 @@
-#include <stdio.h>
-#include <stdint.h>
-#include "softfloat.h"
-#include "softfloat_types.h"
-
-int float_rounding_mode = 0;
-
-union sp {
-  unsigned short x[2];
-  float y;
-} X;
-
-
-int main()
-{
-    uint8_t rounding_mode;
-    uint8_t exceptions;
-
-    uint32_t multiplier, multiplicand, addend, result;
-    float32_t f_multiplier, f_multiplicand, f_addend, f_result;
-
-    multiplier = 0xbf800000;
-    multiplicand = 0xbf800000;
-    addend = 0xffaaaaaa;
-
-    f_multiplier.v = multiplier;
-    f_multiplicand.v = multiplicand;
-    f_addend.v = addend;
-
-    softfloat_roundingMode = rounding_mode;
-    softfloat_exceptionFlags = 0;
-    softfloat_detectTininess = softfloat_tininess_beforeRounding;
-
-    f_result = f32_mulAdd(f_multiplier, f_multiplicand, f_addend);
-
-    result = f_result.v;    
-    exceptions = softfloat_exceptionFlags & 0x1f;
-
-    printf("%x\n", f_result.v);
-
-    // Print out SP number
-    X.x[1] = (f_result.v & 0xffff0000) >> 16;
-    X.x[0] = (f_result.v & 0x0000ffff);
-    printf("Number = %f\n", X.y);
-
-    return 0;
-}

tests/fp/undy.sh

@@ -1,2 +0,0 @@
-#!/bin/sh
-sed -i 's/ /_/g' $1

tests/testsBP/fpga-test-sdc/copyFlash.c

@@ -27,7 +27,7 @@
 
 void copyFlash(long int blockAddr, long int * Dst, int numBlocks) {
 
-  setSDCCLK(1);
+  setSDCCLK(4); // must be even, 1 gives no division.
   waitInitSDC();
 
   int index;

tests/testsBP/fpga-test-sdc/sdcDriver.c

@@ -62,6 +62,7 @@ volatile void waitInitSDC(){
 }
 
 void setSDCCLK(int divider){
+  divider = (1 - (divider >> 1));
   volatile int * mailBoxCLK;
   mailBoxCLK = (int *) (SDC_MAIL_BOX + 0x0);
   *mailBoxCLK = divider;

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefile

@@ -1,3 +1,5 @@
 include ../../Makefile.include
 
+RVTEST_DEFINES += -march=rv$(XLEN)ia # KMG: removed compressed instructions from privileged tests
+
 $(eval $(call compile_template,-march=rv32iac -mabi=ilp32 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN)))

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output

@@ -0,0 +1,990 @@
+00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
+00000001 # mcause from an instruction access fault
+00000000 # mtval of faulting instruction address (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000002 # mcause from an Illegal instruction
+00000000 # mtval of faulting instruction (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000003 # mcause from Breakpoint
+800003ec # mtval of breakpoint instruction adress (0x800003ec)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000004 # mcause from load address misaligned
+800003f5 # mtval of misaligned address (0x800003f5)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000005 # mcause from load access
+00000000 # mtval of accessed adress (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000006 # mcause from store misaligned
+80000411 # mtval of address with misaligned store instr (0x80000410)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000007 # mcause from store access
+00000000 # mtval of accessed address (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+0000000b # mcause from M mode ecall 
+00000000 # mtval of ecall (*** defined to be zero for now)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000008 # mcause from U mode ecall 
+00000000 # mtval of ecall (*** defined to be zero for now)
+00000080 # masked out mstatus.MPP = 00 (from U mode), mstatus.MPIE = 1, and mstatus.MIE = 0
+00000009 # mcause from S mode ecall 
+00000000 # mtval of ecall (*** defined to be zero for now)
+00000880 # masked out mstatus.MPP = 01 (from S mode), mstatus.MPIE = 1, and mstatus.MIE = 0
+000007ec # value to indicate a vectored interrupts
+80000007 # mcause value from m time interrupt
+00000000 # mtval for mtime interrupt (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+000007ec # value to indicate a vectored interrupts
+80000001 # mcause value from m soft interrupt
+00000000 # mtval for msoft interrupt (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+000007ec # value to indicate a vectored interrupts
+8000000b # mcause value from m ext interrupt
+00000000 # mtval for mext interrupt (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+0000b309 # medeleg after attempted write of all 1's (only some bits are writeable)
+00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
+00000001 # Test 5.3.1.4: mcause from an instruction access fault
+00000000 # mtval of faulting instruction address (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000002 # mcause from an Illegal instruction
+00000000 # mtval of faulting instruction (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000003 # mcause from Breakpoint
+800003ec # mtval of breakpoint instruction adress (0x800003ec)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000004 # mcause from load address misaligned
+800003f5 # mtval of misaligned address (0x800003f5)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000005 # mcause from load access
+00000000 # mtval of accessed adress (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000006 # mcause from store misaligned
+80000411 # mtval of address with misaligned store instr (0x80000410)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000007 # mcause from store access
+00000000 # mtval of accessed address (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+0000000b # mcause from M mode ecall 
+00000000 # mtval of ecall (*** defined to be zero for now)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+000007ec # value to indicate a vectored interrupts
+80000007 # mcause value from  time interrupt
+00000000 # mtval for mtime interrupt (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+000007ec # value to indicate a vectored interrupts
+80000001 # mcause value from m soft interrupt
+00000000 # mtval for msoft interrupt (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+000007ec # value to indicate a vectored interrupts
+0000000b # mcause value from m ext interrupt
+00000000 # mtval for mext interrupt (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+0000000b # mcause from M mode ecall from test termination
+00000000 # mtval of ecall (*** defined to be zero for now)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-s-01.S

@@ -25,7 +25,7 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
 
 # Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode.
 

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-u-01.S

@@ -25,7 +25,7 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
 
 # Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in R mode.
 

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MMU-SV32.S

@@ -25,7 +25,8 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
+
 j test_loop_setup // begin test loop/table tests instead of executing inline code.
 
 INIT_TEST_TABLE

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S

@@ -38,7 +38,8 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
+
 j test_loop_setup // begin test loop/table tests instead of executing inline code.
 
 INIT_TEST_TABLE

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMP.S

@@ -25,7 +25,8 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
+
 j test_loop_setup // begin test loop/table tests instead of executing inline code.
 
 INIT_TEST_TABLE

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h

@@ -52,16 +52,128 @@ RVTEST_CODE_BEGIN
     // address for stack
     la sp, top_of_stack
 
-    // trap handler setup
+.endm
-    la x1, machine_trap_handler
+
-    csrrw x4, mtvec, x1  // x4 reserved for "default" trap handler address that needs to be restored before halting this test.
+// Code to trigger traps goes here so we have consistent mtvals for instruction adresses
+// Even if more tests are added.  
+.macro CAUSE_TRAP_TRIGGERS
+j end_trap_triggers
+
+// The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines
+//      This effectively includes everything that isn't to do with page faults (virtual memory)
+
+cause_instr_addr_misaligned:
+    // cause a misaligned address trap
+    auipc x28, 0      // get current PC, which is aligned
+    addi x28, x28, 0x3  // add 1 to pc to create misaligned address
+    jr x28 // cause instruction address midaligned trap
+    ret
+
+cause_instr_access:
+    la x28, 0x0 // address zero is an address with no memory
+    sw x1, -4(sp) // push the return adress ontot the stack
+    addi sp, sp, -4
+    jalr x28 // cause instruction access trap
+    lw x1, 0(sp) // pop return adress back from the stack
+    addi sp, sp, 4
+    ret
+
+cause_illegal_instr:
+    .word 0x00000000 // a 32 bit zros is an illegal instruction
+    ret
+
+cause_breakpnt: // ****
+    ebreak
+    ret
+
+cause_load_addr_misaligned:
+    auipc x28, 0      // get current PC, which is aligned
+    addi x28, x28, 1
+    lw x29, 0(x28)    // load from a misaligned address
+    ret
+
+cause_load_acc:
+    la x28, 0         // 0 is an address with no memory
+    lw x29, 0(x28)    // load from unimplemented address
+    ret
+
+cause_store_addr_misaligned:
+    auipc x28, 0      // get current PC, which is aligned
+    addi x28, x28, 1
+    sw x29, 0(x28)     // store to a misaligned address
+    ret
+
+cause_store_acc: 
+    la x28, 0         // 0 is an address with no memory
+    sw x29, 0(x28)     // store to unimplemented address
+    ret
+
+cause_ecall:
+    // *** ASSUMES you have already gone to the mode you need to call this from.
+    ecall
+    ret
+
+cause_time_interrupt:
+    // The following code works for both RV32 and RV64.  
+    // RV64 alone would be easier using double-word adds and stores
+    li x28, 0x30          // Desired offset from the present time
+    la x29, 0x02004000    // MTIMECMP register in CLINT
+    la x30, 0x0200BFF8    // MTIME register in CLINT
+    lw x7, 0(x30)         // low word of MTIME
+    lw x31, 4(x30)         // high word of MTIME
+    add x28, x7, x28       // add desired offset to the current time
+    bgtu x28, x7, nowrap  // check new time exceeds current time (no wraparound)
+    addi x31, x31, 1       // if wrap, increment most significant word
+    sw x31,4(x29)          // store into most significant word of MTIMECMP
+nowrap:
+    sw x28, 0(x29)         // store into least significant word of MTIMECMP
+    loop: j loop         // wait until interrupt occurs
+    ret
+
+cause_soft_interrupt:
+    la x28, 0x02000000      // MSIP register in CLINT
+    li x29, 1               // 1 in the lsb
+    sw x29, 0(x28)          // Write MSIP bit
+    ret
+
+cause_ext_interrupt:
+    li x28, 0x10060000 // load base GPIO memory location
+    li x29, 0x1
+    sw x29, 8(x28) // enable the first pin as an output
+    sw x29, 28(x28) // set first pin to high interrupt enable
+    sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt)
+    ret
+
+end_trap_triggers:
+.endm
+
+.macro TRAP_HANDLER MODE, VECTORED=1, DEBUG=0
+    // MODE decides which mode this trap handler will be taken in (M or S mode)
+    // Vectored decides whether interrumpts are handled with the vector table at trap_handler_MODE (1)
+    //      vs Using the non-vector approach the rest of the trap handler takes (0)
+    // DEBUG decides whether we will print mtval a string with status.mpie, status.mie, and status.mpp to the signature (1)
+    //      vs not saving that info to the signature (0)
+
+
+    //   Set up the exception Handler, keeping the original handler in x4.
+    la x1, trap_handler_\MODE\()
+    ori x1, x1, \VECTORED // set mode field of tvec to VECTORED, which will force vectored interrupts if it's 1.
+
+.if (\MODE\() == m)
+    csrrw x4, \MODE\()tvec, x1  // x4 reserved for "default" trap handler address that needs to be restored before halting this test.
+.else
+    csrw \MODE\()tvec, x1 // we only neet save the machine trap handler and this if statement ensures it isn't overwritten
+.endif
+
     li a0, 0
     li a1, 0 
     li a2, 0 // reset trap handler inputs to zero
 
-    // go to beginning of S file where we can decide between using the test data loop
+    la x29, 0x02004000    // MTIMECMP register in CLINT
-    // or using the macro inline code insertion
+    li x30, 0xFFFFFFFF
-    j s_file_begin
+    sw x30, 0(x29) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled
+
+    j trap_handler_end_\MODE\() // skip the trap handler when it is being defined.
 
 	// ---------------------------------------------------------------------------------------------
     // General traps Handler
@@ -96,38 +208,77 @@ RVTEST_CODE_BEGIN
     // --------------------------------------------------------------------------------------------
 
 
-machine_trap_handler:
+.align 2
+trap_handler_\MODE\():
+    j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
+    // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
+    // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
+    // No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
+    j soft_interrupt_\MODE\()    // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
+    j segfault_\MODE\()            // 2: reserved
+    j soft_interrupt_\MODE\()    // 3: breakpoint
+    j segfault_\MODE\()            // 4: reserved
+    j time_interrupt_\MODE\()    // 5: load access fault
+    j segfault_\MODE\()            // 6: reserved
+    j time_interrupt_\MODE\()    // 7: store access fault
+    j segfault_\MODE\()            // 8: reserved
+    j ext_interrupt_\MODE\()     // 9: ecall from S-mode
+    j segfault_\MODE\()            // 10: reserved
+    j ext_interrupt_\MODE\()     // 11: ecall from M-mode
+    // 12 through >=16 are reserved or designated for platform use
+
+trap_unvectored_\MODE\():
     // The processor is always in machine mode when a trap takes us here
     // save registers on stack before using
     sw x1, -4(sp)       
     sw x5, -8(sp)      
 
     // Record trap
-    csrr x1, mcause     // record the mcause
+    csrr x1, \MODE\()cause     // record the mcause
     sw x1, 0(x16)        
     addi x6, x6, 4     
     addi x16, x16, 4    // update pointers for logging results
 
+.if (\DEBUG\() == 1) // record extra information (MTVAL, some status bits) about traps
+    csrr x1, \MODE\()tval
+    sw x1, 0(x16)
+    addi x6, x6, 4     
+    addi x16, x16, 4
+
+    csrr x1, \MODE\()status
+    .if (\MODE\() == m) // Taking traps in different modes means we want to get different bits from the status register.
+        li x5, 0x1888 // mask bits to select MPP, MPIE, and MIE.
+    .else
+        li x5, 0x122 // mask bits to select SPP, SPIE, and SIE.
+    .endif
+    and x5, x5, x1
+    sw x5, 0(x16) // store masked out status bits to the output
+    addi x6, x6, 4
+    addi x16, x16, 4
+
+.endif
+
     // Respond to trap based on cause
     // All interrupts should return after being logged
+    csrr x1, \MODE\()cause
     li x5, 0x8000000000000000   // if msb is set, it is an interrupt
     and x5, x5, x1
-    bnez x5, trapreturn   // return from interrupt
+    bnez x5, trapreturn_\MODE\()   // return from interrupt
     // Other trap handling is specified in the vector Table
     slli x1, x1, 2      // multiply cause by 4 to get offset in vector Table
-    la x5, trap_handler_vector_table
+    la x5, exception_vector_table_\MODE\()
     add x5, x5, x1      // compute address of vector in Table
     lw x5, 0(x5)        // fectch address of handler from vector Table
     jr x5               // and jump to the handler
     
-segfault:
+segfault_\MODE\():
     lw x5, -8(sp)      // restore registers from stack before faulting
     lw x1, -4(sp)       
     j terminate_test          // halt program.
 
-trapreturn:
+trapreturn_\MODE\():
     // look at the instruction to figure out whether to add 2 or 4 bytes to PC, or go to address specified in a1
-    csrr x1, mepc       // get the mepc
+    csrr x1, \MODE\()epc       // get the mepc
     addi x1, x1, 4 // *** should be 2 for compressed instructions, see note.
 
 
@@ -151,13 +302,13 @@ trapreturn:
 //     csrr x1, mepc       // get the mepc again    
 //     addi x1, x1, 4      // add 4 to find the next instruction
 
-trapreturn_specified:
+trapreturn_specified_\MODE\():
     // reset the necessary pointers and registers (x1, x5, x6, and the return address going to mepc)
     // so that when we return to a new virtual address, they're all in the right spot as well.
 
-    beqz a1, trapreturn_finished // either update values, of go to default return address.
+    beqz a1, trapreturn_finished_\MODE\() // either update values, of go to default return address.
 
-    la x5, trap_return_pagetype_table
+    la x5, trap_return_pagetype_table_\MODE\()
     slli a2, a2, 2
     add x5, x5, a2
     lw a2, 0(x5) // a2 = number of offset bits in current page type
@@ -189,54 +340,93 @@ trapreturn_specified:
     li a1, 0 
     li a2, 0 // reset trapreturn inputs to the trap handler
 
-trapreturn_finished:
+trapreturn_finished_\MODE\():
-    csrw mepc, x1   // update the mepc with address of next instruction
+    csrw \MODE\()epc, x1   // update the mepc with address of next instruction
     lw x5, -8(sp)   // restore registers from stack before returning
     lw x1, -4(sp)
-    mret  // return from trap
+    \MODE\()ret  // return from trap
 
-ecallhandler:
+ecallhandler_\MODE\():
     // Check input parameter a0. encoding above. 
     // *** ASSUMES: that this trap is being handled in machine mode. in other words, that nothing odd has been written to the medeleg or mideleg csrs.
     li x5, 2            // case 2: change to machine mode
-    beq a0, x5, ecallhandler_changetomachinemode
+    beq a0, x5, ecallhandler_changetomachinemode_\MODE\()
     li x5, 3            // case 3: change to supervisor mode
-    beq a0, x5, ecallhandler_changetosupervisormode
+    beq a0, x5, ecallhandler_changetosupervisormode_\MODE\()
     li x5, 4            // case 4: change to user mode
-    beq a0, x5, ecallhandler_changetousermode
+    beq a0, x5, ecallhandler_changetousermode_\MODE\()
     // unsupported ecalls should segfault
-    j segfault
+    j segfault_\MODE\()
 
-ecallhandler_changetomachinemode:
+ecallhandler_changetomachinemode_\MODE\():
     // Force mstatus.MPP (bits 12:11) to 11 to enter machine mode after mret
     li x1, 0b1100000000000
-    csrs mstatus, x1
+    csrs \MODE\()status, x1
-    j trapreturn        
+    j trapreturn_\MODE\()       
 
-ecallhandler_changetosupervisormode:
+ecallhandler_changetosupervisormode_\MODE\():
     // Force mstatus.MPP (bits 12:11) to 01 to enter supervisor mode after mret
     li x1, 0b1100000000000  
-    csrc mstatus, x1
+    csrc \MODE\()status, x1
     li x1, 0b0100000000000
-    csrs mstatus, x1
+    csrs \MODE\()status, x1
-    j trapreturn
+    j trapreturn_\MODE\()
 
-ecallhandler_changetousermode:
+ecallhandler_changetousermode_\MODE\():
     // Force mstatus.MPP (bits 12:11) to 00 to enter user mode after mret
     li x1, 0b1100000000000  
-    csrc mstatus, x1
+    csrc \MODE\()status, x1
-    j trapreturn
+    j trapreturn_\MODE\()
 
-instrfault:
+instrpagefault_\MODE\():
     lw x1, -4(sp) // load return address int x1 (the address AFTER the jal into faulting page)
-    j trapreturn_finished // puts x1 into mepc, restores stack and returns to program (outside of faulting page)
+    j trapreturn_finished_\MODE\() // puts x1 into mepc, restores stack and returns to program (outside of faulting page)
 
-illegalinstr:
+instrfault_\MODE\():
-    j trapreturn // return to the code after recording the mcause
+    lw x1, -4(sp) // load return address int x1 (the address AFTER the jal to the faulting address)
+    j trapreturn_finished_\MODE\() // return to the code after recording the mcause
 
-accessfault:
+illegalinstr_\MODE\():
+    j trapreturn_\MODE\() // return to the code after recording the mcause
+
+accessfault_\MODE\():
     // *** What do I have to do here?
-    j trapreturn
+    j trapreturn_\MODE\()
+
+addr_misaligned_\MODE\():
+    j trapreturn_\MODE\()
+
+breakpt_\MODE\():
+    j trapreturn_\MODE\()
+
+soft_interrupt_\MODE\():
+    li x5, 0x7EC // write 0x7EC (looks like VEC) to the output before the mcause and extras to indicate that this trap was handled with a vector table. 
+    sw x5, 0(x16)
+    addi x6, x6, 4
+    addi x16, x16, 4
+    la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
+    sw x0, 0(x28)
+    j trap_unvectored_\MODE\()
+
+time_interrupt_\MODE\():
+    li x5, 0x7EC
+    sw x5, 0(x16)
+    addi x6, x6, 4
+    addi x16, x16, 4
+    la x29, 0x02004000    // MTIMECMP register in CLINT
+    li x30, 0xFFFFFFFF
+    sw x30, 0(x29) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
+    j trap_unvectored_\MODE\()
+
+ext_interrupt_\MODE\():
+    li x5, 0x7EC
+    sw x5, 0(x16)
+    addi x6, x6, 4
+    addi x16, x16, 4
+    li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits
+    sw x0, 8(x28) // disable the first pin as an output
+    sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
+    j trap_unvectored_\MODE\()
 
     // Table of trap behavior
     // lists what to do on each exception (not interrupts)
@@ -244,29 +434,30 @@ accessfault:
     // Expected exceptions should increment the EPC to the next instruction and return
 
     .align 2 // aligns this data table to an 4 byte boundary
-trap_handler_vector_table:
+exception_vector_table_\MODE\():
-    .4byte segfault      // 0: instruction address misaligned
+    .4byte addr_misaligned_\MODE\()      // 0: instruction address misaligned
-    .4byte instrfault    // 1: instruction access fault
+    .4byte instrfault_\MODE\()    // 1: instruction access fault
-    .4byte illegalinstr  // 2: illegal instruction
+    .4byte illegalinstr_\MODE\()  // 2: illegal instruction
-    .4byte segfault      // 3: breakpoint
+    .4byte breakpt_\MODE\()      // 3: breakpoint
-    .4byte segfault      // 4: load address misaligned
+    .4byte addr_misaligned_\MODE\()      // 4: load address misaligned
-    .4byte accessfault   // 5: load access fault
+    .4byte accessfault_\MODE\()   // 5: load access fault
-    .4byte segfault      // 6: store address misaligned
+    .4byte addr_misaligned_\MODE\()      // 6: store address misaligned
-    .4byte accessfault   // 7: store access fault
+    .4byte accessfault_\MODE\()   // 7: store access fault
-    .4byte ecallhandler  // 8: ecall from U-mode
+    .4byte ecallhandler_\MODE\()  // 8: ecall from U-mode
-    .4byte ecallhandler  // 9: ecall from S-mode
+    .4byte ecallhandler_\MODE\()  // 9: ecall from S-mode
-    .4byte segfault      // 10: reserved
+    .4byte segfault_\MODE\()      // 10: reserved
-    .4byte ecallhandler  // 11: ecall from M-mode
+    .4byte ecallhandler_\MODE\()  // 11: ecall from M-mode
-    .4byte instrfault    // 12: instruction page fault
+    .4byte instrpagefault_\MODE\()    // 12: instruction page fault
-    .4byte trapreturn    // 13: load page fault
+    .4byte trapreturn_\MODE\()    // 13: load page fault
-    .4byte segfault      // 14: reserved
+    .4byte segfault_\MODE\()      // 14: reserved
-    .4byte trapreturn    // 15: store page fault
+    .4byte trapreturn_\MODE\()    // 15: store page fault
 
 .align 2
-trap_return_pagetype_table:
+trap_return_pagetype_table_\MODE\():
     .4byte 0xC  // 0: kilopage has 12 offset bits
     .4byte 0x16 // 1: megapage has 22 offset bits
 
+trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler and continue with the test
 .endm
 
 // Test Summary table!
@@ -367,7 +558,7 @@ trap_return_pagetype_table:
 // they generally do not fault or cause issues as long as these modes are enabled 
 // *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not?
 
-.macro GOTO_M_MODE RETURN_VPN RETURN_PAGETYPE
+.macro GOTO_M_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
     li a0, 2 // determine trap handler behavior (go to machine mode)
     li a1, \RETURN_VPN // return VPN
     li a2, \RETURN_PAGETYPE // return page types
@@ -375,7 +566,7 @@ trap_return_pagetype_table:
     // now in S mode
 .endm
 
-.macro GOTO_S_MODE RETURN_VPN RETURN_PAGETYPE
+.macro GOTO_S_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
     li a0, 3 // determine trap handler behavior (go to supervisor mode)
     li a1, \RETURN_VPN // return VPN
     li a2, \RETURN_PAGETYPE // return page types
@@ -383,7 +574,7 @@ trap_return_pagetype_table:
     // now in S mode
 .endm
 
-.macro GOTO_U_MODE RETURN_VPN RETURN_PAGETYPE
+.macro GOTO_U_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
     li a0, 4 // determine trap handler behavior (go to user mode)
     li a1, \RETURN_VPN // return VPN
     li a2, \RETURN_PAGETYPE // return page types

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S

@@ -25,7 +25,7 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
 
 // Test 5.2.3.1: testing Read-only access to Machine info CSRs 
 CSR_R_ACCESS mvendorid

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S

@@ -25,7 +25,7 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
 // Test 5.3.2.2: Machine ISA register test
 
 // Misa is a specific case *** so I don't want to add a whole test case for reading nonzero but unkown value CSRs.

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S

@@ -0,0 +1,45 @@
+///////////////////////////////////////////
+//
+// WALLY-unvectored-interrupt
+//
+// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+//
+// Created 2022-03-11
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "WALLY-TEST-LIB-64.h"
+
+INIT_TESTS
+
+// test 5.3.1.5 Unvectored interrupt tests 
+
+TRAP_HANDLER m, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
+
+li x28, 0x8
+csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
+WRITE_READ_CSR mie, 0xFFF // *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
+
+// cause traps, ensuring that we DONT go through the vectored part of the trap handler
+// *** this assumes that interrupt code 0 remains reserved
+
+CAUSE_TIME_INTERRUPT // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+CAUSE_SOFT_INTERRUPT // *** exiting out of the trap handler after these is current;y broken
+CAUSE_EXT_INTERRUPT
+
+END_TESTS
+
+TEST_STACK_AND_DATA

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-scratch-01.S

@@ -25,7 +25,8 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
+
 // Test 5.3.2.3: Scratch registers test
 
 WRITE_READ_CSR mscratch, 0x111 // check that mscratch is readable and writeable in machine mode

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sscratch-s-01.S

@@ -25,7 +25,7 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
 
 // Test 5.3.2.3: Scratch registers test
 WRITE_READ_CSR sscratch, 0x111 // check that sscratch is readable and writeable in machine mode

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S

@@ -0,0 +1,55 @@
+///////////////////////////////////////////
+//
+// WALLY-unvectored-interrupt
+//
+// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+//
+// Created 2022-03-11
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "WALLY-TEST-LIB-64.h"
+
+INIT_TESTS
+
+// test 5.3.1.5 Unvectored interrupt tests 
+
+TRAP_HANDLER s, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
+
+// li x28, 0x8
+// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
+// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
+
+WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
+
+GOTO_S_MODE
+
+// cause traps, ensuring that we DONT go through the vectored part of the trap handler
+// *** this assumes that interrupt code 0 remains reserved
+
+// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
+// CAUSE_EXT_INTERRUPT
+
+GOTO_U_MODE 
+
+// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
+// CAUSE_EXT_INTERRUPT
+
+END_TESTS
+
+TEST_STACK_AND_DATA

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S

@@ -0,0 +1,76 @@
+///////////////////////////////////////////
+//
+// WALLY-trap
+//
+// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+//
+// Created 2022-02-20
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "WALLY-TEST-LIB-64.h"
+
+INIT_TESTS
+
+CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
+
+TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+
+li x28, 0x8
+csrs mstatus, x28 // set mstatus.MIE bit to 1
+WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
+
+// test 5.3.1.4 Basic trap tests 
+
+// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled)
+jal cause_instr_access
+jal cause_illegal_instr
+jal cause_breakpnt
+jal cause_load_addr_misaligned
+jal cause_load_acc
+jal cause_store_addr_misaligned
+jal cause_store_acc
+GOTO_U_MODE // Causes M mode ecall
+GOTO_S_MODE // Causes U mode ecall
+GOTO_M_MODE // Causes S mode ecall
+
+jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken
+jal cause_ext_interrupt
+
+// try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode
+
+WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
+WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
+
+// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled)
+jal cause_instr_access
+jal cause_illegal_instr
+jal cause_breakpnt
+jal cause_load_addr_misaligned
+jal cause_load_acc
+jal cause_store_addr_misaligned
+jal cause_store_acc
+jal cause_ecall // M mode ecall
+
+jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken
+jal cause_ext_interrupt
+
+END_TESTS
+
+TEST_STACK_AND_DATA
+

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S

@@ -0,0 +1,85 @@
+///////////////////////////////////////////
+//
+// WALLY-trap-s
+//
+// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+//
+// Created 2022-03-11
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "WALLY-TEST-LIB-64.h"
+
+INIT_TESTS
+
+// test 5.3.1.4 Basic trap tests 
+
+TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
+
+// Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg
+
+GOTO_S_MODE
+
+li x28, 0x8
+csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
+// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
+
+
+// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
+CAUSE_INSTR_ACCESS
+CAUSE_ILLEGAL_INSTR
+CAUSE_BREAKPNT
+CAUSE_LOAD_ADDR_MISALIGNED
+CAUSE_LOAD_ACC
+CAUSE_STORE_ADDR_MISALIGNED
+CAUSE_STORE_ACC
+CAUSE_ECALL
+
+// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
+// CAUSE_EXT_INTERRUPT
+
+
+// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
+// We can tell which one becuase the different trap handler modes write different bits of the status register 
+// to the output when debug is on.
+
+GOTO_M_MODE // so we can write the delegate registers
+
+WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
+WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
+
+GOTO_S_MODE
+
+// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
+CAUSE_INSTR_ACCESS
+CAUSE_ILLEGAL_INSTR
+CAUSE_BREAKPNT
+CAUSE_LOAD_ADDR_MISALIGNED
+CAUSE_LOAD_ACC
+CAUSE_STORE_ADDR_MISALIGNED
+CAUSE_STORE_ACC
+CAUSE_ECALL
+
+// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
+// CAUSE_EXT_INTERRUPT
+
+END_TESTS
+
+TEST_STACK_AND_DATA
+

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S

@@ -0,0 +1,84 @@
+///////////////////////////////////////////
+//
+// WALLY-trap-u
+//
+// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+//
+// Created 2022-03-11
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "WALLY-TEST-LIB-64.h"
+
+INIT_TESTS
+
+// test 5.3.1.4 Basic trap tests 
+
+TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
+
+// Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg
+
+GOTO_U_MODE
+
+// li x28, 0x8
+// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
+// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
+
+
+// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
+CAUSE_INSTR_ACCESS
+CAUSE_ILLEGAL_INSTR
+CAUSE_BREAKPNT
+CAUSE_LOAD_ADDR_MISALIGNED
+CAUSE_LOAD_ACC
+CAUSE_STORE_ADDR_MISALIGNED
+CAUSE_STORE_ACC
+CAUSE_ECALL
+
+// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
+// CAUSE_EXT_INTERRUPT
+
+
+// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
+// We can tell which one becuase the different trap handler modes write different bits of the status register 
+// to the output when debug is on.
+
+GOTO_M_MODE // so we can write the delegate registers
+
+WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
+WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
+
+GOTO_U_MODE
+
+// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
+CAUSE_INSTR_ACCESS
+CAUSE_ILLEGAL_INSTR
+CAUSE_BREAKPNT
+CAUSE_LOAD_ADDR_MISALIGNED
+CAUSE_LOAD_ACC
+CAUSE_STORE_ADDR_MISALIGNED
+CAUSE_STORE_ACC
+CAUSE_ECALL
+
+// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
+// CAUSE_EXT_INTERRUPT
+
+END_TESTS
+
+TEST_STACK_AND_DATA

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output

@@ -1,23 +1,11 @@
 beef00b4 # Test 12.3.2.1: read 64 bits success in CLINT 
-0000dead # all of these read successes are also confirming successful writes
+0000dead # all of these read successes are also confirming successful writes 
-00000007 # write 32 bits with access fault in CLINT
+beef00b5 # read 32 bits success in CLINT (bottom 32 bits sign extended)
-00000000
+ffffffff
-00000005 # read 32 bits with access fault in CLINT
+000000b6 # read 16 bits success in CLINT (bottom 16 bits sign extended)
-00000000
-00000bad
-00000000
-00000007 # write 16 bits with access fault in CLINT
-00000000
-00000005 # read 16 bits with access fault in CLINT
-00000000
-00000bad
-00000000
-00000007 # write 8 bits with access fault in CLINT
-00000000
-00000005 # read 8 bits with access fault in CLINT
-00000000
-00000bad
 00000000
+ffffffb7 # read 8 bits success in CLINT (bottom 8 bits sign extended)
+ffffffff
 00000001 # execute test with access fault in CLINT
 00000000
 00000bad

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S

@@ -85,12 +85,12 @@ test_cases:
 # Use timecmp register as readable and writable section of the CLINT
 .8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B4, write64_test  # 64-bit write:  success
 .8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B4, read64_test # 64-bit read:   success
-.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B5, write32_test # 32-bit write:  failure *** due to non-native length access
+.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B5, write32_test # 32-bit write: success
-.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B5, read32_test # 32-bit read:   failure
+.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B5, read32_test # 32-bit read:   success
-.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B6, write16_test # 16-bit write:  failure
+.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B6, write16_test # 16-bit write: success
-.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B6, read16_test # 16-bit read:   failure
+.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B6, read16_test # 16-bit read:   success
-.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B7, write08_test # 08-bit write:  failure
+.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B7, write08_test # 08-bit write: success
-.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B7, read08_test # 08-bit read:   failure
+.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B7, read08_test # 08-bit read:   success
 
 .8byte CLINT_BASE, 0xbad, executable_test# execute: instruction access fault
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h

@@ -41,7 +41,7 @@ RVTEST_CODE_BEGIN
     //   
     //   Initialize x6 as a virtual pointer to the test results
     //   Initialize x16 as a physical pointer to the test results
-    //   Set up stack pointer (sp = x2)
+    //   Set up stack pointer, mscratch, sscratch
     //   
 	// ---------------------------------------------------------------------------------------------
 
@@ -50,8 +50,12 @@ RVTEST_CODE_BEGIN
     la x16, test_1_res // x16 reserved for the physical address equivalent of x6 to be used in trap handlers
                         // any time either is used, both must be updated.
 
-    // address for stack
+    // address for normal user stack, mscratch stack, and sscratch stack
-    la sp, top_of_stack
+    la sp, mscratch_top
+    csrw mscratch, sp
+    la sp, sscratch_top
+    csrw sscratch, sp
+    la sp, stack_top
 
 .endm
 
@@ -72,7 +76,7 @@ cause_instr_addr_misaligned:
 
 cause_instr_access:
     la x28, 0x0 // address zero is an address with no memory
-    sd x1, -8(sp) // push the return adress ontot the stack
+    sd x1, -8(sp) // push the return adress onto the stack
     addi sp, sp, -8
     jalr x28 // cause instruction access trap
     ld x1, 0(sp) // pop return adress back from the stack
@@ -83,7 +87,7 @@ cause_illegal_instr:
     .word 0x00000000 // a 32 bit zros is an illegal instruction
     ret
 
-cause_breakpnt: // ****
+cause_breakpnt:
     ebreak
     ret
 
@@ -117,7 +121,7 @@ cause_ecall:
 cause_time_interrupt:
     // The following code works for both RV32 and RV64.  
     // RV64 alone would be easier using double-word adds and stores
-    li x28, 0x100          // Desired offset from the present time
+    li x28, 0x30          // Desired offset from the present time
     la x29, 0x02004000    // MTIMECMP register in CLINT
     la x30, 0x0200BFF8    // MTIME register in CLINT
     lw x7, 0(x30)         // low word of MTIME
@@ -128,7 +132,9 @@ cause_time_interrupt:
     sw x31,4(x29)          // store into most significant word of MTIMECMP
 nowrap:
     sw x28, 0(x29)         // store into least significant word of MTIMECMP
-    loop: j loop         // wait until interrupt occurs
+loop:
+    wfi 
+    j loop         // wait until interrupt occurs
     ret
 
 cause_soft_interrupt:
@@ -150,7 +156,7 @@ end_trap_triggers:
 
 .macro TRAP_HANDLER MODE, VECTORED=1, DEBUG=0
     // MODE decides which mode this trap handler will be taken in (M or S mode)
-    // Vectored decides whether interrumpts are handled with the vector table at trap_handler_MODE (1)
+    // Vectored decides whether interrupts are handled with the vector table at trap_handler_MODE (1)
     //      vs Using the non-vector approach the rest of the trap handler takes (0)
     // DEBUG decides whether we will print mtval a string with status.mpie, status.mie, and status.mpp to the signature (1)
     //      vs not saving that info to the signature (0)
@@ -158,9 +164,7 @@ end_trap_triggers:
 
     //   Set up the exception Handler, keeping the original handler in x4.
     la x1, trap_handler_\MODE\()
-.if (\VECTORED\() == 1)
+    ori x1, x1, \VECTORED // set mode field of tvec to VECTORED, which will force vectored interrupts if it's 1.
-    ori x1, x1, 0x1 // set mode field of tvec to 1, forcing vectored interrupts
-.endif
 
 .if (\MODE\() == m)
     csrrw x4, \MODE\()tvec, x1  // x4 reserved for "default" trap handler address that needs to be restored before halting this test.
@@ -172,6 +176,10 @@ end_trap_triggers:
     li a1, 0 
     li a2, 0 // reset trap handler inputs to zero
 
+    la x29, 0x02004000    // MTIMECMP register in CLINT
+    li x30, 0xFFFFFFFF
+    sd x30, 0(x29) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled
+
     j trap_handler_end_\MODE\() // skip the trap handler when it is being defined.
 
 	// ---------------------------------------------------------------------------------------------
@@ -214,23 +222,28 @@ trap_handler_\MODE\():
     // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
     // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
     // No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
-    j s_soft_interrupt_\MODE\()    // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
+    j s_soft_vector_\MODE\()    // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
     j segfault_\MODE\()            // 2: reserved
-    j m_soft_interrupt_\MODE\()    // 3: breakpoint
+    j m_soft_vector_\MODE\()    // 3: breakpoint
     j segfault_\MODE\()            // 4: reserved
-    j s_time_interrupt_\MODE\()    // 5: load access fault
+    j s_time_vector_\MODE\()    // 5: load access fault
     j segfault_\MODE\()            // 6: reserved
-    j m_time_interrupt_\MODE\()    // 7: store access fault
+    j m_time_vector_\MODE\()    // 7: store access fault
     j segfault_\MODE\()            // 8: reserved
-    j s_ext_interrupt_\MODE\()     // 9: ecall from S-mode
+    j s_ext_vector_\MODE\()     // 9: ecall from S-mode
     j segfault_\MODE\()            // 10: reserved
-    j m_ext_interrupt_\MODE\()     // 11: ecall from M-mode
+    j m_ext_vector_\MODE\()     // 11: ecall from M-mode
     // 12 through >=16 are reserved or designated for platform use
 
 trap_unvectored_\MODE\():
+    csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
+    // *** NOTE: this means that nested traps will be screwed up but they shouldn't happen in any of these tests
+
+trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since we already switch sp and scratch there
     // save registers on stack before using
     sd x1, -8(sp)       
-    sd x5, -16(sp)      
+    sd x5, -16(sp)
+    sd x7, -24(sp) 
 
     // Record trap
     csrr x1, \MODE\()cause     // record the mcause
@@ -245,12 +258,11 @@ trap_unvectored_\MODE\():
     addi x16, x16, 8
 
     csrr x1, \MODE\()status
-.if (\MODE\() == m) // Taking traps in different modes means we want to get different bits from the status register.
+    .if (\MODE\() == m) // Taking traps in different modes means we want to get different bits from the status register.
-    li x5, 0x1888 // mask bits to select MPP, MPIE, and MIE.
+        li x5, 0x1888 // mask bits to select MPP, MPIE, and MIE.
-.else
+    .else
-    li x5, 0x122 // mask bits to select SPP, SPIE, and SIE.
+        li x5, 0x122 // mask bits to select SPP, SPIE, and SIE.
-.endif
+    .endif
-
     and x5, x5, x1
     sd x5, 0(x16) // store masked out status bits to the output
     addi x6, x6, 8
@@ -261,50 +273,35 @@ trap_unvectored_\MODE\():
     // Respond to trap based on cause
     // All interrupts should return after being logged
     csrr x1, \MODE\()cause
+    slli x1, x1, 3          // multiply cause by 8 to get offset in vector Table
     li x5, 0x8000000000000000   // if msb is set, it is an interrupt
     and x5, x5, x1
-    bnez x5, trapreturn_\MODE\()   // return from interrupt
+    bnez x5, interrupt_handler_\MODE\()  // return from interrupt
     // Other trap handling is specified in the vector Table
-    csrr x1, \MODE\()cause
-    slli x1, x1, 3      // multiply cause by 8 to get offset in vector Table
     la x5, exception_vector_table_\MODE\()
     add x5, x5, x1      // compute address of vector in Table
     ld x5, 0(x5)        // fectch address of handler from vector Table
     jr x5               // and jump to the handler
-    
+
+interrupt_handler_\MODE\():
+    la x5, interrupt_vector_table_\MODE\() // NOTE THIS IS NOT THE SAME AS VECTORED INTERRUPTS!!!
+    add x5, x5, x1      // compute address of vector in Table
+    ld x5, 0(x5)        // fectch address of handler from vector Table
+    jr x5               // and jump to the handler
+
 segfault_\MODE\():
-    ld x5, -16(sp)      // restore registers from stack before faulting
+    sd x7, -24(sp)  // restore registers from stack before faulting 
+    ld x5, -16(sp)
     ld x1, -8(sp)       
     j terminate_test          // halt program.
 
 trapreturn_\MODE\():
-    // look at the instruction to figure out whether to add 2 or 4 bytes to PC, or go to address specified in a1
+    csrr x1, \MODE\()epc
-    csrr x1, \MODE\()epc       // get the mepc
+    addi x1, x1, 4 // return to the address AFTER the trapping instruction
-    addi x1, x1, 4 // *** should be 2 for compressed instructions, see note.
-
-
-// ****** KMG: the following is no longer as easy to determine. mepc gets the virtual address of the trapped instruction, 
-// ********     but in the handler, we work in M mode with physical addresses
-//              This means the address in mepc is suddenly pointing somewhere else.
-//              to get this to work, We could either retranslate the vaddr back into a paddr (probably on the scale of difficult to intractible)
-//              or we could come up with some other ingenious way to stay in M mode and see if the instruction was compressed.
-
-//     lw x5, 0(x1)        // read the faulting instruction
-//     li x1, 3            // check bottom 2 bits of instruction to see if compressed
-//     and x5, x5, x1      // mask the other bits
-//     beq x5, x1, trapreturn_uncompressed_\MODE\()  // if 11, the instruction is return_uncompressed
-
-// trapreturn_compressed_\MODE\():
-//     csrr x1, mepc       // get the mepc again
-//     addi x1, x1, 2      // add 2 to find the next instruction
-//     j trapreturn_specified_\MODE\() // and return
-
-// trapreturn_uncompressed_\MODE\():
-//      csrr x1, mepc       // get the mepc again    
-//      addi x1, x1, 4      // add 4 to find the next instruction
 
 trapreturn_specified_\MODE\():
     // reset the necessary pointers and registers (x1, x5, x6, and the return address going to mepc)
+    // note that we don't need to change x7 since it was a temporary register with no important address in it.
     // so that when we return to a new virtual address, they're all in the right spot as well.
 
     beqz a1, trapreturn_finished_\MODE\() // either update values, of go to default return address.
@@ -318,13 +315,13 @@ trapreturn_specified_\MODE\():
     sll x5, x5, a2
     addi x5, x5, -1 // x5 = mask bits for offset into current pagetype
 
-    // reset the top of the stack, x1
+    // reset the top of the stack, which will be put into ra
     ld x7, -8(sp) 
     and x7, x5, x7 // x7 = offset for x1
     add x7, x7, a1 // x7 = new address for x1
     sd x7, -8(sp)
 
-    // reset the second spot in the stack, x5
+    // reset the second spot in the stack, which will be put into x5
     ld x7, -16(sp)
     and x7, x5, x7 // x7 = offset for x5
     add x7, x7, a1 // x7 = new address for x5
@@ -334,7 +331,7 @@ trapreturn_specified_\MODE\():
     and x7, x5, x6 // x7 = offset for x6
     add x6, x7, a1 // x6 = new address for the result pointer
     
-    // set return address, stored temporarily in x1, to the next instruction, but in the new virtual page.
+    // reset x1, which temporarily holds the return address that will be written to mepc.
     and x1, x5, x1 // x1 = offset for the return address
     add x1, x1, a1 // x1 = new return address.
 
@@ -342,10 +339,10 @@ trapreturn_specified_\MODE\():
     li a2, 0 // reset trapreturn inputs to the trap handler
 
 trapreturn_finished_\MODE\():
-    csrw \MODE\()epc, x1       // update the epc with address of next instruction
+    csrw \MODE\()epc, x1            // update the epc with address of next instruction
-    ld x5, -16(sp)      // restore registers from stack before returning
+    ld x7, -24(sp)     // restore registers from stack before returning
+    ld x5, -16(sp)
     ld x1, -8(sp)
-    csrw \MODE\()ip, 0x0 // clear interrupt pending register to indicate interrupt has been handled
     \MODE\()ret  // return from trap
 
 ecallhandler_\MODE\():
@@ -376,22 +373,21 @@ ecallhandler_changetosupervisormode_\MODE\():
 ecallhandler_changetousermode_\MODE\():
     // Force mstatus.MPP (bits 12:11) to 00 to enter user mode after mret
     li x1, 0b1100000000000  
-    csrc mstatus, x1
+    csrc \MODE\()status, x1
     j trapreturn_\MODE\()
 
 instrpagefault_\MODE\():
-    ld x1, -8(sp) // load return address int x1 (the address AFTER the jal to the faulting address)
+    ld x1, -8(sp) // load return address from stack into ra (the address AFTER the jal to the faulting address)
     j trapreturn_finished_\MODE\() // puts x1 into mepc, restores stack and returns to program (outside of faulting page)
 
 instrfault_\MODE\():
-    ld x1, -8(sp) // load return address int x1 (the address AFTER the jal to the faulting address)
+    ld x1, -8(sp) // load return address from stack into ra (the address AFTER the jal to the faulting address)
-    j trapreturn_finished_\MODE\() // return to the code after recording the mcause
+    j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
 
 illegalinstr_\MODE\():
     j trapreturn_\MODE\() // return to the code after recording the mcause
 
 accessfault_\MODE\():
-    // *** What do I have to do here?
     j trapreturn_\MODE\()
 
 addr_misaligned_\MODE\():
@@ -400,58 +396,67 @@ addr_misaligned_\MODE\():
 breakpt_\MODE\():
     j trapreturn_\MODE\()
 
-s_soft_interrupt_\MODE\(): // these labels are here to make sure the code compiles, but don't actually do anything yet
+s_soft_vector_\MODE\():
-    li x5, 0x7EC // write 0x7EC (looks like VEC) to the output before the mcause and extras to indicate that this trap was handled with a vector table. 
+    csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
-    sd x5, 0(x16)
+    sd x5, -8(sp) // put x5 on the scratch stack before messing with it
+    li x5, 0x7EC01 // write 0x7ec01 (for "VEC"tored and 01 for the interrupt code)
+    j vectored_int_end_\MODE\()
+
+m_soft_vector_\MODE\():
+    csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
+    sd x5, -8(sp) // put x5 on the scratch stack before messing with it
+    li x5, 0x7EC03 // write 0x7ec03 (for "VEC"tored and 03 for the interrupt code)
+    j vectored_int_end_\MODE\()
+
+s_time_vector_\MODE\():
+    csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
+    sd x5, -8(sp) // put x5 on the scratch stack before messing with it
+    li x5, 0x7EC05 // write 0x7ec05 (for "VEC"tored and 05 for the interrupt code)
+    j vectored_int_end_\MODE\()
+
+m_time_vector_\MODE\():
+    csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
+    sd x5, -8(sp) // put x5 on the scratch stack before messing with it
+    li x5, 0x7EC07 // write 0x7ec07 (for "VEC"tored and 07 for the interrupt code)
+    j vectored_int_end_\MODE\()
+
+s_ext_vector_\MODE\():
+    csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
+    sd x5, -8(sp) // put x5 on the scratch stack before messing with it
+    li x5, 0x7EC09 // write 0x7ec09 (for "VEC"tored and 08 for the interrupt code)
+    j vectored_int_end_\MODE\()
+
+m_ext_vector_\MODE\():
+    csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
+    sd x5, -8(sp) // put x5 on the scratch stack before messing with it
+    li x5, 0x7EC0B // write 0x7ec0B (for "VEC"tored and 0B for the interrupt code)
+    j vectored_int_end_\MODE\()
+
+vectored_int_end_\MODE\():
+    sd x5, 0(x16) // store to signature to show vectored interrupts succeeded. 
     addi x6, x6, 8
     addi x16, x16, 8
+    ld x5, -8(sp) // restore x5 before continuing to handle trap in case its needed.
+    j trap_stack_saved_\MODE\()
+
+soft_interrupt_\MODE\():
     la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
     sw x0, 0(x28)
-    j trap_unvectored_\MODE\()
+    j trapreturn_\MODE\()
 
-m_soft_interrupt_\MODE\():
+time_interrupt_\MODE\():
-    li x5, 0x7EC
+    la x29, 0x02004000    // MTIMECMP register in CLINT
-    sd x5, 0(x16)
+    li x30, 0xFFFFFFFF
-    addi x6, x6, 8
+    sd x30, 0(x29) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
-    addi x16, x16, 8
+    
-    la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
+    ld x1, -8(sp) // load return address from stack into ra (the address AFTER the jal to the faulting address)
-    sw x0, 0(x28)
+    j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
-    j trap_unvectored_\MODE\()
 
-s_time_interrupt_\MODE\():
+ext_interrupt_\MODE\():
-    li x5, 0x7EC
-    sd x5, 0(x16)
-    addi x6, x6, 8
-    addi x16, x16, 8
-    j trap_unvectored_\MODE\()
-
-m_time_interrupt_\MODE\():
-    li x5, 0x7EC
-    sd x5, 0(x16)
-    addi x6, x6, 8
-    addi x16, x16, 8
-    j trap_unvectored_\MODE\()
-
-s_ext_interrupt_\MODE\():
-    li x5, 0x7EC
-    sd x5, 0(x16)
-    addi x6, x6, 8
-    addi x16, x16, 8
     li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits
     sw x0, 8(x28) // disable the first pin as an output
     sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
-    j trap_unvectored_\MODE\()
+    j trapreturn_\MODE\()
-
-m_ext_interrupt_\MODE\():
-    li x5, 0x7EC
-    sd x5, 0(x16)
-    addi x6, x6, 8
-    addi x16, x16, 8
-    li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits
-    sw x0, 8(x28) // disable the first pin as an output
-    sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
-    j trap_unvectored_\MODE\()
-
 
     // Table of trap behavior
     // lists what to do on each exception (not interrupts)
@@ -477,6 +482,21 @@ exception_vector_table_\MODE\():
     .8byte segfault_\MODE\()      // 14: reserved
     .8byte trapreturn_\MODE\()    // 15: store page fault
 
+    .align 3 // aligns this data table to an 8 byte boundary
+interrupt_vector_table_\MODE\():
+    .8byte segfault_\MODE\()            // 0: reserved
+    .8byte s_soft_vector_\MODE\()    // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
+    .8byte segfault_\MODE\()            // 2: reserved
+    .8byte m_soft_vector_\MODE\()    // 3: breakpoint
+    .8byte segfault_\MODE\()            // 4: reserved
+    .8byte s_time_vector_\MODE\()    // 5: load access fault
+    .8byte segfault_\MODE\()            // 6: reserved
+    .8byte m_time_vector_\MODE\()    // 7: store access fault
+    .8byte segfault_\MODE\()            // 8: reserved
+    .8byte s_ext_vector_\MODE\()     // 9: ecall from S-mode
+    .8byte segfault_\MODE\()            // 10: reserved
+    .8byte m_ext_vector_\MODE\()     // 11: ecall from M-mode
+
 .align 3
 trap_return_pagetype_table_\MODE\():
     .8byte 0xC  // 0: kilopage has 12 offset bits
@@ -720,87 +740,6 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
     addi x16, x16, 8 
 .endm
 
-// // The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines
-// //      This effectively includes everything that isn't to do with page faults (virtual memory)
-
-// .macro CAUSE_INSTR_ADDR_MISALIGNED
-//     // cause a misaligned address trap
-//     auipc x28, 0      // get current PC, which is aligned
-//     addi x28, x28, 0x1  // add 1 to pc to create misaligned address
-//     jalr x28 // cause instruction address midaligned trap
-// .endm
-
-// .macro CAUSE_INSTR_ACCESS
-//     la x28, 0x0 // address zero is an address with no memory
-//     jalr x28 // cause instruction access trap
-// .endm
-
-// .macro CAUSE_ILLEGAL_INSTR
-//     .word 0x00000000 // a 32 bit zros is an illegal instruction
-// .endm
-
-// .macro CAUSE_BREAKPNT // ****
-//     ebreak
-// .endm
-
-// .macro CAUSE_LOAD_ADDR_MISALIGNED
-//     auipc x28, 0      // get current PC, which is aligned
-//     addi x28, x28, 1
-//     lw x29, 0(x28)    // load from a misaligned address
-// .endm
-
-// .macro CAUSE_LOAD_ACC
-//     la x28, 0         // 0 is an address with no memory
-//     lw x29, 0(x28)    // load from unimplemented address
-// .endm
-
-// .macro CAUSE_STORE_ADDR_MISALIGNED
-//     auipc x28, 0      // get current PC, which is aligned
-//     addi x28, x28, 1
-//     sw x29, 0(x28)     // store to a misaligned address
-// .endm
-
-// .macro CAUSE_STORE_ACC 
-//     la x28, 0         // 0 is an address with no memory
-//     sw x29, 0(x28)     // store to unimplemented address
-// .endm
-
-// .macro CAUSE_ECALL
-//     // *** ASSUMES you have already gone to the mode you need to call this from.
-//     ecall
-// .endm
-
-// .macro CAUSE_TIME_INTERRUPT
-//     // The following code works for both RV32 and RV64.  
-//     // RV64 alone would be easier using double-word adds and stores
-//     li x28, 0x100          // Desired offset from the present time
-//     la x29, 0x02004000    // MTIMECMP register in CLINT
-//     la x30, 0x0200BFF8    // MTIME register in CLINT
-//     lw x7, 0(x30)         // low word of MTIME
-//     lw x31, 4(x30)         // high word of MTIME
-//     add x28, x7, x28       // add desired offset to the current time
-//     bgtu x28, x7, nowrap  // check new time exceeds current time (no wraparound)
-//     addi x31, x31, 1       // if wrap, increment most significant word
-//     sw x31,4(x29)          // store into most significant word of MTIMECMP
-// nowrap:
-//     sw x28, 0(x29)         // store into least significant word of MTIMECMP
-//     loop: j loop         // wait until interrupt occurs
-// .endm
-
-// .macro CAUSE_SOFT_INTERRUPT
-//     la x28, 0x02000000      // MSIP register in CLINT
-//     li x29, 1               // 1 in the lsb
-//     sw x29, 0(x28)          // Write MSIP bit
-// .endm
-
-// .macro CAUSE_EXT_INTERRUPT
-//     li x28, 0x10060000 // load base GPIO memory location
-//     li x29, 0x1
-//     sw x29, 8(x28) // enable the first pin as an output
-//     sw x29, 28(x28) // set first pin to high interrupt enable
-//     sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt)
-// .endm
-
 .macro END_TESTS
     // invokes one final ecall to return to machine mode then terminates this program, so the output is
     //      0x8: termination called from U mode
@@ -1154,9 +1093,20 @@ rvtest_data:
 RVTEST_DATA_END
 
 .align 3 // align stack to 8 byte boundary
-bottom_of_stack:
+stack_bottom:
     .fill 1024, 4, 0xdeadbeef 
-top_of_stack:
+stack_top:
+
+.align 3
+mscratch_bottom:
+    .fill 512, 4, 0xdeadbeef
+mscratch_top:
+
+.align 3
+sscratch_bottom:
+    .fill 512, 4, 0xdeadbeef
+sscratch_top:
+
 
 
 RVMODEL_DATA_BEGIN