forked from Github_Repos/cvw
FMA project ready to start
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David Harris
parent
0693f76676
commit
0ecfff7e3a
@ -12,12 +12,12 @@ vlog -lint -work worklib fma16.sv testbench.sv
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vopt +acc worklib.testbench_fma16 -work worklib -o testbenchopt
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vsim -lib worklib testbenchopt
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add wave sim:/testbench/clk
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add wave sim:/testbench/reset
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add wave sim:/testbench/x
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add wave sim:/testbench/y
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add wave sim:/testbench/z
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add wave sim:/testbench/result
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add wave sim:/testbench/rexpected
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add wave sim:/testbench_fma16/clk
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add wave sim:/testbench_fma16/reset
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add wave sim:/testbench_fma16/x
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add wave sim:/testbench_fma16/y
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add wave sim:/testbench_fma16/z
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add wave sim:/testbench_fma16/result
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add wave sim:/testbench_fma16/rexpected
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run -all
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@ -5,145 +5,20 @@
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// Operation: general purpose multiply, add, fma, with optional negation
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// If mul=1, p = x * y. Else p = x.
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// If add=1, result = p + z. Else result = p.
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// If negp or negz = 1, negate p or z to handle negations and subtractions
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// fadd: mul = 0, add = 1, negp = negz = 0
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// fsub: mul = 0, add = 1, negp = 0, negz = 1
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// fmul: mul = 1, add = 0, negp = 0, negz = 0
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// fma: mul = 1, add = 1, negp = 0, negz = 0
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// If negr or negz = 1, negate result or z to handle negations and subtractions
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// fadd: mul = 0, add = 1, negr = negz = 0
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// fsub: mul = 0, add = 1, negr = 0, negz = 1
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// fmul: mul = 1, add = 0, negr = 0, negz = 0
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// fmadd: mul = 1, add = 1, negr = 0, negz = 0
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// fmsub: mul = 1, add = 1, negr = 0, negz = 1
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// fnmadd: mul = 1, add = 1, negr = 1, negz = 0
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// fnmsub: mul = 1, add = 1, negr = 1, negz = 1
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module fma16(
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input logic [15:0] x, y, z,
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input logic mul, add, negp, negz,
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input logic mul, add, negr, negz,
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input logic [1:0] roundmode, // 00: rz, 01: rne, 10: rp, 11: rn
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output logic [15:0] result);
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logic [10:0] xm, ym, zm;
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logic [4:0] xe, ye, ze;
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logic xs, ys, zs;
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logic zs1; // sign before optional negation
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logic [21:0] pm;
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logic [5:0] pe;
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logic ps; // sign of product
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logic [22:0] rm;
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logic [6:0] re;
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logic rs;
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unpack16 unpack(x, y, z, xm, ym, zm, xe, ye, ze, xs, ys, zs1); // unpack inputs
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signadj16 signadj(negp, negz, xs, ys, zs1, ps, zs); // handle negations
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mult16 m(mul, xm, ym, xe, ye, pm, pe); // p = x * y
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add16 a(add, pm, zm, pe, ze, ps, zs, rm, re, rs); // r = z + p
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postproc16 post(roundmode, rm, re, rs, result); // normalize, round, pack
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endmodule
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module mult16(
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input logic mul,
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input logic [10:0] xm, ym,
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input logic [4:0] xe, ye,
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output logic [21:0] pm,
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output logic [5:0] pe);
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// only multiply if mul = 1
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assign pm = mul ? xm * ym : {1'b0, xm, 10'b0}; // multiply mantiassas
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assign pe = mul ? xe + ye : {1'b0, xe};
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endmodule
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module add16(
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input logic add,
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input logic [21:0] pm,
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input logic [10:0] zm,
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input logic [5:0] pe,
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input logic [4:0] ze,
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input logic ps, zs,
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output logic [22:0] rm,
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output logic [6:0] re,
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output logic rs);
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logic [22:0] arm;
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logic [6:0] are;
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logic ars;
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/*
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alignshift as(pe, ze, zm, zmaligned);
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condneg cnp(pm, ps, pmn);
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condneg cnz(zm, zs, zmn);
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assign
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*/
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// add or pass product through
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assign rm = add ? arm : {1'b0, pm};
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assign re = add ? are : {1'b0, pe};
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assign rs = add ? ars : ps;
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endmodule
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module postproc16(
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input logic [1:0] roundmode,
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input logic [22:0] rm,
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input logic [6:0] re,
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input logic rs,
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output logic [15:0] result);
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logic [9:0] uf, uff;
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logic [6:0] ue;
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logic [6:0] ueb, uebiased;
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always_comb
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if (rm[21]) begin // normalization right shift by 1 and bump up exponent;
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ue = re + 7'b1;
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uf = rm[20:11];
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end else begin // no normalization shift needed
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ue = re;
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uf = rm[19:10];
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end
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// overflow
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always_comb begin
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ueb = ue-7'd15;
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if (ue >= 7'd46) begin // overflow
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/* uebiased = 7'd30;
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uff = 10'h3ff; */
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end else begin
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uebiased = ue-7'd15;
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uff = uf;
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end
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end
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assign result = {rs, uebiased[4:0], uff};
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// add special case handling for zeros, NaN, Infinity
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endmodule
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module signadj16(
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input logic negx, negz,
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input logic xs, ys, zs1,
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output logic ps, zs);
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assign ps = xs ^ ys ^ negx; // sign of product
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assign zs = zs1 ^ negz; //
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endmodule
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module unpack16(
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input logic [15:0] x, y, z,
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output logic [10:0] xm, ym, zm,
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output logic [4:0] xe, ye, ze,
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output logic xs, ys, zs);
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unpacknum16 upx(x, xm, xe, xs);
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unpacknum16 upy(y, ym, ye, ys);
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unpacknum16 upz(z, zm, ze, zs);
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endmodule
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module unpacknum16(
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input logic [15:0] num,
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output logic [10:0] m,
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output logic [4:0] e,
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output logic s);
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logic [9:0] f; // fraction without leading 1
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logic [4:0] eb; // biased exponent
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assign {s, eb, f} = num; // pull bit fields out of floating-point number
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assign m = {1'b1, f}; // prepend leading 1 to fraction
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assign e = eb; // leave bias in exponent ***
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endmodule
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1
pipelined/src/fma/sim-fma-batch
Executable file
1
pipelined/src/fma/sim-fma-batch
Executable file
@ -0,0 +1 @@
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vsim -c -do "do fma.do"
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