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Wallypipeliendcore/soc cleanup

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This commit is contained in:
David Harris 2023-01-14 05:57:50 -08:00
parent 10f76dd7e6
commit 0c91505f41
2 changed files with 54 additions and 97 deletions
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112
pipelined/src/wally/wallypipelinedcore.sv
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@ -6,6 +6,8 @@
// //
// Purpose: Pipelined RISC-V Processor // Purpose: Pipelined RISC-V Processor
// //
// Documentation: RISC-V System on Chip Design (Figure 4.1)
//
// A component of the CORE-V-WALLY configurable RISC-V project. // A component of the CORE-V-WALLY configurable RISC-V project.
// //
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
@ -162,56 +164,33 @@ module wallypipelinedcore (
logic CommittedF; logic CommittedF;
// instruction fetch unit: PC, branch prediction, instruction cache // instruction fetch unit: PC, branch prediction, instruction cache
ifu ifu( ifu ifu(.clk, .reset,
.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
.StallF, .StallD, .StallE, .StallM, .StallW,
.FlushD, .FlushE, .FlushM, .FlushW,
// Fetch // Fetch
.HRDATA, .PCF, .IFUHADDR, .PCNext2F, .HRDATA, .PCF, .IFUHADDR, .PCNext2F,
.IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
.IFUHREADY, .IFUHWRITE,
.ICacheAccess, .ICacheMiss, .ICacheAccess, .ICacheMiss,
// Execute // Execute
.PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE,
.BPPredWrongE,
// Mem // Mem
.CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM, .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
.InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM,
.BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
// Faults out
// Writeback .IllegalBaseInstrFaultD, .InstrPageFaultF, .IllegalIEUInstrFaultD, .InstrMisalignedFaultM,
// output logic
// Faults
.IllegalBaseInstrFaultD, .InstrPageFaultF,
.IllegalIEUInstrFaultD, .InstrMisalignedFaultM,
// mmu management // mmu management
.PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ITLBWriteF, .sfencevmaM, .ITLBMissF,
.STATUS_MPP, .ITLBWriteF, .sfencevmaM, // pmp/pma (inside mmu) signals.
.ITLBMissF, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrDAPageFaultF);
// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.InstrAccessFaultF,
.InstrDAPageFaultF);
// integer execution unit: integer register file, datapath and controller // integer execution unit: integer register file, datapath and controller
ieu ieu( ieu ieu(.clk, .reset,
.clk, .reset,
// Decode Stage interface // Decode Stage interface
.InstrD, .IllegalIEUInstrFaultD, .InstrD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD,
.IllegalBaseInstrFaultD,
// Execute Stage interface // Execute Stage interface
.PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E,
.IEUAdrE, .IntDivE, .W64E, .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE,
.Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
// Memory stage interface // Memory stage interface
.SquashSCW, // from LSU .SquashSCW, // from LSU
.MemRWM, // read/write control goes to LSU .MemRWM, // read/write control goes to LSU
@ -220,40 +199,24 @@ module wallypipelinedcore (
.Funct3M, // size and signedness to LSU .Funct3M, // size and signedness to LSU
.SrcAM, // to privilege and fpu .SrcAM, // to privilege and fpu
.RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
// Writeback stage // Writeback stage
.CSRReadValW, .MDUResultW, .FIntDivResultW, .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]),
.RdW, .ReadDataW(ReadDataW[`XLEN-1:0]), .InstrValidM, .FCvtIntResW, .FCvtIntW,
.InstrValidM,
.FCvtIntResW,
.FCvtIntW,
// hazards // hazards
.StallD, .StallE, .StallM, .StallW, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
.FlushD, .FlushE, .FlushM, .FlushW, .FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, .PCSrcE,
.FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, .CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .StoreStallD);
.PCSrcE,
.CSRReadM, .CSRWriteM, .PrivilegedM,
.CSRWriteFenceM, .StoreStallD);
lsu lsu( lsu lsu(
.clk, .reset, .StallM, .FlushM, .StallW, .clk, .reset, .StallM, .FlushM, .StallW, .FlushW,
.FlushW,
// CPU interface // CPU interface
.MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .AtomicM,
.AtomicM, .CommittedM, .DCacheMiss, .DCacheAccess, .SquashSCW,
.CommittedM, .DCacheMiss, .DCacheAccess, .FpLoadStoreM, .FWriteDataM, .IEUAdrE, .IEUAdrM, .WriteDataM,
.SquashSCW,
.FpLoadStoreM,
.FWriteDataM,
//.DataMisalignedM(DataMisalignedM),
.IEUAdrE, .IEUAdrM, .WriteDataM,
.ReadDataW, .FlushDCacheM, .ReadDataW, .FlushDCacheM,
// connected to ahb (all stay the same) // connected to ahb (all stay the same)
.LSUHADDR, .LSUHADDR, .HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE,
.HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, .LSUHBURST, .LSUHTRANS, .LSUHWRITE, .LSUHREADY,
.LSUHWRITE, .LSUHREADY,
// connect to csr or privilege and stay the same. // connect to csr or privilege and stay the same.
.PrivilegeModeW, .BigEndianM, // connects to csr .PrivilegeModeW, .BigEndianM, // connects to csr
.PMPCFG_ARRAY_REGW, // connects to csr .PMPCFG_ARRAY_REGW, // connects to csr
@ -264,7 +227,6 @@ module wallypipelinedcore (
.STATUS_SUM, // from csr .STATUS_SUM, // from csr
.STATUS_MPRV, // from csr .STATUS_MPRV, // from csr
.STATUS_MPP, // from csr .STATUS_MPP, // from csr
.sfencevmaM, // connects to privilege .sfencevmaM, // connects to privilege
.LoadPageFaultM, // connects to privilege .LoadPageFaultM, // connects to privilege
.StoreAmoPageFaultM, // connects to privilege .StoreAmoPageFaultM, // connects to privilege
@ -274,7 +236,6 @@ module wallypipelinedcore (
.StoreAmoMisalignedFaultM, // connects to privilege .StoreAmoMisalignedFaultM, // connects to privilege
.StoreAmoAccessFaultM, // connects to privilege .StoreAmoAccessFaultM, // connects to privilege
.InstrDAPageFaultF, .InstrDAPageFaultF,
.PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW, .PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
.LSUStallM); .LSUStallM);
@ -319,12 +280,10 @@ module wallypipelinedcore (
if (`ZICSR_SUPPORTED) begin:priv if (`ZICSR_SUPPORTED) begin:priv
privileged priv( privileged priv(
.clk, .reset, .clk, .reset,
.FlushD, .FlushE, .FlushM, .FlushW, .FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW,
.StallD, .StallE, .StallM, .StallW,
.CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PCNext2F, .CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PCNext2F,
.InstrM, .CSRReadValW, .UnalignedPCNextF, .InstrM, .CSRReadValW, .UnalignedPCNextF,
.RetM, .TrapM, .RetM, .TrapM, .sfencevmaM,
.sfencevmaM,
.InstrValidM, .CommittedM, .CommittedF, .InstrValidM, .CommittedM, .CommittedF,
.FRegWriteM, .LoadStallD, .FRegWriteM, .LoadStallD,
.DirPredictionWrongM, .BTBPredPCWrongM, .DirPredictionWrongM, .BTBPredPCWrongM,
@ -334,12 +293,9 @@ module wallypipelinedcore (
.InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .InstrMisalignedFaultM, .IllegalIEUInstrFaultD,
.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
.MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
.MTIME_CLINT, .MTIME_CLINT, .IEUAdrM, .SetFflagsM,
.IEUAdrM,
.SetFflagsM,
.InstrAccessFaultF, .HPTWInstrAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW, .InstrAccessFaultF, .HPTWInstrAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW,
.IllegalFPUInstrM, .IllegalFPUInstrM, .PrivilegeModeW, .SATP_REGW,
.PrivilegeModeW, .SATP_REGW,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.FRM_REGW,.BreakpointFaultM, .EcallFaultM, .WFIStallM, .BigEndianM); .FRM_REGW,.BreakpointFaultM, .EcallFaultM, .WFIStallM, .BigEndianM);
@ -355,11 +311,10 @@ module wallypipelinedcore (
// multiply/divide unit // multiply/divide unit
if (`M_SUPPORTED) begin:mdu if (`M_SUPPORTED) begin:mdu
mdu mdu(.clk, .reset, mdu mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
.ForwardedSrcAE, .ForwardedSrcBE, .ForwardedSrcAE, .ForwardedSrcBE,
.Funct3E, .Funct3M, .IntDivE, .W64E, .Funct3E, .Funct3M, .IntDivE, .W64E,
.MDUResultW, .DivBusyE, .MDUResultW, .DivBusyE);
.StallM, .StallW, .FlushE, .FlushM, .FlushW);
end else begin // no M instructions supported end else begin // no M instructions supported
assign MDUResultW = 0; assign MDUResultW = 0;
assign DivBusyE = 0; assign DivBusyE = 0;
@ -374,7 +329,6 @@ module wallypipelinedcore (
.ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory .ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory
.ForwardedSrcAE, // Integer input being processed (from IEU) .ForwardedSrcAE, // Integer input being processed (from IEU)
.StallE, .StallM, .StallW, // stall signals from HZU .StallE, .StallM, .StallW, // stall signals from HZU
//.TrapM,
.FlushE, .FlushM, .FlushW, // flush signals from HZU .FlushE, .FlushM, .FlushW, // flush signals from HZU
.RdE, .RdM, .RdW, // which FP register to write to (from IEU) .RdE, .RdM, .RdW, // which FP register to write to (from IEU)
.STATUS_FS, // is floating-point enabled? .STATUS_FS, // is floating-point enabled?

31
pipelined/src/wally/wallypipelinedsoc.sv
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@ -6,6 +6,8 @@
// //
// Purpose: System on chip including pipelined processor and uncore memories/peripherals // Purpose: System on chip including pipelined processor and uncore memories/peripherals
// //
// Documentation: RISC-V System on Chip Design (Figure 6.20)
//
// A component of the CORE-V-WALLY configurable RISC-V project. // A component of the CORE-V-WALLY configurable RISC-V project.
// //
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
@ -28,8 +30,8 @@
module wallypipelinedsoc ( module wallypipelinedsoc (
input logic clk, input logic clk,
input logic reset_ext, input logic reset_ext, // external asynchronous reset pin
output logic reset, output logic reset, // reset synchronized to clk to prevent races on release
// AHB Interface // AHB Interface
input logic [`AHBW-1:0] HRDATAEXT, input logic [`AHBW-1:0] HRDATAEXT,
input logic HREADYEXT, HRESPEXT, input logic HREADYEXT, HRESPEXT,
@ -47,22 +49,23 @@ module wallypipelinedsoc (
output logic HMASTLOCK, output logic HMASTLOCK,
output logic HREADY, output logic HREADY,
// I/O Interface // I/O Interface
input logic TIMECLK, input logic TIMECLK, // optional for CLINT MTIME counter
input logic [31:0] GPIOPinsIn, input logic [31:0] GPIOPinsIn, // inputs from GPIO
output logic [31:0] GPIOPinsOut, GPIOPinsEn, output logic [31:0] GPIOPinsOut, // output values for GPIO
input logic UARTSin, output logic [31:0] GPIOPinsEn, // output enables for GPIO
output logic UARTSout, input logic UARTSin, // UART serial data input
input logic SDCCmdIn, output logic UARTSout, // UART serial data output
output logic SDCCmdOut, input logic SDCCmdIn, // SDC Command input
output logic SDCCmdOE, output logic SDCCmdOut, // SDC Command output
input logic [3:0] SDCDatIn, output logic SDCCmdOE, // SDC Command output enable
output logic SDCCLK input logic [3:0] SDCDatIn, // SDC data input
output logic SDCCLK // SDC clock
); );
// Uncore signals // Uncore signals
logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore
logic HRESP; logic HRESP; // response from AHB
logic MTimerInt, MSwInt; // from CLINT logic MTimerInt, MSwInt; // timer and software interrupts from CLINT
logic [63:0] MTIME_CLINT; // from CLINT to CSRs logic [63:0] MTIME_CLINT; // from CLINT to CSRs
logic MExtInt,SExtInt; // from PLIC logic MExtInt,SExtInt; // from PLIC