forked from Github_Repos/cvw
		
	sltD signal debug. Passes regression
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				@ -215,8 +215,8 @@ module controller(
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  //NOTE: Move the B conditional logic into bctrl
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  if (`ZBA_SUPPORTED) begin
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    // ALU Decoding is more comprehensive when ZBA is supported. Only conflict with Funct3 is with slt instructionsb
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    assign sltD = (Funct3D == 3'b010 & ~(Funct7D[4]));
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    // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw
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    assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ;
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  end else begin
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    assign sltD = (Funct3D == 3'b010);
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  end
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