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fpu passing idiv tests on rv32gc 1 copy of radix 2!

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Cedar Turek 2022-12-26 21:47:56 -08:00
parent bebaf08bed
commit 0b14aa852d
1 changed files with 10 additions and 10 deletions
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20
pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -53,8 +53,8 @@ module fdivsqrtpostproc(
logic NegStickyM; logic NegStickyM;
logic weq0E, weq0M; logic weq0E, weq0M;
logic [`DIVBLEN:0] NormShiftM; logic [`DIVBLEN:0] NormShiftM;
logic [`DIVb:0] IntQuotM, NormQuotM; logic [`DIVb:0] NormQuotM;
logic [`DIVb+3:0] IntRemM, NormRemM; logic [`DIVb+3:0] IntQuotM, IntRemM, NormRemM;
logic signed [`DIVb+3:0] PreResultM, PreFPIntDivResultM; logic signed [`DIVb+3:0] PreResultM, PreFPIntDivResultM;
logic WZeroM; logic WZeroM;
@ -116,10 +116,10 @@ module fdivsqrtpostproc(
// if (NegStickyM | weq0) begin // *** old code, replaced by the one below in the right stage and more comprehensive // if (NegStickyM | weq0) begin // *** old code, replaced by the one below in the right stage and more comprehensive
if (NegStickyM | WZeroM) begin if (NegStickyM | WZeroM) begin
NormQuotM = FirstUM; NormQuotM = FirstUM;
NormRemM = W; NormRemM = -(W + DM);
end else begin end else begin
NormQuotM = FirstU; NormQuotM = FirstU;
NormRemM = W - DM; NormRemM = -W;
end end
// Integer division: Special cases // Integer division: Special cases
@ -128,17 +128,17 @@ module fdivsqrtpostproc(
IntQuotM = '0; IntQuotM = '0;
IntRemM = {{(`DIVb-`XLEN+4){1'b0}}, ForwardedSrcAM}; IntRemM = {{(`DIVb-`XLEN+4){1'b0}}, ForwardedSrcAM};
end else begin end else begin
logic [`DIVb:0] PreIntQuotM; logic [`DIVb+3:0] PreIntQuotM;
if (WZeroM) begin if (WZeroM) begin
if (weq0M) begin if (weq0M) begin
PreIntQuotM = FirstU; PreIntQuotM = {3'b000, FirstU};
IntRemM = '0; IntRemM = '0;
end else begin end else begin
PreIntQuotM = FirstUM; PreIntQuotM = {3'b000, FirstUM};
IntRemM = '0; IntRemM = '0;
end end
end else begin end else begin
PreIntQuotM = NormQuotM; PreIntQuotM = {3'b000, NormQuotM};
IntRemM = NormRemM; IntRemM = NormRemM;
end end
// flip sign if necessary // flip sign if necessary
@ -148,11 +148,11 @@ module fdivsqrtpostproc(
always_comb always_comb
if (RemOpM) begin if (RemOpM) begin
NormShiftM = (mM + (`DIVBLEN+1)'(`DIVa)); NormShiftM = ALTBM ? '0 : (mM + (`DIVBLEN+1)'(`DIVa)); // no postshift if forwarding input A to remainder
PreResultM = IntRemM; PreResultM = IntRemM;
end else begin end else begin
NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR))); NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR)));
PreResultM = {{3{IntQuotM[`DIVb]}}, IntQuotM}; PreResultM = IntQuotM;
/* /*
if (~ALTBM & NegQuotM) begin if (~ALTBM & NegQuotM) begin
PreResultM = {3'b111, -IntQuotM}; PreResultM = {3'b111, -IntQuotM};