forked from Github_Repos/cvw
fpu passing idiv tests on rv32gc 1 copy of radix 2!
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@ -53,8 +53,8 @@ module fdivsqrtpostproc(
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logic NegStickyM;
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logic NegStickyM;
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logic weq0E, weq0M;
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logic weq0E, weq0M;
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logic [`DIVBLEN:0] NormShiftM;
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logic [`DIVBLEN:0] NormShiftM;
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logic [`DIVb:0] IntQuotM, NormQuotM;
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logic [`DIVb:0] NormQuotM;
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logic [`DIVb+3:0] IntRemM, NormRemM;
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logic [`DIVb+3:0] IntQuotM, IntRemM, NormRemM;
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logic signed [`DIVb+3:0] PreResultM, PreFPIntDivResultM;
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logic signed [`DIVb+3:0] PreResultM, PreFPIntDivResultM;
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logic WZeroM;
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logic WZeroM;
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@ -116,10 +116,10 @@ module fdivsqrtpostproc(
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// if (NegStickyM | weq0) begin // *** old code, replaced by the one below in the right stage and more comprehensive
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// if (NegStickyM | weq0) begin // *** old code, replaced by the one below in the right stage and more comprehensive
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if (NegStickyM | WZeroM) begin
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if (NegStickyM | WZeroM) begin
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NormQuotM = FirstUM;
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NormQuotM = FirstUM;
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NormRemM = W;
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NormRemM = -(W + DM);
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end else begin
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end else begin
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NormQuotM = FirstU;
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NormQuotM = FirstU;
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NormRemM = W - DM;
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NormRemM = -W;
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end
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end
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// Integer division: Special cases
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// Integer division: Special cases
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@ -128,17 +128,17 @@ module fdivsqrtpostproc(
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IntQuotM = '0;
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IntQuotM = '0;
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IntRemM = {{(`DIVb-`XLEN+4){1'b0}}, ForwardedSrcAM};
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IntRemM = {{(`DIVb-`XLEN+4){1'b0}}, ForwardedSrcAM};
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end else begin
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end else begin
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logic [`DIVb:0] PreIntQuotM;
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logic [`DIVb+3:0] PreIntQuotM;
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if (WZeroM) begin
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if (WZeroM) begin
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if (weq0M) begin
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if (weq0M) begin
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PreIntQuotM = FirstU;
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PreIntQuotM = {3'b000, FirstU};
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IntRemM = '0;
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IntRemM = '0;
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end else begin
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end else begin
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PreIntQuotM = FirstUM;
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PreIntQuotM = {3'b000, FirstUM};
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IntRemM = '0;
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IntRemM = '0;
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end
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end
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end else begin
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end else begin
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PreIntQuotM = NormQuotM;
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PreIntQuotM = {3'b000, NormQuotM};
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IntRemM = NormRemM;
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IntRemM = NormRemM;
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end
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end
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// flip sign if necessary
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// flip sign if necessary
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@ -148,11 +148,11 @@ module fdivsqrtpostproc(
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always_comb
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always_comb
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if (RemOpM) begin
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if (RemOpM) begin
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NormShiftM = (mM + (`DIVBLEN+1)'(`DIVa));
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NormShiftM = ALTBM ? '0 : (mM + (`DIVBLEN+1)'(`DIVa)); // no postshift if forwarding input A to remainder
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PreResultM = IntRemM;
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PreResultM = IntRemM;
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end else begin
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end else begin
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NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR)));
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NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR)));
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PreResultM = {{3{IntQuotM[`DIVb]}}, IntQuotM};
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PreResultM = IntQuotM;
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/*
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/*
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if (~ALTBM & NegQuotM) begin
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if (~ALTBM & NegQuotM) begin
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PreResultM = {3'b111, -IntQuotM};
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PreResultM = {3'b111, -IntQuotM};
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