forked from Github_Repos/cvw
Merge remote-tracking branch 'upstream/main' into main
This commit is contained in:
Kip Macsai-Goren
commit
0a6787026b
31
.gitignore
vendored
31
.gitignore
vendored
@ -81,37 +81,6 @@ synthDC/runArchive
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||||
synthDC/hdl
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/pipelined/regression/power.saif
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tests/fp/vectors/*.tv
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# Temporary configs produced for synthesis
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pipelined/config/rv32e_FPUoff
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||||
pipelined/config/rv32e_PMP0
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||||
pipelined/config/rv32e_PMP16
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||||
pipelined/config/rv32e_noMulDiv
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||||
pipelined/config/rv32e_noPriv
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||||
pipelined/config/rv32e_orig
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||||
pipelined/config/rv32gc_FPUoff
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||||
pipelined/config/rv32gc_PMP0
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||||
pipelined/config/rv32gc_PMP16
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||||
pipelined/config/rv32gc_noMulDiv
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||||
pipelined/config/rv32gc_noPriv
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||||
pipelined/config/rv32gc_orig
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pipelined/config/rv32ic_FPUoff
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||||
pipelined/config/rv32ic_PMP0
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||||
pipelined/config/rv32ic_PMP16
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pipelined/config/rv32ic_noMulDiv
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||||
pipelined/config/rv32ic_noPriv
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||||
pipelined/config/rv32ic_orig
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||||
pipelined/config/rv64gc_FPUoff
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||||
pipelined/config/rv64gc_PMP0
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||||
pipelined/config/rv64gc_PMP16
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||||
pipelined/config/rv64gc_noMulDiv
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pipelined/config/rv64gc_noPriv
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pipelined/config/rv64gc_orig
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pipelined/config/rv64ic_FPUoff
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pipelined/config/rv64ic_PMP0
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pipelined/config/rv64ic_PMP16
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pipelined/config/rv64ic_noMulDiv
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||||
pipelined/config/rv64ic_noPriv
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||||
pipelined/config/rv64ic_orig
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||||
synthDC/Summary.csv
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pipelined/srt/exptestgen
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pipelined/srt/testgen
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@ -1,35 +0,0 @@
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// fir.s
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// mmasserfrye@hmc.edu 30 January 2022
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// FIR filter
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// a0 = N, a1 = M, a2 = &X, a3 = &c, a4 = &Y
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.global fir
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fir:
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li t0, 0 # n = 0 = t0
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slli t6, a0, 3 # N*8
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slli t5, a1, 3 # M*8
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addi t4, t5, -8 # (M-1)*8
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for1:
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bge t0, t6, end # exit outer for if n >= N
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fmv.d.x f3, zero # sum = 0 = f3
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li t2, 0 # i = 0 = t2
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add t1, t4, t0 # [(M-1) + n]*8
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for2:
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bge t2, t5, for1end # exit inner for if i >= M
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sub t3, t1, t2 # [(M-1) + n - i]*8
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add t3, t3, a2 # t3 = offset + &X
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fld f0, 0(t3) # X[n-i+(M-1)]
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add t3, t2, a3 # t3 = offset + &c
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fld f1, 0(t3) # c[i]
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fmadd.d f3, f0, f1, f3 # sum += c[i]*X[n-i+(M-1)]
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addi t2, t2, 8 # i++
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j for2
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for1end:
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add t3, t0, a4 # t3 = offset + &Y
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fsd f3, 0(t3) # Y[n] = sum
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addi t0, t0, 8 # n++
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j for1
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end:
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ret
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@ -130,8 +130,20 @@
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`define BPRED_SUPPORTED 1
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`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
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`define TESTSBP 0
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`define BPRED_SIZE 10
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`define HPTW_WRITES_SUPPORTED 1
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// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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// bit manipulation
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`define ZBA_SUPPORTED 0
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`define ZBB_SUPPORTED 0
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`define ZBC_SUPPORTED 0
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`define ZBS_SUPPORTED 0
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// Memory synthesis configuration
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`define USE_SRAM 0
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@ -139,8 +139,20 @@
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`define BPRED_SUPPORTED 1
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`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
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`define TESTSBP 1
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`define BPRED_SIZE 10
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`define HPTW_WRITES_SUPPORTED 1
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// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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// bit manipulation
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`define ZBA_SUPPORTED 0
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`define ZBB_SUPPORTED 0
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`define ZBC_SUPPORTED 0
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`define ZBS_SUPPORTED 0
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// Memory synthesis configuration
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`define USE_SRAM 0
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@ -134,7 +134,19 @@
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`define BPRED_SUPPORTED 0
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`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
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`define TESTSBP 0
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`define BPRED_SIZE 10
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`define HPTW_WRITES_SUPPORTED 0
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// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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// bit manipulation
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`define ZBA_SUPPORTED 0
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`define ZBB_SUPPORTED 0
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`define ZBC_SUPPORTED 0
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`define ZBS_SUPPORTED 0
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// Memory synthesis configuration
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`define USE_SRAM 0
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@ -68,7 +68,7 @@
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// Integer Divider Configuration
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// IDIV_BITSPERCYCLE must be 1, 2, or 4
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`define IDIV_BITSPERCYCLE 4
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`define IDIV_ON_FPU 0
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`define IDIV_ON_FPU 1
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 16
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@ -133,7 +133,19 @@
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`define BPRED_SUPPORTED 1
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`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
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`define TESTSBP 0
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`define BPRED_SIZE 10
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||||
`define HPTW_WRITES_SUPPORTED 0
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// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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// bit manipulation
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`define ZBA_SUPPORTED 0
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`define ZBB_SUPPORTED 0
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`define ZBC_SUPPORTED 0
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`define ZBS_SUPPORTED 0
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||||
|
||||
// Memory synthesis configuration
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||||
`define USE_SRAM 0
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||||
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||||
@ -134,7 +134,19 @@
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|
||||
`define BPRED_SUPPORTED 0
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`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
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`define TESTSBP 0
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`define BPRED_SIZE 10
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||||
`define HPTW_WRITES_SUPPORTED 0
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||||
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||||
// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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// bit manipulation
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`define ZBA_SUPPORTED 0
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`define ZBB_SUPPORTED 0
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||||
`define ZBC_SUPPORTED 0
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||||
`define ZBS_SUPPORTED 0
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||||
// Memory synthesis configuration
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||||
`define USE_SRAM 0
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||||
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||||
@ -37,7 +37,7 @@
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||||
// IEEE 754 compliance
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||||
`define IEEE754 0
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||||
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||||
`define MISA (32'h00000104 | 1 << 20 | 1 << 18 )
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`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12)
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`define ZICSR_SUPPORTED 1
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`define ZIFENCEI_SUPPORTED 1
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`define COUNTERS 32
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@ -133,7 +133,19 @@
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||||
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||||
`define BPRED_SUPPORTED 0
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`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
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`define TESTSBP 0
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`define BPRED_SIZE 10
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||||
`define HPTW_WRITES_SUPPORTED 0
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// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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// bit manipulation
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`define ZBA_SUPPORTED 0
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`define ZBB_SUPPORTED 0
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`define ZBC_SUPPORTED 0
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`define ZBS_SUPPORTED 0
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||||
// Memory synthesis configuration
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`define USE_SRAM 0
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@ -136,7 +136,19 @@
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||||
|
||||
`define BPRED_SUPPORTED 1
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`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
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`define TESTSBP 0
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`define BPRED_SIZE 10
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`define HPTW_WRITES_SUPPORTED 0
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// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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// bit manipulation
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`define ZBA_SUPPORTED 0
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`define ZBB_SUPPORTED 0
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`define ZBC_SUPPORTED 0
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`define ZBS_SUPPORTED 0
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|
||||
// Memory synthesis configuration
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`define USE_SRAM 0
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@ -136,7 +136,19 @@
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|
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`define BPRED_SUPPORTED 1
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`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
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`define TESTSBP 0
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`define BPRED_SIZE 10
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`define HPTW_WRITES_SUPPORTED 0
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// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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||||
// bit manipulation
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`define ZBA_SUPPORTED 0
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`define ZBB_SUPPORTED 0
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||||
`define ZBC_SUPPORTED 0
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`define ZBS_SUPPORTED 0
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||||
|
||||
// Memory synthesis configuration
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||||
`define USE_SRAM 0
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||||
|
||||
@ -136,7 +136,19 @@
|
||||
|
||||
`define BPRED_SUPPORTED 0
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||||
`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
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||||
`define TESTSBP 0
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||||
`define BPRED_SIZE 10
|
||||
|
||||
`define HPTW_WRITES_SUPPORTED 0
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||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
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||||
`define DIVCOPIES 32'h4
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||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 0
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||||
`define ZBB_SUPPORTED 0
|
||||
`define ZBC_SUPPORTED 0
|
||||
`define ZBS_SUPPORTED 0
|
||||
|
||||
// Memory synthesis configuration
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||||
`define USE_SRAM 0
|
||||
|
||||
@ -1,148 +0,0 @@
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||||
//////////////////////////////////////////
|
||||
// wally-constants.vh
|
||||
//
|
||||
// Written: tfleming@hmc.edu 4 March 2021
|
||||
// Modified: Kmacsaigoren@hmc.edu 31 May 2021
|
||||
// Added constants for checking sv mode and changed existing constants to accomodate
|
||||
// both sv48 and sv39
|
||||
//
|
||||
// Purpose: Specify constants nexessary for different memory virtualization modes.
|
||||
// These are specific to sv49, defined in section 4.5 of the privileged spec.
|
||||
// However, despite different constants for different modes, the hardware helps distinguish between
|
||||
// each mode.
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// constants defining different privilege modes
|
||||
// defined in Table 1.1 of the privileged spec
|
||||
`define M_MODE (2'b11)
|
||||
`define S_MODE (2'b01)
|
||||
`define U_MODE (2'b00)
|
||||
|
||||
// Virtual Memory Constants
|
||||
`define VPN_SEGMENT_BITS (`XLEN == 32 ? 10 : 9)
|
||||
`define VPN_BITS (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS))
|
||||
`define PPN_BITS (`XLEN==32 ? 22 : 44)
|
||||
`define PA_BITS (`XLEN==32 ? 34 : 56)
|
||||
`define SVMODE_BITS (`XLEN==32 ? 1 : 4)
|
||||
`define ASID_BASE (`XLEN==32 ? 22 : 44)
|
||||
`define ASID_BITS (`XLEN==32 ? 9 : 16)
|
||||
|
||||
// constants to check SATP_MODE against
|
||||
// defined in Table 4.3 of the privileged spec
|
||||
`define NO_TRANSLATE 0
|
||||
`define SV32 1
|
||||
`define SV39 8
|
||||
`define SV48 9
|
||||
|
||||
// macros to define supported modes
|
||||
`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
|
||||
`define B_SUPPORTED ((`ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED)) // not based on MISA
|
||||
`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
|
||||
`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
|
||||
`define E_SUPPORTED ((`MISA >> 4) % 2 == 1)
|
||||
`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
|
||||
`define I_SUPPORTED ((`MISA >> 8) % 2 == 1)
|
||||
`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
|
||||
`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1)
|
||||
`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
|
||||
`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
|
||||
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
|
||||
|
||||
// logarithm of XLEN, used for number of index bits to select
|
||||
`define LOG_XLEN (`XLEN == 32 ? 5 : 6)
|
||||
|
||||
// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
|
||||
`define PMPCFG_ENTRIES (`PMP_ENTRIES/8)
|
||||
|
||||
// Floating point constants for Quad, Double, Single, and Half precisions
|
||||
`define Q_LEN 32'd128
|
||||
`define Q_NE 32'd15
|
||||
`define Q_NF 32'd112
|
||||
`define Q_BIAS 32'd16383
|
||||
`define Q_FMT 2'd3
|
||||
`define D_LEN 32'd64
|
||||
`define D_NE 32'd11
|
||||
`define D_NF 32'd52
|
||||
`define D_BIAS 32'd1023
|
||||
`define D_FMT 2'd1
|
||||
`define S_LEN 32'd32
|
||||
`define S_NE 32'd8
|
||||
`define S_NF 32'd23
|
||||
`define S_BIAS 32'd127
|
||||
`define S_FMT 2'd0
|
||||
`define H_LEN 32'd16
|
||||
`define H_NE 32'd5
|
||||
`define H_NF 32'd10
|
||||
`define H_BIAS 32'd15
|
||||
`define H_FMT 2'd2
|
||||
|
||||
// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
|
||||
`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `S_LEN)
|
||||
`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `S_NE)
|
||||
`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `S_NF)
|
||||
`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : 2'd0)
|
||||
`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `S_BIAS)
|
||||
/* Delete once tested dh 10/10/22
|
||||
|
||||
`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN)
|
||||
`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE)
|
||||
`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF)
|
||||
`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : `F_SUPPORTED ? 2'd0 : 2'd2)
|
||||
`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)*/
|
||||
|
||||
// Floating point constants needed for FPU paramerterization
|
||||
`define FPSIZES ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED))
|
||||
`define FMTBITS ((32)'(`FPSIZES>=3)+1)
|
||||
`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN)
|
||||
`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE)
|
||||
`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF)
|
||||
`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0 : 2'd2)
|
||||
`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS)
|
||||
`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN)
|
||||
`define NE2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE)
|
||||
`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF)
|
||||
`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0 : 2'd2)
|
||||
`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS)
|
||||
|
||||
// largest length in IEU/FPU
|
||||
`define CVTLEN ((`NF<`XLEN) ? (`XLEN) : (`NF))
|
||||
`define LLEN ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN))
|
||||
`define LOGCVTLEN $unsigned($clog2(`CVTLEN+1))
|
||||
`define NORMSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6)))
|
||||
`define LOGNORMSHIFTSZ ($clog2(`NORMSHIFTSZ))
|
||||
`define CORRSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVN+1+`NF) > (3*`NF+4) ? (`DIVN+1+`NF) : (3*`NF+4)))
|
||||
|
||||
// division constants
|
||||
|
||||
`define DIVN (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input
|
||||
`define LOGR ($clog2(`RADIX)) // r = log(R)
|
||||
`define RK (`LOGR*`DIVCOPIES) // r*k used for intdiv preproc
|
||||
`define LOGRK ($clog2(`RK)) // log2(r*k)
|
||||
`define FPDUR ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4))
|
||||
`define DURLEN ($clog2(`FPDUR+1))
|
||||
`define DIVb (`FPDUR*`LOGR*`DIVCOPIES-1) // canonical fdiv size (b)
|
||||
`define DIVBLEN ($clog2(`DIVb+1)-1)
|
||||
`define DIVa (`DIVb+1-`XLEN) // used for idiv on fpu
|
||||
|
||||
// Disable spurious Verilator warnings
|
||||
|
||||
/* verilator lint_off STMTDLY */
|
||||
/* verilator lint_off ASSIGNDLY */
|
||||
/* verilator lint_off PINCONNECTEMPTY */
|
||||
@ -23,19 +23,123 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// division constants
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
// constants defining different privilege modes
|
||||
// defined in Table 1.1 of the privileged spec
|
||||
`define M_MODE (2'b11)
|
||||
`define S_MODE (2'b01)
|
||||
`define U_MODE (2'b00)
|
||||
|
||||
// eventually move to each config
|
||||
`define ZBA_SUPPORTED 0
|
||||
`define ZBB_SUPPORTED 0
|
||||
`define ZBC_SUPPORTED 0
|
||||
`define ZBS_SUPPORTED 0
|
||||
// Virtual Memory Constants
|
||||
`define VPN_SEGMENT_BITS (`XLEN == 32 ? 10 : 9)
|
||||
`define VPN_BITS (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS))
|
||||
`define PPN_BITS (`XLEN==32 ? 22 : 44)
|
||||
`define PA_BITS (`XLEN==32 ? 34 : 56)
|
||||
`define SVMODE_BITS (`XLEN==32 ? 1 : 4)
|
||||
`define ASID_BASE (`XLEN==32 ? 22 : 44)
|
||||
`define ASID_BITS (`XLEN==32 ? 9 : 16)
|
||||
|
||||
// constants to check SATP_MODE against
|
||||
// defined in Table 4.3 of the privileged spec
|
||||
`define NO_TRANSLATE 0
|
||||
`define SV32 1
|
||||
`define SV39 8
|
||||
`define SV48 9
|
||||
|
||||
// macros to define supported modes
|
||||
`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
|
||||
`define B_SUPPORTED ((`ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED)) // not based on MISA
|
||||
`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
|
||||
`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
|
||||
`define E_SUPPORTED ((`MISA >> 4) % 2 == 1)
|
||||
`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
|
||||
`define I_SUPPORTED ((`MISA >> 8) % 2 == 1)
|
||||
`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
|
||||
`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1)
|
||||
`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
|
||||
`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
|
||||
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
|
||||
|
||||
// logarithm of XLEN, used for number of index bits to select
|
||||
`define LOG_XLEN (`XLEN == 32 ? 5 : 6)
|
||||
|
||||
// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
|
||||
`define PMPCFG_ENTRIES (`PMP_ENTRIES/8)
|
||||
|
||||
// Floating point constants for Quad, Double, Single, and Half precisions
|
||||
`define Q_LEN 32'd128
|
||||
`define Q_NE 32'd15
|
||||
`define Q_NF 32'd112
|
||||
`define Q_BIAS 32'd16383
|
||||
`define Q_FMT 2'd3
|
||||
`define D_LEN 32'd64
|
||||
`define D_NE 32'd11
|
||||
`define D_NF 32'd52
|
||||
`define D_BIAS 32'd1023
|
||||
`define D_FMT 2'd1
|
||||
`define S_LEN 32'd32
|
||||
`define S_NE 32'd8
|
||||
`define S_NF 32'd23
|
||||
`define S_BIAS 32'd127
|
||||
`define S_FMT 2'd0
|
||||
`define H_LEN 32'd16
|
||||
`define H_NE 32'd5
|
||||
`define H_NF 32'd10
|
||||
`define H_BIAS 32'd15
|
||||
`define H_FMT 2'd2
|
||||
|
||||
// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
|
||||
`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `S_LEN)
|
||||
`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `S_NE)
|
||||
`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `S_NF)
|
||||
`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : 2'd0)
|
||||
`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `S_BIAS)
|
||||
/* Delete once tested dh 10/10/22
|
||||
|
||||
`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN)
|
||||
`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE)
|
||||
`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF)
|
||||
`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : `F_SUPPORTED ? 2'd0 : 2'd2)
|
||||
`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)*/
|
||||
|
||||
// Floating point constants needed for FPU paramerterization
|
||||
`define FPSIZES ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED))
|
||||
`define FMTBITS ((32)'(`FPSIZES>=3)+1)
|
||||
`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN)
|
||||
`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE)
|
||||
`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF)
|
||||
`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0 : 2'd2)
|
||||
`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS)
|
||||
`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN)
|
||||
`define NE2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE)
|
||||
`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF)
|
||||
`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0 : 2'd2)
|
||||
`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS)
|
||||
|
||||
// largest length in IEU/FPU
|
||||
`define CVTLEN ((`NF<`XLEN) ? (`XLEN) : (`NF))
|
||||
`define LLEN ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN))
|
||||
`define LOGCVTLEN $unsigned($clog2(`CVTLEN+1))
|
||||
`define NORMSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6)))
|
||||
`define LOGNORMSHIFTSZ ($clog2(`NORMSHIFTSZ))
|
||||
`define CORRSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVN+1+`NF) > (3*`NF+4) ? (`DIVN+1+`NF) : (3*`NF+4)))
|
||||
|
||||
// division constants
|
||||
|
||||
`define DIVN (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input
|
||||
`define LOGR ($clog2(`RADIX)) // r = log(R)
|
||||
`define RK (`LOGR*`DIVCOPIES) // r*k used for intdiv preproc
|
||||
`define LOGRK ($clog2(`RK)) // log2(r*k)
|
||||
`define FPDUR ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4))
|
||||
`define DURLEN ($clog2(`FPDUR+1))
|
||||
`define DIVb (`FPDUR*`LOGR*`DIVCOPIES-1) // canonical fdiv size (b)
|
||||
`define DIVBLEN ($clog2(`DIVb+1)-1)
|
||||
`define DIVa (`DIVb+1-`XLEN) // used for idiv on fpu
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
|
||||
// shared constants
|
||||
`include "wally-constants.vh"
|
||||
// Disable spurious Verilator warnings
|
||||
|
||||
/* verilator lint_off STMTDLY */
|
||||
/* verilator lint_off ASSIGNDLY */
|
||||
/* verilator lint_off PINCONNECTEMPTY */
|
||||
|
||||
@ -5,7 +5,7 @@ export PATH=$PATH:/usr/local/bin/
|
||||
verilator=`which verilator`
|
||||
|
||||
basepath=$(dirname $0)/..
|
||||
for config in rv32e rv64gc rv32gc rv32ic rv32i rv64i rv64fpquad; do
|
||||
for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
|
||||
#for config in rv64gc; do
|
||||
echo "$config linting..."
|
||||
if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
|
||||
|
||||
@ -94,13 +94,13 @@ for test in tests32gc:
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
tests32icimperas = ["imperas32i", "imperas32c"] # unused
|
||||
tests32ic = ["arch32i", "arch32c", "wally32periph"]
|
||||
for test in tests32ic:
|
||||
tests32imcimperas = ["imperas32i", "imperas32c"] # unused
|
||||
tests32imc = ["arch32i", "arch32c", "arch32m", "wally32periph"]
|
||||
for test in tests32imc:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
variant="rv32ic",
|
||||
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32ic "+test+"\n!",
|
||||
variant="rv32imc",
|
||||
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32imc "+test+"\n!",
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
|
||||
@ -1,56 +0,0 @@
|
||||
# wally-pipelined.do
|
||||
#
|
||||
# Modification by Oklahoma State University & Harvey Mudd College
|
||||
# Use with Testbench
|
||||
# James Stine, 2008; David Harris 2021
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
|
||||
|
||||
# Use this wally-pipelined.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do wally-pipelined.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do wally-pipelined.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
# suppress spurious warnngs about
|
||||
# "Extra checking for conflicts with always_comb done at vopt time"
|
||||
# because vsim will run vopt
|
||||
|
||||
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
|
||||
# do wally-pipelined.do ../config/rv32ic
|
||||
#switch $argc {
|
||||
# 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
# 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
#}
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-harvard.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
vopt +acc work.testbench -G TEST=$2 -o workopt
|
||||
vsim workopt
|
||||
|
||||
view wave
|
||||
-- display input and output signals as hexidecimal values
|
||||
#do ./wave-dos/peripheral-waves.do
|
||||
add log -recursive /*
|
||||
do wave.do
|
||||
|
||||
-- Run the Simulation
|
||||
#run 3600
|
||||
run -all
|
||||
#quit
|
||||
#noview ../testbench/testbench-imperas.sv
|
||||
noview ../testbench/testbench.sv
|
||||
view wave
|
||||
@ -8,7 +8,7 @@
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# Usage: do wally-pipelined-batch.do <config> <testcases>
|
||||
# Example: do wally-pipelined-batch.do rv32ic imperas-32i
|
||||
# Example: do wally-pipelined-batch.do rv32imc imperas-32i
|
||||
|
||||
# Use this wally-pipelined-batch.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
@ -37,7 +37,7 @@ if {$2 eq "ahb"} {
|
||||
# because vsim will run vopt
|
||||
|
||||
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
|
||||
# do wally-pipelined-batch.do ../config/rv32ic rv32ic
|
||||
# do wally-pipelined-batch.do ../config/rv32imc rv32imc
|
||||
if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
|
||||
@ -49,17 +49,17 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
|
||||
// ***************************************************************************
|
||||
// TRUE SRAM macro
|
||||
// ***************************************************************************
|
||||
if (`USE_SRAM == 1 && WIDTH == 128 && `XLEN == 64) begin
|
||||
if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 64) begin
|
||||
genvar index;
|
||||
// 64 x 128-bit SRAM
|
||||
logic [WIDTH-1:0] BitWriteMask;
|
||||
for (index=0; index < WIDTH; index++)
|
||||
assign BitWriteMask[index] = bwe[index/8];
|
||||
ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
|
||||
TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
|
||||
.A(addr), .D(din),
|
||||
.BWEB(~BitWriteMask), .Q(dout));
|
||||
|
||||
end else if (`USE_SRAM == 1 && WIDTH == 44 && `XLEN == 64) begin
|
||||
end else if (`USE_SRAM == 1 && WIDTH == 44 && DEPTH == 64) begin
|
||||
genvar index;
|
||||
// 64 x 44-bit SRAM
|
||||
logic [WIDTH-1:0] BitWriteMask;
|
||||
|
||||
@ -6,6 +6,8 @@
|
||||
// When clk rises Addr and LineWriteData are sampled.
|
||||
// Following the clk edge read data is output from the sampled Addr.
|
||||
// Write
|
||||
// Modified: james.stine@okstate.edu Feb 1, 2023
|
||||
// Integration of memories
|
||||
//
|
||||
// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
|
||||
//
|
||||
@ -43,11 +45,57 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
|
||||
);
|
||||
|
||||
logic [WIDTH-1:0] mem[DEPTH-1:0];
|
||||
localparam SRAMWIDTH = 32;
|
||||
localparam SRAMNUMSETS = SRAMWIDTH/WIDTH;
|
||||
|
||||
// ***************************************************************************
|
||||
// TRUE Smem macro
|
||||
// ***************************************************************************
|
||||
|
||||
if (`USE_SRAM == 1 && WIDTH == 68 && DEPTH == 1024) begin
|
||||
|
||||
ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk),
|
||||
.CEBA(~ce1), .CEBB(~ce2),
|
||||
.WEBA('0), .WEBB(~we2),
|
||||
.AA(ra1), .AB(wa2),
|
||||
.DA('0),
|
||||
.DB(wd2),
|
||||
.BWEBA('0), .BWEBB('1),
|
||||
.QA(rd1),
|
||||
.QB());
|
||||
|
||||
end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 1024) begin
|
||||
|
||||
logic [SRAMWIDTH-1:0] SRAMReadData;
|
||||
logic [SRAMWIDTH-1:0] SRAMWriteData;
|
||||
logic [SRAMWIDTH-1:0] RD1Sets[SRAMNUMSETS-1:0];
|
||||
logic [SRAMNUMSETS-1:0] SRAMBitMaskPre;
|
||||
logic [SRAMWIDTH-1:0] SRAMBitMask;
|
||||
logic [$clog2(DEPTH)-1:0] RA1Q;
|
||||
|
||||
|
||||
onehotdecoder #($clog2(SRAMNUMSETS)) oh1(wa2[$clog2(SRAMNUMSETS)-1:0], SRAMBitMaskPre);
|
||||
genvar index;
|
||||
for (index = 0; index < SRAMNUMSETS; index++) begin:readdatalinesetsmux
|
||||
assign RD1Sets[index] = SRAMReadData[(index*WIDTH)+WIDTH-1 : (index*WIDTH)];
|
||||
assign SRAMWriteData[index*2+1:index*2] = wd2;
|
||||
assign SRAMBitMask[index*2+1:index*2] = {2{SRAMBitMaskPre[index]}};
|
||||
end
|
||||
flopen #($clog2(DEPTH)) mem_reg1 (clk, ce1, ra1, RA1Q);
|
||||
assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]];
|
||||
ram2p1r1wbe_64x32 memory2(.CLKA(clk), .CLKB(clk),
|
||||
.CEBA(~ce1), .CEBB(~ce2),
|
||||
.WEBA('0), .WEBB(~we2),
|
||||
.AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]),
|
||||
.AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]),
|
||||
.DA('0),
|
||||
.DB(SRAMWriteData),
|
||||
.BWEBA('0), .BWEBB(SRAMBitMask),
|
||||
.QA(SRAMReadData),
|
||||
.QB());
|
||||
|
||||
end else begin
|
||||
|
||||
// ***************************************************************************
|
||||
// READ first SRAM model
|
||||
// ***************************************************************************
|
||||
@ -69,4 +117,6 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
|
||||
if (ce2 & we2 & bwe2[WIDTH/8])
|
||||
mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8];
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
///////////////////////////////////////////
|
||||
// ram2p1rwbe_1024x69.sv
|
||||
// ram2p1rwbe_1024x68.sv
|
||||
//
|
||||
// Written: james.stine@okstate.edu 28 January 2023
|
||||
// Modified:
|
||||
@ -24,7 +24,7 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module ram2p1r1wbe_1024x69(
|
||||
module ram2p1r1wbe_1024x68(
|
||||
input logic CLKA,
|
||||
input logic CLKB,
|
||||
input logic CEBA,
|
||||
@ -33,16 +33,16 @@ module ram2p1r1wbe_1024x69(
|
||||
input logic WEBB,
|
||||
input logic [9:0] AA,
|
||||
input logic [9:0] AB,
|
||||
input logic [68:0] DA,
|
||||
input logic [68:0] DB,
|
||||
input logic [68:0] BWEBA,
|
||||
input logic [68:0] BWEBB,
|
||||
output logic [68:0] QA,
|
||||
output logic [68:0] QB
|
||||
input logic [67:0] DA,
|
||||
input logic [67:0] DB,
|
||||
input logic [67:0] BWEBA,
|
||||
input logic [67:0] BWEBB,
|
||||
output logic [67:0] QA,
|
||||
output logic [67:0] QB
|
||||
);
|
||||
|
||||
// replace "generic1024x69RAM" with "TSDN..1024X69.." module from your memory vendor
|
||||
generic1024x69RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
|
||||
generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
|
||||
.AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
|
||||
|
||||
endmodule
|
||||
48
pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv
Executable file
48
pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv
Executable file
@ -0,0 +1,48 @@
|
||||
///////////////////////////////////////////
|
||||
// ram2p1rwbe_64x32.sv
|
||||
//
|
||||
// Written: james.stine@okstate.edu 28 January 2023
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: RAM wrapper for instantiating RAM IP
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module ram2p1r1wbe_64x32(
|
||||
input logic CLKA,
|
||||
input logic CLKB,
|
||||
input logic CEBA,
|
||||
input logic CEBB,
|
||||
input logic WEBA,
|
||||
input logic WEBB,
|
||||
input logic [5:0] AA,
|
||||
input logic [5:0] AB,
|
||||
input logic [31:0] DA,
|
||||
input logic [31:0] DB,
|
||||
input logic [31:0] BWEBA,
|
||||
input logic [31:0] BWEBB,
|
||||
output logic [31:0] QA,
|
||||
output logic [31:0] QB
|
||||
);
|
||||
|
||||
// replace "generic64x32RAM" with "TSDN..64X32.." module from your memory vendor
|
||||
generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
|
||||
.AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
|
||||
|
||||
endmodule
|
||||
@ -27,23 +27,21 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module rom1p1r
|
||||
#(
|
||||
//--------------------------------------------------------------------------
|
||||
parameter ADDR_WIDTH = 8,
|
||||
// Addr Width in bits : 2 **ADDR_WIDTH = RAM Depth
|
||||
parameter DATA_WIDTH = 32, // Data Width in bits
|
||||
parameter PRELOAD_ENABLED = 0
|
||||
//----------------------------------------------------------------------
|
||||
) (
|
||||
input logic clk,
|
||||
module rom1p1r #(parameter ADDR_WIDTH = 8,
|
||||
parameter DATA_WIDTH = 32,
|
||||
parameter PRELOAD_ENABLED = 0)
|
||||
(input logic clk,
|
||||
input logic ce,
|
||||
input logic [ADDR_WIDTH-1:0] addr,
|
||||
output logic [DATA_WIDTH-1:0] dout
|
||||
);
|
||||
);
|
||||
|
||||
// Core Memory
|
||||
logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0];
|
||||
if (`USE_SRAM == 1 && DATA_WIDTH == 64 && `XLEN == 64) begin
|
||||
rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout));
|
||||
|
||||
end else begin
|
||||
always @ (posedge clk) begin
|
||||
if(ce) dout <= ROM[addr];
|
||||
end
|
||||
@ -95,6 +93,7 @@ module rom1p1r
|
||||
ROM[41] = 64'h40a7853b4015551b;
|
||||
ROM[42] = 64'h808210a7a02367c9;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule // bytewrite_tdp_ram_rf
|
||||
endmodule
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
// Written: james.stine@okstate.edu 28 January 2023
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: RAM wrapper for instantiating RAM IP
|
||||
// Purpose: ROM wrapper for instantiating ROM IP
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
|
||||
37
pipelined/src/generic/mem/rom1p1r_128x64.sv
Executable file
37
pipelined/src/generic/mem/rom1p1r_128x64.sv
Executable file
@ -0,0 +1,37 @@
|
||||
///////////////////////////////////////////
|
||||
// rom1p1r_128x64.sv
|
||||
//
|
||||
// Written: james.stine@okstate.edu 28 January 2023
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: ROM wrapper for instantiating ROM IP
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module rom1p1r_128x64(
|
||||
input logic CLK,
|
||||
input logic CEB,
|
||||
input logic [6:0] A,
|
||||
output logic [63:0] Q
|
||||
);
|
||||
|
||||
// replace "generic64x128RAM" with "TS3N..64X128.." module from your memory vendor
|
||||
generic64x128ROM romIP (.CLK, .CEB, .A, .Q);
|
||||
|
||||
endmodule
|
||||
@ -100,7 +100,6 @@ package cvw;
|
||||
parameter PLIC_UART_ID = `PLIC_UART_ID;
|
||||
parameter BPRED_SUPPORTED = `BPRED_SUPPORTED;
|
||||
parameter BPRED_TYPE = `BPRED_TYPE;
|
||||
parameter TESTSBP = `TESTSBP;
|
||||
parameter BPRED_SIZE = `BPRED_SIZE;
|
||||
parameter HPTW_WRITES_SUPPORTED = `HPTW_WRITES_SUPPORTED;
|
||||
// parameter = `;
|
||||
|
||||
@ -26,7 +26,8 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
import cvw::*; // global CORE-V-Wally parameters
|
||||
//import cvw::*; // global CORE-V-Wally parameters
|
||||
`include "wally-config.vh"
|
||||
|
||||
module wallypipelinedcore (
|
||||
input logic clk, reset,
|
||||
@ -34,12 +35,12 @@ module wallypipelinedcore (
|
||||
input logic MTimerInt, MExtInt, SExtInt, MSwInt,
|
||||
input logic [63:0] MTIME_CLINT,
|
||||
// Bus Interface
|
||||
input logic [AHBW-1:0] HRDATA,
|
||||
input logic [`AHBW-1:0] HRDATA,
|
||||
input logic HREADY, HRESP,
|
||||
output logic HCLK, HRESETn,
|
||||
output logic [PA_BITS-1:0] HADDR,
|
||||
output logic [AHBW-1:0] HWDATA,
|
||||
output logic [XLEN/8-1:0] HWSTRB,
|
||||
output logic [`PA_BITS-1:0] HADDR,
|
||||
output logic [`AHBW-1:0] HWDATA,
|
||||
output logic [`XLEN/8-1:0] HWSTRB,
|
||||
output logic HWRITE,
|
||||
output logic [2:0] HSIZE,
|
||||
output logic [2:0] HBURST,
|
||||
@ -57,15 +58,15 @@ module wallypipelinedcore (
|
||||
logic IntDivE, W64E;
|
||||
logic CSRReadM, CSRWriteM, PrivilegedM;
|
||||
logic [1:0] AtomicM;
|
||||
logic [XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE;
|
||||
logic [XLEN-1:0] SrcAM;
|
||||
logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE;
|
||||
logic [`XLEN-1:0] SrcAM;
|
||||
logic [2:0] Funct3E;
|
||||
logic [31:0] InstrD;
|
||||
logic [31:0] InstrM;
|
||||
logic [XLEN-1:0] PCFSpill, PCE, PCLinkE;
|
||||
logic [XLEN-1:0] PCM;
|
||||
logic [XLEN-1:0] CSRReadValW, MDUResultW;
|
||||
logic [XLEN-1:0] UnalignedPCNextF, PCNext2F;
|
||||
logic [`XLEN-1:0] PCFSpill, PCE, PCLinkE;
|
||||
logic [`XLEN-1:0] PCM;
|
||||
logic [`XLEN-1:0] CSRReadValW, MDUResultW;
|
||||
logic [`XLEN-1:0] UnalignedPCNextF, PCNext2F;
|
||||
logic [1:0] MemRWM;
|
||||
logic InstrValidM;
|
||||
logic InstrMisalignedFaultM;
|
||||
@ -85,9 +86,9 @@ module wallypipelinedcore (
|
||||
logic [4:0] RdE, RdM, RdW;
|
||||
logic FPUStallD;
|
||||
logic FWriteIntE;
|
||||
logic [FLEN-1:0] FWriteDataM;
|
||||
logic [XLEN-1:0] FIntResM;
|
||||
logic [XLEN-1:0] FCvtIntResW;
|
||||
logic [`FLEN-1:0] FWriteDataM;
|
||||
logic [`XLEN-1:0] FIntResM;
|
||||
logic [`XLEN-1:0] FCvtIntResW;
|
||||
logic FCvtIntW;
|
||||
logic FDivBusyE;
|
||||
logic IllegalFPUInstrM;
|
||||
@ -95,23 +96,23 @@ module wallypipelinedcore (
|
||||
logic FCvtIntStallD;
|
||||
logic FpLoadStoreM;
|
||||
logic [4:0] SetFflagsM;
|
||||
logic [XLEN-1:0] FIntDivResultW;
|
||||
logic [`XLEN-1:0] FIntDivResultW;
|
||||
|
||||
// memory management unit signals
|
||||
logic ITLBWriteF;
|
||||
logic ITLBMissF;
|
||||
logic [XLEN-1:0] SATP_REGW;
|
||||
logic [`XLEN-1:0] SATP_REGW;
|
||||
logic STATUS_MXR, STATUS_SUM, STATUS_MPRV;
|
||||
logic [1:0] STATUS_MPP, STATUS_FS;
|
||||
logic [1:0] PrivilegeModeW;
|
||||
logic [XLEN-1:0] PTE;
|
||||
logic [`XLEN-1:0] PTE;
|
||||
logic [1:0] PageType;
|
||||
logic sfencevmaM, WFIStallM;
|
||||
logic SelHPTW;
|
||||
|
||||
// PMA checker signals
|
||||
var logic [XLEN-1:0] PMPADDR_ARRAY_REGW[PMP_ENTRIES-1:0];
|
||||
var logic [7:0] PMPCFG_ARRAY_REGW[PMP_ENTRIES-1:0];
|
||||
var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0];
|
||||
var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0];
|
||||
|
||||
// IMem stalls
|
||||
logic IFUStallF;
|
||||
@ -119,14 +120,14 @@ module wallypipelinedcore (
|
||||
|
||||
// cpu lsu interface
|
||||
logic [2:0] Funct3M;
|
||||
logic [XLEN-1:0] IEUAdrE;
|
||||
logic [XLEN-1:0] WriteDataM;
|
||||
logic [XLEN-1:0] IEUAdrM;
|
||||
logic [LLEN-1:0] ReadDataW;
|
||||
logic [`XLEN-1:0] IEUAdrE;
|
||||
logic [`XLEN-1:0] WriteDataM;
|
||||
logic [`XLEN-1:0] IEUAdrM;
|
||||
logic [`LLEN-1:0] ReadDataW;
|
||||
logic CommittedM;
|
||||
|
||||
// AHB ifu interface
|
||||
logic [PA_BITS-1:0] IFUHADDR;
|
||||
logic [`PA_BITS-1:0] IFUHADDR;
|
||||
logic [2:0] IFUHBURST;
|
||||
logic [1:0] IFUHTRANS;
|
||||
logic [2:0] IFUHSIZE;
|
||||
@ -134,9 +135,9 @@ module wallypipelinedcore (
|
||||
logic IFUHREADY;
|
||||
|
||||
// AHB LSU interface
|
||||
logic [PA_BITS-1:0] LSUHADDR;
|
||||
logic [XLEN-1:0] LSUHWDATA;
|
||||
logic [XLEN/8-1:0] LSUHWSTRB;
|
||||
logic [`PA_BITS-1:0] LSUHADDR;
|
||||
logic [`XLEN-1:0] LSUHWDATA;
|
||||
logic [`XLEN/8-1:0] LSUHWSTRB;
|
||||
logic LSUHWRITE;
|
||||
logic LSUHREADY;
|
||||
|
||||
@ -199,7 +200,7 @@ module wallypipelinedcore (
|
||||
.SrcAM, // to privilege and fpu
|
||||
.RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
|
||||
// Writeback stage
|
||||
.CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[XLEN-1:0]),
|
||||
.CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]),
|
||||
.InstrValidM, .FCvtIntResW, .FCvtIntW,
|
||||
// hazards
|
||||
.StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
@ -238,7 +239,7 @@ module wallypipelinedcore (
|
||||
.PCFSpill, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
|
||||
.LSUStallM);
|
||||
|
||||
if(BUS_SUPPORTED) begin : ebu
|
||||
if(`BUS_SUPPORTED) begin : ebu
|
||||
ebu ebu(// IFU connections
|
||||
.clk, .reset,
|
||||
// IFU interface
|
||||
@ -276,7 +277,7 @@ module wallypipelinedcore (
|
||||
.FlushD, .FlushE, .FlushM, .FlushW);
|
||||
|
||||
// privileged unit
|
||||
if (ZICSR_SUPPORTED) begin:priv
|
||||
if (`ZICSR_SUPPORTED) begin:priv
|
||||
privileged priv(
|
||||
.clk, .reset,
|
||||
.FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW,
|
||||
@ -309,7 +310,7 @@ module wallypipelinedcore (
|
||||
end
|
||||
|
||||
// multiply/divide unit
|
||||
if (M_SUPPORTED) begin:mdu
|
||||
if (`M_SUPPORTED) begin:mdu
|
||||
mdu mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
|
||||
.ForwardedSrcAE, .ForwardedSrcBE,
|
||||
.Funct3E, .Funct3M, .IntDivE, .W64E,
|
||||
@ -320,12 +321,12 @@ module wallypipelinedcore (
|
||||
end
|
||||
|
||||
// floating point unit
|
||||
if (F_SUPPORTED) begin:fpu
|
||||
if (`F_SUPPORTED) begin:fpu
|
||||
fpu fpu(
|
||||
.clk, .reset,
|
||||
.FRM_REGW, // Rounding mode from CSR
|
||||
.InstrD, // instruction from IFU
|
||||
.ReadDataW(ReadDataW[FLEN-1:0]),// Read data from memory
|
||||
.ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory
|
||||
.ForwardedSrcAE, // Integer input being processed (from IEU)
|
||||
.StallE, .StallM, .StallW, // stall signals from HZU
|
||||
.FlushE, .FlushM, .FlushW, // flush signals from HZU
|
||||
|
||||
@ -26,21 +26,22 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
import cvw::*; // global CORE-V-Wally parameters
|
||||
//import cvw::*; // global CORE-V-Wally parameters
|
||||
`include "wally-config.vh"
|
||||
|
||||
module wallypipelinedsoc (
|
||||
input logic clk,
|
||||
input logic reset_ext, // external asynchronous reset pin
|
||||
output logic reset, // reset synchronized to clk to prevent races on release
|
||||
// AHB Interface
|
||||
input logic [AHBW-1:0] HRDATAEXT,
|
||||
input logic [`AHBW-1:0] HRDATAEXT,
|
||||
input logic HREADYEXT, HRESPEXT,
|
||||
output logic HSELEXT,
|
||||
// outputs to external memory, shared with uncore memory
|
||||
output logic HCLK, HRESETn,
|
||||
output logic [PA_BITS-1:0] HADDR,
|
||||
output logic [AHBW-1:0] HWDATA,
|
||||
output logic [XLEN/8-1:0] HWSTRB,
|
||||
output logic [`PA_BITS-1:0] HADDR,
|
||||
output logic [`AHBW-1:0] HWDATA,
|
||||
output logic [`XLEN/8-1:0] HWSTRB,
|
||||
output logic HWRITE,
|
||||
output logic [2:0] HSIZE,
|
||||
output logic [2:0] HBURST,
|
||||
@ -63,7 +64,7 @@ module wallypipelinedsoc (
|
||||
);
|
||||
|
||||
// Uncore signals
|
||||
logic [AHBW-1:0] HRDATA; // from AHB mux in uncore
|
||||
logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore
|
||||
logic HRESP; // response from AHB
|
||||
logic MTimerInt, MSwInt; // timer and software interrupts from CLINT
|
||||
logic [63:0] MTIME_CLINT; // from CLINT to CSRs
|
||||
@ -80,7 +81,7 @@ module wallypipelinedsoc (
|
||||
);
|
||||
|
||||
// instantiate uncore if a bus interface exists
|
||||
if (BUS_SUPPORTED) begin : uncore
|
||||
if (`BUS_SUPPORTED) begin : uncore
|
||||
uncore uncore(.HCLK, .HRESETn, .TIMECLK,
|
||||
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
|
||||
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,
|
||||
|
||||
@ -548,7 +548,7 @@ module riscvassertions;
|
||||
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2");
|
||||
assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF");
|
||||
assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
|
||||
assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
|
||||
assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported");
|
||||
assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
|
||||
assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
|
||||
assert (`DCACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
|
||||
|
||||
@ -95,47 +95,6 @@ string tvpaths[] = '{
|
||||
"bd_sizeopt_speed/src/wikisort/wikisort"
|
||||
};
|
||||
|
||||
// *** restore CSR tests from Imperas old
|
||||
string extra64i[] = '{
|
||||
`MYIMPERASTEST,
|
||||
"rv64i_m/I/WALLY-ADD",
|
||||
"rv64i_m/I/WALLY-SUB",
|
||||
"rv64i_m/I/WALLY-ADDI",
|
||||
"rv64i_m/I/WALLY-ANDI",
|
||||
"rv64i_m/I/WALLY-ORI",
|
||||
"rv64i_m/I/WALLY-XORI",
|
||||
"rv64i_m/I/WALLY-SLTI",
|
||||
"rv64i_m/I/WALLY-SLTIU",
|
||||
"rv64i_m/I/WALLY-SLLI",
|
||||
"rv64i_m/I/WALLY-SRLI",
|
||||
"rv64i_m/I/WALLY-SRAI",
|
||||
"rv64i_m/I/WALLY-JAL",
|
||||
"rv64i_m/I/WALLY-JALR",
|
||||
"rv64i_m/I/WALLY-STORE",
|
||||
"rv64i_m/I/WALLY-ADDIW",
|
||||
"rv64i_m/I/WALLY-SLLIW",
|
||||
"rv64i_m/I/WALLY-SRLIW",
|
||||
"rv64i_m/I/WALLY-SRAIW",
|
||||
"rv64i_m/I/WALLY-ADDW",
|
||||
"rv64i_m/I/WALLY-SUBW",
|
||||
"rv64i_m/I/WALLY-SLLW",
|
||||
"rv64i_m/I/WALLY-SRLW",
|
||||
"rv64i_m/I/WALLY-SRAW",
|
||||
"rv64i_m/I/WALLY-BEQ",
|
||||
"rv64i_m/I/WALLY-BNE",
|
||||
"rv64i_m/I/WALLY-BLTU",
|
||||
"rv64i_m/I/WALLY-BLT",
|
||||
"rv64i_m/I/WALLY-BGE",
|
||||
"rv64i_m/I/WALLY-BGEU",
|
||||
"rv64i_m/I/WALLY-CSRRW",
|
||||
"rv64i_m/I/WALLY-CSRRS",
|
||||
"rv64i_m/I/WALLY-CSRRC",
|
||||
"rv64i_m/I/WALLY-CSRRWI",
|
||||
"rv64i_m/I/WALLY-CSRRSI",
|
||||
"rv64i_m/I/WALLY-CSRRCI"
|
||||
};
|
||||
|
||||
|
||||
string imperas32f[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv32i_m/F/FSQRT-S-DYN-RDN-01",
|
||||
@ -875,40 +834,17 @@ string imperas32f[] = '{
|
||||
"rv32i_m/I/XORI-01"
|
||||
};
|
||||
|
||||
string imperas32p[] = '{
|
||||
`MYIMPERASTEST,
|
||||
"rv32p/WALLY-MSTATUS",
|
||||
"rv32p/WALLY-MCAUSE",
|
||||
"rv32p/WALLY-SCAUSE",
|
||||
"rv32p/WALLY-MEPC",
|
||||
"rv32p/WALLY-SEPC",
|
||||
"rv32p/WALLY-MTVAL",
|
||||
"rv32p/WALLY-STVAL",
|
||||
"rv32p/WALLY-MARCHID",
|
||||
"rv32p/WALLY-MIMPID",
|
||||
"rv32p/WALLY-MHARTID",
|
||||
"rv32p/WALLY-MVENDORID",
|
||||
"rv32p/WALLY-MTVEC",
|
||||
"rv32p/WALLY-STVEC",
|
||||
"rv32p/WALLY-MIE",
|
||||
"rv32p/WALLY-MEDELEG",
|
||||
"rv32p/WALLY-IP",
|
||||
"rv32p/WALLY-CSR-PERMISSIONS-M",
|
||||
"rv32p/WALLY-CSR-PERMISSIONS-S"
|
||||
};
|
||||
|
||||
string wally64a[] = '{
|
||||
`WALLYTEST,
|
||||
"rv64i_m/privilege/src/WALLY-amo-01.S",
|
||||
"rv64i_m/privilege/src/WALLY-lrsc-01.S",
|
||||
"rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S"
|
||||
"rv64i_m/privilege/src/WALLY-lrsc-01.S"
|
||||
};
|
||||
|
||||
string wally32a[] = '{
|
||||
`WALLYTEST,
|
||||
"rv32i_m/privilege/src/WALLY-amo-01.S",
|
||||
"rv32i_m/privilege/src/WALLY-lrsc-01.S",
|
||||
"rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S"
|
||||
"rv32i_m/privilege/src/WALLY-lrsc-01.S"
|
||||
};
|
||||
|
||||
string arch64priv[] = '{
|
||||
@ -1825,6 +1761,7 @@ string imperas32f[] = '{
|
||||
"rv64i_m/privilege/src/WALLY-status-sie-01.S",
|
||||
"rv64i_m/privilege/src/WALLY-status-tw-01.S",
|
||||
"rv64i_m/privilege/src/WALLY-status-tvm-01.S",
|
||||
"rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S",
|
||||
"rv64i_m/privilege/src/WALLY-stvec-01.S",
|
||||
"rv64i_m/privilege/src/WALLY-trap-01.S",
|
||||
"rv64i_m/privilege/src/WALLY-trap-s-01.S",
|
||||
@ -1912,6 +1849,7 @@ string imperas32f[] = '{
|
||||
"rv32i_m/privilege/src/WALLY-status-sie-01.S",
|
||||
"rv32i_m/privilege/src/WALLY-status-tw-01.S",
|
||||
"rv32i_m/privilege/src/WALLY-status-tvm-01.S",
|
||||
"rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S",
|
||||
"rv32i_m/privilege/src/WALLY-stvec-01.S",
|
||||
"rv32i_m/privilege/src/WALLY-trap-01.S",
|
||||
"rv32i_m/privilege/src/WALLY-trap-s-01.S",
|
||||
|
||||
4
setup.sh
4
setup.sh
@ -13,9 +13,9 @@ echo \$WALLY set to ${WALLY}
|
||||
|
||||
# License servers and commercial CAD tool paths
|
||||
# Must edit these based on your local environment. Ask your sysadmin.
|
||||
export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server
|
||||
export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server
|
||||
export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server
|
||||
export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin # Change this for your path to Questa
|
||||
export QUESTAPATH=/cad/mentor/questa_sim-2022.4_2/questasim/bin # Change this for your path to Questa
|
||||
export SNPSPATH=/cad/synopsys/SYN/bin # Change this for your path to Design Compiler
|
||||
|
||||
# Path to RISC-V Tools
|
||||
|
||||
@ -48,6 +48,10 @@ set cache_read $cache_write
|
||||
lappend search_path ./scripts
|
||||
lappend search_path ./hdl
|
||||
lappend search_path ./mapped
|
||||
set memory /home/jstine/WallyMem/rv64gc/
|
||||
lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db
|
||||
lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db
|
||||
lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db
|
||||
|
||||
# Set up User Information
|
||||
set company "Oklahoma State University"
|
||||
|
||||
@ -44,7 +44,7 @@ default:
|
||||
@echo "Use wallySynth.py to run a concurrent sweep "
|
||||
|
||||
|
||||
DIRS32 = rv32e rv32gc rv32ic rv32i
|
||||
DIRS32 = rv32e rv32gc rv32imc rv32i
|
||||
DIRS64 = rv64i rv64gc
|
||||
DIRS32 = rv32e rv32gc rv32ic rv32i
|
||||
DIRS64 = rv64i rv64gc
|
||||
@ -63,12 +63,18 @@ $(CONFIG):
|
||||
cp -r $(OLDCONFIGDIR)/$(CONFIG) $(CONFIGDIR)/$(CONFIG)_orig
|
||||
sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
|
||||
sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
|
||||
sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
|
||||
sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
|
||||
|
||||
ifneq ($(filter $ $(CONFIG), $(DIRS32)),)
|
||||
sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
|
||||
sed -i "s/DTIM_RANGE.*/DTIM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
|
||||
sed -i "s/IROM_RANGE.*/IROM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
|
||||
sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
|
||||
sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
|
||||
else ifneq ($(filter $ $(CONFIG), $(DIRS64)),)
|
||||
sed -i "s/RAM_RANGE.*/RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
|
||||
sed -i "s/DTIM_RANGE.*/DTIM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
|
||||
sed -i "s/IROM_RANGE.*/IROM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
|
||||
sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
|
||||
sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
|
||||
else
|
||||
$(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64))
|
||||
@echo "Config not in list, RAM_RANGE will be unmodified"
|
||||
@ -106,7 +112,6 @@ endif
|
||||
freqs:
|
||||
@$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e FREQ=$(freq) MAXCORES=1;)
|
||||
|
||||
mkdirecs:
|
||||
mkdirecs:
|
||||
@echo "DC Synthesis"
|
||||
@mkdir -p $(OUTPUTDIR)
|
||||
@ -116,17 +121,12 @@ mkdirecs:
|
||||
@mkdir -p $(OUTPUTDIR)/mapped
|
||||
@mkdir -p $(OUTPUTDIR)/unmapped
|
||||
|
||||
synth: mkdirecs configs rundc clean
|
||||
|
||||
rundc:
|
||||
|
||||
synth: mkdirecs configs rundc clean
|
||||
|
||||
rundc:
|
||||
dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out
|
||||
|
||||
clean:
|
||||
rm -rf $(OUTPUTDIR)/hdl
|
||||
|
||||
clean:
|
||||
rm -rf $(OUTPUTDIR)/hdl
|
||||
|
||||
@ -134,8 +134,8 @@ if {$tech == "sky130"} {
|
||||
|
||||
# Set input/output delay
|
||||
if {$drive == "FLOP"} {
|
||||
set_input_delay 0.1 -max -clock $my_clk $all_in_ex_clk
|
||||
set_output_delay 0.1 -max -clock $my_clk [all_outputs]
|
||||
set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk
|
||||
set_output_delay 0.0 -max -clock $my_clk [all_outputs]
|
||||
} else {
|
||||
set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk
|
||||
set_output_delay 0.0 -max -clock $my_clk [all_outputs]
|
||||
|
||||
@ -17,7 +17,7 @@ def mask(command):
|
||||
if __name__ == '__main__':
|
||||
|
||||
techs = ['sky90', 'tsmc28']
|
||||
allConfigs = ['rv32gc', 'rv32ic', 'rv64gc', 'rv64ic', 'rv32e', 'rv32i', 'rv64i']
|
||||
allConfigs = ['rv32gc', 'rv32imc', 'rv64gc', 'rv64imc', 'rv32e', 'rv32i', 'rv64i']
|
||||
freqVaryPct = [-20, -12, -8, -6, -4, -2, 0, 2, 4, 6, 8, 12, 20]
|
||||
|
||||
pool = Pool()
|
||||
@ -25,7 +25,7 @@ if __name__ == '__main__':
|
||||
parser = argparse.ArgumentParser()
|
||||
|
||||
parser.add_argument("-s", "--freqsweep", type=int, help = "Synthesize wally with target frequencies at given MHz and +/- 2, 4, 6, 8 %%")
|
||||
parser.add_argument("-c", "--configsweep", action='store_true', help = "Synthesize wally with configurations 32e, 32ic, 64ic, 32gc, and 64gc")
|
||||
parser.add_argument("-c", "--configsweep", action='store_true', help = "Synthesize wally with configurations 32e, 32imc, 64ic, 32gc, and 64gc")
|
||||
parser.add_argument("-f", "--featuresweep", action='store_true', help = "Synthesize wally with features turned off progressively to visualize critical path")
|
||||
|
||||
parser.add_argument("-v", "--version", choices=allConfigs, help = "Configuration of wally")
|
||||
@ -47,7 +47,7 @@ if __name__ == '__main__':
|
||||
for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep
|
||||
runSynth(config, mod, tech, freq, maxopt)
|
||||
if args.configsweep:
|
||||
for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32ic', 'rv32e']: #configs
|
||||
for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32imc', 'rv32e']: #configs
|
||||
runSynth(config, mod, tech, freq, maxopt)
|
||||
if args.featuresweep:
|
||||
config = args.version if args.version else 'rv64gc'
|
||||
|
||||
360
wallypipelinedcore.sv
Normal file
360
wallypipelinedcore.sv
Normal file
@ -0,0 +1,360 @@
|
||||
///////////////////////////////////////////
|
||||
// wallypipelinedcore.sv
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 9 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Pipelined RISC-V Processor
|
||||
//
|
||||
// Documentation: RISC-V System on Chip Design (Figure 4.1)
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
import cvw::*; // global CORE-V-Wally parameters
|
||||
|
||||
module wallypipelinedcore (
|
||||
input logic clk, reset,
|
||||
// Privileged
|
||||
input logic MTimerInt, MExtInt, SExtInt, MSwInt,
|
||||
input logic [63:0] MTIME_CLINT,
|
||||
// Bus Interface
|
||||
input logic [AHBW-1:0] HRDATA,
|
||||
input logic HREADY, HRESP,
|
||||
output logic HCLK, HRESETn,
|
||||
output logic [PA_BITS-1:0] HADDR,
|
||||
output logic [AHBW-1:0] HWDATA,
|
||||
output logic [XLEN/8-1:0] HWSTRB,
|
||||
output logic HWRITE,
|
||||
output logic [2:0] HSIZE,
|
||||
output logic [2:0] HBURST,
|
||||
output logic [3:0] HPROT,
|
||||
output logic [1:0] HTRANS,
|
||||
output logic HMASTLOCK
|
||||
);
|
||||
|
||||
logic StallF, StallD, StallE, StallM, StallW;
|
||||
logic FlushD, FlushE, FlushM, FlushW;
|
||||
logic RetM;
|
||||
logic TrapM;
|
||||
|
||||
// signals that must connect through DP
|
||||
logic IntDivE, W64E;
|
||||
logic CSRReadM, CSRWriteM, PrivilegedM;
|
||||
logic [1:0] AtomicM;
|
||||
logic [XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE;
|
||||
logic [XLEN-1:0] SrcAM;
|
||||
logic [2:0] Funct3E;
|
||||
logic [31:0] InstrD;
|
||||
logic [31:0] InstrM;
|
||||
logic [XLEN-1:0] PCFSpill, PCE, PCLinkE;
|
||||
logic [XLEN-1:0] PCM;
|
||||
logic [XLEN-1:0] CSRReadValW, MDUResultW;
|
||||
logic [XLEN-1:0] UnalignedPCNextF, PCNext2F;
|
||||
logic [1:0] MemRWM;
|
||||
logic InstrValidM;
|
||||
logic InstrMisalignedFaultM;
|
||||
logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
|
||||
logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM;
|
||||
logic LoadMisalignedFaultM, LoadAccessFaultM;
|
||||
logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM;
|
||||
logic InvalidateICacheM, FlushDCacheM;
|
||||
logic PCSrcE;
|
||||
logic CSRWriteFenceM;
|
||||
logic DivBusyE;
|
||||
logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
|
||||
logic SquashSCW;
|
||||
|
||||
// floating point unit signals
|
||||
logic [2:0] FRM_REGW;
|
||||
logic [4:0] RdE, RdM, RdW;
|
||||
logic FPUStallD;
|
||||
logic FWriteIntE;
|
||||
logic [FLEN-1:0] FWriteDataM;
|
||||
logic [XLEN-1:0] FIntResM;
|
||||
logic [XLEN-1:0] FCvtIntResW;
|
||||
logic FCvtIntW;
|
||||
logic FDivBusyE;
|
||||
logic IllegalFPUInstrM;
|
||||
logic FRegWriteM;
|
||||
logic FCvtIntStallD;
|
||||
logic FpLoadStoreM;
|
||||
logic [4:0] SetFflagsM;
|
||||
logic [XLEN-1:0] FIntDivResultW;
|
||||
|
||||
// memory management unit signals
|
||||
logic ITLBWriteF;
|
||||
logic ITLBMissF;
|
||||
logic [XLEN-1:0] SATP_REGW;
|
||||
logic STATUS_MXR, STATUS_SUM, STATUS_MPRV;
|
||||
logic [1:0] STATUS_MPP, STATUS_FS;
|
||||
logic [1:0] PrivilegeModeW;
|
||||
logic [XLEN-1:0] PTE;
|
||||
logic [1:0] PageType;
|
||||
logic sfencevmaM, WFIStallM;
|
||||
logic SelHPTW;
|
||||
|
||||
// PMA checker signals
|
||||
var logic [XLEN-1:0] PMPADDR_ARRAY_REGW[PMP_ENTRIES-1:0];
|
||||
var logic [7:0] PMPCFG_ARRAY_REGW[PMP_ENTRIES-1:0];
|
||||
|
||||
// IMem stalls
|
||||
logic IFUStallF;
|
||||
logic LSUStallM;
|
||||
|
||||
// cpu lsu interface
|
||||
logic [2:0] Funct3M;
|
||||
logic [XLEN-1:0] IEUAdrE;
|
||||
logic [XLEN-1:0] WriteDataM;
|
||||
logic [XLEN-1:0] IEUAdrM;
|
||||
logic [LLEN-1:0] ReadDataW;
|
||||
logic CommittedM;
|
||||
|
||||
// AHB ifu interface
|
||||
logic [PA_BITS-1:0] IFUHADDR;
|
||||
logic [2:0] IFUHBURST;
|
||||
logic [1:0] IFUHTRANS;
|
||||
logic [2:0] IFUHSIZE;
|
||||
logic IFUHWRITE;
|
||||
logic IFUHREADY;
|
||||
|
||||
// AHB LSU interface
|
||||
logic [PA_BITS-1:0] LSUHADDR;
|
||||
logic [XLEN-1:0] LSUHWDATA;
|
||||
logic [XLEN/8-1:0] LSUHWSTRB;
|
||||
logic LSUHWRITE;
|
||||
logic LSUHREADY;
|
||||
|
||||
logic BPPredWrongE, BPPredWrongM;
|
||||
logic DirPredictionWrongM;
|
||||
logic BTBPredPCWrongM;
|
||||
logic RASPredPCWrongM;
|
||||
logic PredictionInstrClassWrongM;
|
||||
logic [3:0] InstrClassM;
|
||||
logic InstrAccessFaultF, HPTWInstrAccessFaultM;
|
||||
logic [2:0] LSUHSIZE;
|
||||
logic [2:0] LSUHBURST;
|
||||
logic [1:0] LSUHTRANS;
|
||||
|
||||
logic DCacheMiss;
|
||||
logic DCacheAccess;
|
||||
logic ICacheMiss;
|
||||
logic ICacheAccess;
|
||||
logic BreakpointFaultM, EcallFaultM;
|
||||
logic InstrDAPageFaultF;
|
||||
logic BigEndianM;
|
||||
logic FCvtIntE;
|
||||
logic CommittedF;
|
||||
logic JumpOrTakenBranchM;
|
||||
|
||||
// instruction fetch unit: PC, branch prediction, instruction cache
|
||||
ifu ifu(.clk, .reset,
|
||||
.StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
// Fetch
|
||||
.HRDATA, .PCFSpill, .IFUHADDR, .PCNext2F,
|
||||
.IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
|
||||
.ICacheAccess, .ICacheMiss,
|
||||
// Execute
|
||||
.PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE, .BPPredWrongM,
|
||||
// Mem
|
||||
.CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
|
||||
.InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .JumpOrTakenBranchM,
|
||||
.BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
|
||||
// Faults out
|
||||
.IllegalBaseInstrFaultD, .InstrPageFaultF, .IllegalIEUInstrFaultD, .InstrMisalignedFaultM,
|
||||
// mmu management
|
||||
.PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
|
||||
.STATUS_MPP, .ITLBWriteF, .sfencevmaM, .ITLBMissF,
|
||||
// pmp/pma (inside mmu) signals.
|
||||
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrDAPageFaultF);
|
||||
|
||||
// integer execution unit: integer register file, datapath and controller
|
||||
ieu ieu(.clk, .reset,
|
||||
// Decode Stage interface
|
||||
.InstrD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD,
|
||||
// Execute Stage interface
|
||||
.PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E,
|
||||
.Funct3E, .ForwardedSrcAE, .ForwardedSrcBE,
|
||||
// Memory stage interface
|
||||
.SquashSCW, // from LSU
|
||||
.MemRWM, // read/write control goes to LSU
|
||||
.AtomicM, // atomic control goes to LSU
|
||||
.WriteDataM, // Write data to LSU
|
||||
.Funct3M, // size and signedness to LSU
|
||||
.SrcAM, // to privilege and fpu
|
||||
.RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
|
||||
// Writeback stage
|
||||
.CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[XLEN-1:0]),
|
||||
.InstrValidM, .FCvtIntResW, .FCvtIntW,
|
||||
// hazards
|
||||
.StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, .PCSrcE,
|
||||
.CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .StoreStallD);
|
||||
|
||||
lsu lsu(
|
||||
.clk, .reset, .StallM, .FlushM, .StallW, .FlushW,
|
||||
// CPU interface
|
||||
.MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .AtomicM,
|
||||
.CommittedM, .DCacheMiss, .DCacheAccess, .SquashSCW,
|
||||
.FpLoadStoreM, .FWriteDataM, .IEUAdrE, .IEUAdrM, .WriteDataM,
|
||||
.ReadDataW, .FlushDCacheM,
|
||||
// connected to ahb (all stay the same)
|
||||
.LSUHADDR, .HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE,
|
||||
.LSUHBURST, .LSUHTRANS, .LSUHWRITE, .LSUHREADY,
|
||||
// connect to csr or privilege and stay the same.
|
||||
.PrivilegeModeW, .BigEndianM, // connects to csr
|
||||
.PMPCFG_ARRAY_REGW, // connects to csr
|
||||
.PMPADDR_ARRAY_REGW, // connects to csr
|
||||
// hptw keep i/o
|
||||
.SATP_REGW, // from csr
|
||||
.STATUS_MXR, // from csr
|
||||
.STATUS_SUM, // from csr
|
||||
.STATUS_MPRV, // from csr
|
||||
.STATUS_MPP, // from csr
|
||||
.sfencevmaM, // connects to privilege
|
||||
.LoadPageFaultM, // connects to privilege
|
||||
.StoreAmoPageFaultM, // connects to privilege
|
||||
.LoadMisalignedFaultM, // connects to privilege
|
||||
.LoadAccessFaultM, // connects to privilege
|
||||
.HPTWInstrAccessFaultM, // connects to privilege
|
||||
.StoreAmoMisalignedFaultM, // connects to privilege
|
||||
.StoreAmoAccessFaultM, // connects to privilege
|
||||
.InstrDAPageFaultF,
|
||||
.PCFSpill, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
|
||||
.LSUStallM);
|
||||
|
||||
if(BUS_SUPPORTED) begin : ebu
|
||||
ebu ebu(// IFU connections
|
||||
.clk, .reset,
|
||||
// IFU interface
|
||||
.IFUHADDR,
|
||||
.IFUHBURST,
|
||||
.IFUHTRANS,
|
||||
.IFUHREADY,
|
||||
.IFUHSIZE,
|
||||
// LSU interface
|
||||
.LSUHADDR,
|
||||
.LSUHWDATA,
|
||||
.LSUHWSTRB,
|
||||
.LSUHSIZE,
|
||||
.LSUHBURST,
|
||||
.LSUHTRANS,
|
||||
.LSUHWRITE,
|
||||
.LSUHREADY,
|
||||
// BUS interface
|
||||
.HREADY, .HRESP, .HCLK, .HRESETn,
|
||||
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
|
||||
.HPROT, .HTRANS, .HMASTLOCK);
|
||||
end
|
||||
|
||||
// global stall and flush control
|
||||
hazard hzu(
|
||||
.BPPredWrongE, .CSRWriteFenceM, .RetM, .TrapM,
|
||||
.LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD,
|
||||
.LSUStallM, .IFUStallF,
|
||||
.FCvtIntStallD, .FPUStallD,
|
||||
.DivBusyE, .FDivBusyE,
|
||||
.EcallFaultM, .BreakpointFaultM,
|
||||
.WFIStallM,
|
||||
// Stall & flush outputs
|
||||
.StallF, .StallD, .StallE, .StallM, .StallW,
|
||||
.FlushD, .FlushE, .FlushM, .FlushW);
|
||||
|
||||
// privileged unit
|
||||
if (ZICSR_SUPPORTED) begin:priv
|
||||
privileged priv(
|
||||
.clk, .reset,
|
||||
.FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW,
|
||||
.CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PCNext2F,
|
||||
.InstrM, .CSRReadValW, .UnalignedPCNextF,
|
||||
.RetM, .TrapM, .sfencevmaM,
|
||||
.InstrValidM, .CommittedM, .CommittedF,
|
||||
.FRegWriteM, .LoadStallD,
|
||||
.DirPredictionWrongM, .BTBPredPCWrongM, .BPPredWrongM,
|
||||
.RASPredPCWrongM, .PredictionInstrClassWrongM,
|
||||
.InstrClassM, .JumpOrTakenBranchM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
|
||||
.InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
|
||||
.InstrMisalignedFaultM, .IllegalIEUInstrFaultD,
|
||||
.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
|
||||
.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
|
||||
.MTIME_CLINT, .IEUAdrM, .SetFflagsM,
|
||||
.InstrAccessFaultF, .HPTWInstrAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW,
|
||||
.IllegalFPUInstrM, .PrivilegeModeW, .SATP_REGW,
|
||||
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
|
||||
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
|
||||
.FRM_REGW,.BreakpointFaultM, .EcallFaultM, .WFIStallM, .BigEndianM);
|
||||
end else begin
|
||||
assign CSRReadValW = 0;
|
||||
assign UnalignedPCNextF = PCNext2F;
|
||||
assign RetM = 0;
|
||||
assign TrapM = 0;
|
||||
assign WFIStallM = 0;
|
||||
assign sfencevmaM = 0;
|
||||
assign BigEndianM = 0;
|
||||
end
|
||||
|
||||
// multiply/divide unit
|
||||
if (M_SUPPORTED) begin:mdu
|
||||
mdu mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
|
||||
.ForwardedSrcAE, .ForwardedSrcBE,
|
||||
.Funct3E, .Funct3M, .IntDivE, .W64E,
|
||||
.MDUResultW, .DivBusyE);
|
||||
end else begin // no M instructions supported
|
||||
assign MDUResultW = 0;
|
||||
assign DivBusyE = 0;
|
||||
end
|
||||
|
||||
// floating point unit
|
||||
if (F_SUPPORTED) begin:fpu
|
||||
fpu fpu(
|
||||
.clk, .reset,
|
||||
.FRM_REGW, // Rounding mode from CSR
|
||||
.InstrD, // instruction from IFU
|
||||
.ReadDataW(ReadDataW[FLEN-1:0]),// Read data from memory
|
||||
.ForwardedSrcAE, // Integer input being processed (from IEU)
|
||||
.StallE, .StallM, .StallW, // stall signals from HZU
|
||||
.FlushE, .FlushM, .FlushW, // flush signals from HZU
|
||||
.RdE, .RdM, .RdW, // which FP register to write to (from IEU)
|
||||
.STATUS_FS, // is floating-point enabled?
|
||||
.FRegWriteM, // FP register write enable
|
||||
.FpLoadStoreM,
|
||||
.ForwardedSrcBE, // Integer input for intdiv
|
||||
.Funct3E, .Funct3M, .IntDivE, .W64E, // Integer flags and functions
|
||||
.FPUStallD, // Stall the decode stage
|
||||
.FWriteIntE, .FCvtIntE, // integer register write enable, conversion operation
|
||||
.FWriteDataM, // Data to be written to memory
|
||||
.FIntResM, // data to be written to integer register
|
||||
.FCvtIntResW, // fp -> int conversion result to be stored in int register
|
||||
.FCvtIntW, // fpu result selection
|
||||
.FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
|
||||
.IllegalFPUInstrM, // Is the instruction an illegal fpu instruction
|
||||
.SetFflagsM, // FPU flags (to privileged unit)
|
||||
.FIntDivResultW);
|
||||
end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
|
||||
assign FPUStallD = 0;
|
||||
assign FWriteIntE = 0;
|
||||
assign FCvtIntE = 0;
|
||||
assign FIntResM = 0;
|
||||
assign FCvtIntW = 0;
|
||||
assign FDivBusyE = 0;
|
||||
assign IllegalFPUInstrM = 1;
|
||||
assign SetFflagsM = 0;
|
||||
assign FpLoadStoreM = 0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
92
wallypipelinedsoc.sv
Normal file
92
wallypipelinedsoc.sv
Normal file
@ -0,0 +1,92 @@
|
||||
///////////////////////////////////////////
|
||||
// wally-pipelinedsoc.sv
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 6 November 2020
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: System on chip including pipelined processor and uncore memories/peripherals
|
||||
//
|
||||
// Documentation: RISC-V System on Chip Design (Figure 6.20)
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
import cvw::*; // global CORE-V-Wally parameters
|
||||
|
||||
module wallypipelinedsoc (
|
||||
input logic clk,
|
||||
input logic reset_ext, // external asynchronous reset pin
|
||||
output logic reset, // reset synchronized to clk to prevent races on release
|
||||
// AHB Interface
|
||||
input logic [AHBW-1:0] HRDATAEXT,
|
||||
input logic HREADYEXT, HRESPEXT,
|
||||
output logic HSELEXT,
|
||||
// outputs to external memory, shared with uncore memory
|
||||
output logic HCLK, HRESETn,
|
||||
output logic [PA_BITS-1:0] HADDR,
|
||||
output logic [AHBW-1:0] HWDATA,
|
||||
output logic [XLEN/8-1:0] HWSTRB,
|
||||
output logic HWRITE,
|
||||
output logic [2:0] HSIZE,
|
||||
output logic [2:0] HBURST,
|
||||
output logic [3:0] HPROT,
|
||||
output logic [1:0] HTRANS,
|
||||
output logic HMASTLOCK,
|
||||
output logic HREADY,
|
||||
// I/O Interface
|
||||
input logic TIMECLK, // optional for CLINT MTIME counter
|
||||
input logic [31:0] GPIOPinsIn, // inputs from GPIO
|
||||
output logic [31:0] GPIOPinsOut, // output values for GPIO
|
||||
output logic [31:0] GPIOPinsEn, // output enables for GPIO
|
||||
input logic UARTSin, // UART serial data input
|
||||
output logic UARTSout, // UART serial data output
|
||||
input logic SDCCmdIn, // SDC Command input
|
||||
output logic SDCCmdOut, // SDC Command output
|
||||
output logic SDCCmdOE, // SDC Command output enable
|
||||
input logic [3:0] SDCDatIn, // SDC data input
|
||||
output logic SDCCLK // SDC clock
|
||||
);
|
||||
|
||||
// Uncore signals
|
||||
logic [AHBW-1:0] HRDATA; // from AHB mux in uncore
|
||||
logic HRESP; // response from AHB
|
||||
logic MTimerInt, MSwInt; // timer and software interrupts from CLINT
|
||||
logic [63:0] MTIME_CLINT; // from CLINT to CSRs
|
||||
logic MExtInt,SExtInt; // from PLIC
|
||||
|
||||
// synchronize reset to SOC clock domain
|
||||
synchronizer resetsync(.clk, .d(reset_ext), .q(reset));
|
||||
|
||||
// instantiate processor and internal memories
|
||||
wallypipelinedcore core(.clk, .reset,
|
||||
.MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT,
|
||||
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB,
|
||||
.HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK
|
||||
);
|
||||
|
||||
// instantiate uncore if a bus interface exists
|
||||
if (BUS_SUPPORTED) begin : uncore
|
||||
uncore uncore(.HCLK, .HRESETn, .TIMECLK,
|
||||
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
|
||||
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,
|
||||
.MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin,
|
||||
.UARTSout, .MTIME_CLINT,
|
||||
.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK);
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue
Block a user