forked from Github_Repos/cvw
fixed various bugs
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@ -23,7 +23,14 @@ module tb;
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wire inexact;
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wire inexact;
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integer fp;
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integer fp;
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reg nan;
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reg wnan;
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reg xnan;
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reg ynan;
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reg znan;
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reg ansnan;
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reg [105:0] s; // partial product 2
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reg [51:0] xnorm;
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reg [51:0] ynorm;
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localparam period = 20;
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localparam period = 20;
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fmac UUT(.xrf(xrf), .y(y), .zrf(zrf), .rn(rn), .rz(rz), .rp(rp), .rm(rm),
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fmac UUT(.xrf(xrf), .y(y), .zrf(zrf), .rn(rn), .rz(rz), .rp(rp), .rm(rm),
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@ -33,4 +40,4 @@ fmac UUT(.xrf(xrf), .y(y), .zrf(zrf), .rn(rn), .rz(rz), .rp(rp), .rm(rm),
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initial
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initial
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begin
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begin
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fp = $fopen("/home/kparry/code/FMAC/tbgen/results.dat","w");
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fp = $fopen("/home/kparry/riscv-wally/wally-pipelined/src/fpu/FMA/tbgen/results.dat","w");
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