forked from Github_Repos/cvw
testbench code visual improvements
This commit is contained in:
parent
38349e6a4f
commit
0862688168
@ -169,7 +169,7 @@ module testbench;
|
|||||||
logic InitializingMemories;
|
logic InitializingMemories;
|
||||||
integer ResetCount, ResetThreshold;
|
integer ResetCount, ResetThreshold;
|
||||||
logic InReset;
|
logic InReset;
|
||||||
logic Begin;
|
logic BeginSample;
|
||||||
|
|
||||||
// instantiate device to be tested
|
// instantiate device to be tested
|
||||||
assign GPIOIN = 0;
|
assign GPIOIN = 0;
|
||||||
@ -225,7 +225,8 @@ module testbench;
|
|||||||
totalerrors = 0;
|
totalerrors = 0;
|
||||||
testadr = 0;
|
testadr = 0;
|
||||||
testadrNoBase = 0;
|
testadrNoBase = 0;
|
||||||
// riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests and tests[0] == "2" refers to WallyRiscvArchTests
|
// riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests
|
||||||
|
// and tests[0] == "2" refers to WallyRiscvArchTests
|
||||||
riscofTest = tests[0] == "1" | tests[0] == "2";
|
riscofTest = tests[0] == "1" | tests[0] == "2";
|
||||||
// fill memory with defined values to reduce Xs in simulation
|
// fill memory with defined values to reduce Xs in simulation
|
||||||
// Quick note the memory will need to be initialized. The C library does not
|
// Quick note the memory will need to be initialized. The C library does not
|
||||||
@ -265,8 +266,9 @@ module testbench;
|
|||||||
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
|
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
|
||||||
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
|
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
|
||||||
end
|
end
|
||||||
// declare memory labels that interest us, the updateProgramAddrLabelArray task will find the addr of each label and fill the array
|
// declare memory labels that interest us, the updateProgramAddrLabelArray task will find
|
||||||
// to expand, add more elements to this array and initialize them to zero (also initilaize them to zero at the start of the next test)
|
// the addr of each label and fill the array. To expand, add more elements to this array
|
||||||
|
// and initialize them to zero (also initilaize them to zero at the start of the next test)
|
||||||
if(!`FPGA) begin
|
if(!`FPGA) begin
|
||||||
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
|
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
|
||||||
$display("Read memfile %s", memfilename);
|
$display("Read memfile %s", memfilename);
|
||||||
@ -311,8 +313,10 @@ module testbench;
|
|||||||
#600; // give time for instructions in pipeline to finish
|
#600; // give time for instructions in pipeline to finish
|
||||||
if (TEST == "embench") begin
|
if (TEST == "embench") begin
|
||||||
// Writes contents of begin_signature to .sim.output file
|
// Writes contents of begin_signature to .sim.output file
|
||||||
// this contains instret and cycles for start and end of test run, used by embench python speed script to calculate embench speed score
|
// this contains instret and cycles for start and end of test run, used by embench
|
||||||
// also begin_signature contains the results of the self checking mechanism, which will be read by the python script for error checking
|
// python speed script to calculate embench speed score.
|
||||||
|
// also, begin_signature contains the results of the self checking mechanism,
|
||||||
|
// which will be read by the python script for error checking
|
||||||
$display("Embench Benchmark: %s is done.", tests[test]);
|
$display("Embench Benchmark: %s is done.", tests[test]);
|
||||||
if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
|
if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
|
||||||
else outputfile = {pathname, tests[test], ".sim.output"};
|
else outputfile = {pathname, tests[test], ".sim.output"};
|
||||||
@ -366,15 +370,14 @@ module testbench;
|
|||||||
errors = errors+1;
|
errors = errors+1;
|
||||||
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
|
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
|
||||||
tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
|
tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
|
||||||
$stop;//***debug
|
$stop; //***debug
|
||||||
end
|
end
|
||||||
i = i + 1;
|
i = i + 1;
|
||||||
end
|
end
|
||||||
/* verilator lint_on INFINITELOOP */
|
/* verilator lint_on INFINITELOOP */
|
||||||
if (errors == 0) begin
|
if (errors == 0) begin
|
||||||
$display("%s succeeded. Brilliant!!!", tests[test]);
|
$display("%s succeeded. Brilliant!!!", tests[test]);
|
||||||
end
|
end else begin
|
||||||
else begin
|
|
||||||
$display("%s failed with %d errors. :(", tests[test], errors);
|
$display("%s failed with %d errors. :(", tests[test], errors);
|
||||||
totalerrors = totalerrors+1;
|
totalerrors = totalerrors+1;
|
||||||
end
|
end
|
||||||
@ -385,8 +388,7 @@ module testbench;
|
|||||||
if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
|
if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
|
||||||
else $display("FAIL: %d test programs had errors", totalerrors);
|
else $display("FAIL: %d test programs had errors", totalerrors);
|
||||||
$stop;
|
$stop;
|
||||||
end
|
end else begin
|
||||||
else begin
|
|
||||||
InitializingMemories = 1;
|
InitializingMemories = 1;
|
||||||
// If there are still additional tests to run, read in information for the next test
|
// If there are still additional tests to run, read in information for the next test
|
||||||
//pathname = tvpaths[tests[0]];
|
//pathname = tvpaths[tests[0]];
|
||||||
@ -480,10 +482,9 @@ module testbench;
|
|||||||
assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
|
assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
|
||||||
|
|
||||||
flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed);
|
flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed);
|
||||||
assign Begin = StartSampleFirst & ~BeginDelayed;
|
assign BeginSample = StartSampleFirst & ~BeginDelayed;
|
||||||
|
|
||||||
end
|
end
|
||||||
|
|
||||||
always @(negedge clk) begin
|
always @(negedge clk) begin
|
||||||
if(StartSample) begin
|
if(StartSample) begin
|
||||||
for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin
|
for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin
|
||||||
@ -552,7 +553,7 @@ module testbench;
|
|||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
||||||
if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger
|
if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger
|
||||||
@ -581,7 +582,7 @@ end
|
|||||||
dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M";
|
dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M";
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
if(resetEdge) $fwrite(file, "TRAIN\n");
|
if(resetEdge) $fwrite(file, "TRAIN\n");
|
||||||
if(Begin) $fwrite(file, "BEGIN %s\n", memfilename);
|
if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
|
||||||
if(Enable) begin // only log i cache reads
|
if(Enable) begin // only log i cache reads
|
||||||
$fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString);
|
$fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString);
|
||||||
end
|
end
|
||||||
@ -621,7 +622,7 @@ end
|
|||||||
end
|
end
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
if(resetEdge) $fwrite(file, "TRAIN\n");
|
if(resetEdge) $fwrite(file, "TRAIN\n");
|
||||||
if(Begin) $fwrite(file, "BEGIN %s\n", memfilename);
|
if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
|
||||||
if(Enabled) begin
|
if(Enabled) begin
|
||||||
$fwrite(file, "%h %s %s\n", dut.core.lsu.PAdrM, AccessTypeString, HitMissString);
|
$fwrite(file, "%h %s %s\n", dut.core.lsu.PAdrM, AccessTypeString, HitMissString);
|
||||||
end
|
end
|
||||||
@ -656,7 +657,7 @@ end
|
|||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
// check for hange up.
|
// check for hang up.
|
||||||
logic [`XLEN-1:0] OldPCW;
|
logic [`XLEN-1:0] OldPCW;
|
||||||
integer WatchDogTimerCount;
|
integer WatchDogTimerCount;
|
||||||
localparam WatchDogTimerThreshold = 1000000;
|
localparam WatchDogTimerThreshold = 1000000;
|
||||||
@ -806,8 +807,7 @@ task automatic updateProgramAddrLabelArray;
|
|||||||
integer returncode;
|
integer returncode;
|
||||||
returncode = $fscanf(ProgramLabelMapFP, "%s\n", label);
|
returncode = $fscanf(ProgramLabelMapFP, "%s\n", label);
|
||||||
returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr);
|
returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr);
|
||||||
if (ProgramAddrLabelArray.exists(label))
|
if (ProgramAddrLabelArray.exists(label)) ProgramAddrLabelArray[label] = adrstr.atohex();
|
||||||
ProgramAddrLabelArray[label] = adrstr.atohex();
|
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
$fclose(ProgramLabelMapFP);
|
$fclose(ProgramLabelMapFP);
|
||||||
|
Loading…
Reference in New Issue
Block a user