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Touched up TLB D and A bit checks

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This commit is contained in:
David Harris 2021-07-04 18:17:09 -04:00
parent b0f199b574
commit 07f2064c19
2 changed files with 7 additions and 4 deletions
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2
wally-pipelined/src/ebu/ahblite.sv
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@ -219,8 +219,6 @@ module ahblite (
generate generate
if (`A_SUPPORTED) begin if (`A_SUPPORTED) begin
logic [`XLEN-1:0] AMOResult; logic [`XLEN-1:0] AMOResult;
// amoalu amoalu(.a(HRDATA), .b(WriteDataM), .funct(Funct7M), .width(MemSizeM),
// .result(AMOResult));
amoalu amoalu(.srca(HRDATAW), .srcb(WriteDataM), .funct(Funct7M), .width(MemSizeM), amoalu amoalu(.srca(HRDATAW), .srcb(WriteDataM), .funct(Funct7M), .width(MemSizeM),
.result(AMOResult)); .result(AMOResult));
mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, AtomicMaskedM[1], WriteData); mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, AtomicMaskedM[1], WriteData);

9
wally-pipelined/src/mmu/tlb.sv
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@ -111,6 +111,7 @@ module tlb #(parameter TLB_ENTRIES = 8,
logic [1:0] HitPageType; logic [1:0] HitPageType;
logic CAMHit; logic CAMHit;
logic [`ASID_BITS-1:0] ASID; logic [`ASID_BITS-1:0] ASID;
logic DAFault;
// Grab the sv mode from SATP and determine whether translation should occur // Grab the sv mode from SATP and determine whether translation should occur
assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
@ -165,7 +166,9 @@ module tlb #(parameter TLB_ENTRIES = 8,
// only execute non-user mode pages. // only execute non-user mode pages.
assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) && ~PTE_U) || assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) && ~PTE_U) ||
((EffectivePrivilegeMode == `S_MODE) && PTE_U); ((EffectivePrivilegeMode == `S_MODE) && PTE_U);
assign TLBPageFault = Translate && TLBHit && (ImproperPrivilege || ~PTE_X); // fault for software handling if access bit is off
assign DAFault = ~PTE_A;
assign TLBPageFault = Translate && TLBHit && (ImproperPrivilege || ~PTE_X || DAFault);
end else begin end else begin
logic ImproperPrivilege, InvalidRead, InvalidWrite; logic ImproperPrivilege, InvalidRead, InvalidWrite;
@ -180,7 +183,9 @@ module tlb #(parameter TLB_ENTRIES = 8,
// Check for write error. Writes are invalid when the page's write bit is // Check for write error. Writes are invalid when the page's write bit is
// low. // low.
assign InvalidWrite = WriteAccess && ~PTE_W; assign InvalidWrite = WriteAccess && ~PTE_W;
assign TLBPageFault = Translate && TLBHit && (ImproperPrivilege || InvalidRead || InvalidWrite); // Fault for software handling if access bit is off or writing a page with dirty bit off
assign DAFault = ~PTE_A | WriteAccess & ~PTE_D;
assign TLBPageFault = Translate && TLBHit && (ImproperPrivilege || InvalidRead || InvalidWrite || DAFault);
end end
endgenerate endgenerate