Added mux for integer special case, renamed signals to match pipelined stage

pipelined/src/fpu/fdivsqrt/fdivsqrt.sv

@@ -64,22 +64,23 @@ module fdivsqrt(
   logic [`DIVb:0]   FirstU, FirstUM;
   logic [`DIVb+1:0] FirstC;
   logic Firstun;
-  logic WZero;
+  logic WZeroM, AZeroE, BZeroE;
   logic SpecialCaseM;
   logic [`DIVBLEN:0] n, m;
-  logic OTFCSwap, ALTBM, BZero, As;
+  logic OTFCSwap, ALTBM, As;
   logic DivStartE;
 
   fdivsqrtpreproc fdivsqrtpreproc(
     .clk, .IFDivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), 
     .Sqrt(SqrtE), .Ym(YmE), .XZero(XZeroE), .X, .DPreproc, 
-    .n, .m, .OTFCSwap, .ALTBM, .BZero, .As,
+    .n, .m, .OTFCSwap, .ALTBM, .AZeroE, .BZeroE, .As,
     .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E);
   fdivsqrtfsm fdivsqrtfsm(
-    .clk, .reset, .FmtE, .XsE, .SqrtE, 
+    .clk, .reset, .FmtE, .XsE, .SqrtE,
-    .FDivBusyE, .FDivStartE, .IDivStartE, .IFDivStartE, .FDivDoneE, .StallE, .StallM, .FlushE, /*.DivDone, */ .XZeroE, .YZeroE, 
+    .FDivBusyE, .FDivStartE, .IDivStartE, .IFDivStartE, .FDivDoneE, .StallE, .StallM, .FlushE, /*.DivDone, */ 
+    .XZeroE, .YZeroE, .AZeroE, .BZeroE,
     .XNaNE, .YNaNE, .MDUE, .n,
-    .XInfE, .YInfE, .WZero, .SpecialCaseM);
+    .XInfE, .YInfE, .WZeroM, .SpecialCaseM);
   fdivsqrtiter fdivsqrtiter(
     .clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .MDUE, .SqrtE, // .SqrtM,
     .X,.DPreproc, .FirstWS(WS), .FirstWC(WC),
@@ -88,6 +89,6 @@ module fdivsqrt(
   fdivsqrtpostproc fdivsqrtpostproc(
     .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, 
     .SqrtM, .SpecialCaseM, .RemOpM(Funct3M[1]), .ForwardedSrcAE,
-    .n, .ALTBM, .m, .BZero, .As,
+    .n, .ALTBM, .m, .BZeroE, .As,
-    .QmM, .WZero, .DivSM, .FPIntDivResultM);
+    .QmM, .WZeroM, .DivSM, .FPIntDivResultM);
 endmodule

pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv

@@ -36,6 +36,7 @@ module fdivsqrtfsm(
   input  logic [`FMTBITS-1:0] FmtE,
   input  logic XInfE, YInfE, 
   input  logic XZeroE, YZeroE, 
+  input  logic AZeroE, BZeroE,
   input  logic XNaNE, YNaNE, 
   input  logic FDivStartE, IDivStartE,
   input  logic XsE,
@@ -43,7 +44,7 @@ module fdivsqrtfsm(
   input  logic StallE,
   input  logic StallM,
   input  logic FlushE,
-  input  logic WZero,
+  input  logic WZeroM,
   input  logic MDUE,
   input  logic [`DIVBLEN:0] n,
   output logic IFDivStartE,
@@ -56,7 +57,7 @@ module fdivsqrtfsm(
 
   logic [`DURLEN-1:0] step;
   logic [`DURLEN-1:0] cycles;
-  logic SpecialCaseE;
+  logic SpecialCaseE, FSpecialCaseE, ISpecialCaseE;
 
   // FDivStartE and IDivStartE come from fctrl, reflecitng the start of floating-point and possibly integer division
   assign IFDivStartE = (FDivStartE | (IDivStartE & `IDIV_ON_FPU)) & (state == IDLE) & ~StallM;
@@ -64,7 +65,9 @@ module fdivsqrtfsm(
   assign FDivBusyE = (state == BUSY) | IFDivStartE; 
 
   // terminate immediately on special cases
-  assign SpecialCaseE = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE);
+  assign FSpecialCaseE = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE);
+  assign ISpecialCaseE = AZeroE | BZeroE;
+  assign SpecialCaseE  = MDUE ? ISpecialCaseE : FSpecialCaseE;
   flopenr #(1) SpecialCaseReg(clk, reset, ~StallM, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
 
 // DIVN = `NF+3
@@ -116,7 +119,7 @@ module fdivsqrtfsm(
       end else if (state == BUSY) begin
           if (step == 1)  state <= #1 DONE;
           step <= step - 1;
-      end else if ((state == DONE) | (WZero & (state == BUSY))) begin
+      end else if ((state == DONE) | (WZeroM & (state == BUSY))) begin
         if (StallM) state <= #1 DONE;
         else        state <= #1 IDLE;
       end 

pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv

@@ -31,20 +31,20 @@
 `include "wally-config.vh"
 
 module fdivsqrtpostproc(
-  input  logic [`DIVb+3:0] WS, WC,
+  input  logic [`DIVb+3:0]  WS, WC,
-  input  logic [`DIVb-1:0] D, 
+  input  logic [`DIVb-1:0]  D, 
-  input  logic [`DIVb:0]   FirstU, FirstUM, 
+  input  logic [`DIVb:0]    FirstU, FirstUM, 
-  input  logic [`DIVb+1:0] FirstC,
+  input  logic [`DIVb+1:0]  FirstC,
-  input  logic Firstun,
+  input  logic              Firstun,
-  input  logic SqrtM,
+  input  logic              SqrtM,
-  input  logic SpecialCaseM,
+  input  logic              SpecialCaseM,
-	input  logic [`XLEN-1:0] ForwardedSrcAE,
+	input  logic [`XLEN-1:0]  ForwardedSrcAE,
-  input  logic RemOpM, ALTBM, BZero, As,
+  input  logic              RemOpM, ALTBM, BZeroE, As,
   input  logic [`DIVBLEN:0] n, m,
   output logic [`DIVb:0]    QmM, 
-  output logic WZero,
+  output logic              WZeroM,
-  output logic DivSM,
+  output logic              DivSM,
-  output logic [`XLEN-1:0] FPIntDivResultM
+  output logic [`XLEN-1:0]  FPIntDivResultM
 );
   
   logic [`DIVb+3:0] W, Sum, RemDM;
@@ -69,11 +69,11 @@ module fdivsqrtpostproc(
     assign FZero = SqrtM ? {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
     csa #(`DIVb+4) fadd(WS, WC, FZero, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
     aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0);
-    assign WZero = weq0|(wfeq0 & Firstun);
+    assign WZeroM = weq0|(wfeq0 & Firstun);
   end else begin
-    assign WZero = weq0;
+    assign WZeroM = weq0;
   end 
-  assign DivSM = ~WZero & ~(SpecialCaseM & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide
+  assign DivSM = ~WZeroM & ~(SpecialCaseM & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide
 
   // Determine if sticky bit is negative
   assign Sum = WC + WS;
@@ -109,10 +109,10 @@ module fdivsqrtpostproc(
     if(ALTBM) begin
       IntQuotM = '0;
       IntRemM  = {{(`DIVb-`XLEN+4){1'b0}}, ForwardedSrcAE};
-    end else if (BZero) begin
+    end else if (BZeroE) begin
       IntQuotM = '1;
       IntRemM  = {{(`DIVb-`XLEN+4){1'b0}}, ForwardedSrcAE};
-    end else if (WZero) begin
+    end else if (WZeroM) begin
       if (weq0) begin
         IntQuotM = FirstU;
         IntRemM  = '0;

pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -42,7 +42,7 @@ module fdivsqrtpreproc (
 	input  logic [2:0] 	Funct3E, Funct3M,
 	input  logic MDUE, W64E,
   output logic [`DIVBLEN:0] n, m,
-  output logic OTFCSwap, ALTBM, BZero, As,
+  output logic OTFCSwap, ALTBM, As, AZeroE, BZeroE,
   output logic [`NE+1:0] QeM,
   output logic [`DIVb+3:0] X,
   output logic [`DIVb-1:0] DPreproc
@@ -75,7 +75,8 @@ module fdivsqrtpreproc (
   
   assign PosA = As ? -A64 : A64;
   assign PosB = Bs ? -B64 : B64;
-  assign BZero = ~(|ForwardedSrcBE);
+  assign AZeroE = ~(|ForwardedSrcAE);
+  assign BZeroE = ~(|ForwardedSrcBE);
 
   assign IFNormLenX = MDUE ? {PosA, {(`DIVb-`XLEN){1'b0}}} : {Xm, {(`DIVb-`NF-1){1'b0}}};
   assign IFNormLenD = MDUE ? {PosB, {(`DIVb-`XLEN){1'b0}}} : {Ym, {(`DIVb-`NF-1){1'b0}}};