added high bit registers to CSR permission tests

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-CSR-permission-s-01.reference_output

@@ -1,4 +1,103 @@
 0000000b # Test 5.2.3.6: ecall from going to S mode from M mode
+00000002 # S mode write to pmpcfg1 with illegal instruction
+00000002 # S mode read from pmpcfg1 with illegal instruction
+00000bad
+00000002 # S mode write to pmpcfg3 with illegal instruction
+00000002 # S mode read from pmpcfg3 with illegal instruction
+00000bad
+00000002 # S mode write to mcycleh with illegal instruction
+00000002 # S mode read from mcycleh with illegal instruction
+00000bad
+00000002 # S mode write to minstreth with illegal instruction
+00000002 # S mode read from minstreth with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter3h with illegal instruction
+00000002 # S mode read from mhpmcounter3h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter4h with illegal instruction
+00000002 # S mode read from mhpmcounter4h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter5h with illegal instruction
+00000002 # S mode read from mhpmcounter5h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter6h with illegal instruction
+00000002 # S mode read from mhpmcounter6h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter7h with illegal instruction
+00000002 # S mode read from mhpmcounter7h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter8h with illegal instruction
+00000002 # S mode read from mhpmcounter8h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter9h with illegal instruction
+00000002 # S mode read from mhpmcounter9h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter10h with illegal instruction
+00000002 # S mode read from mhpmcounter10h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter11h with illegal instruction
+00000002 # S mode read from mhpmcounter11h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter12h with illegal instruction
+00000002 # S mode read from mhpmcounter12h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter13h with illegal instruction
+00000002 # S mode read from mhpmcounter13h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter14h with illegal instruction
+00000002 # S mode read from mhpmcounter14h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter15h with illegal instruction
+00000002 # S mode read from mhpmcounter15h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter16h with illegal instruction
+00000002 # S mode read from mhpmcounter16h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter17h with illegal instruction
+00000002 # S mode read from mhpmcounter17h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter18h with illegal instruction
+00000002 # S mode read from mhpmcounter18h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter19h with illegal instruction
+00000002 # S mode read from mhpmcounter19h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter20h with illegal instruction
+00000002 # S mode read from mhpmcounter20h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter21h with illegal instruction
+00000002 # S mode read from mhpmcounter21h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter22h with illegal instruction
+00000002 # S mode read from mhpmcounter22h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter23h with illegal instruction
+00000002 # S mode read from mhpmcounter23h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter24h with illegal instruction
+00000002 # S mode read from mhpmcounter24h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter25h with illegal instruction
+00000002 # S mode read from mhpmcounter25h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter26h with illegal instruction
+00000002 # S mode read from mhpmcounter26h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter27h with illegal instruction
+00000002 # S mode read from mhpmcounter27h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter28h with illegal instruction
+00000002 # S mode read from mhpmcounter28h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter29h with illegal instruction
+00000002 # S mode read from mhpmcounter29h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter30h with illegal instruction
+00000002 # S mode read from mhpmcounter30h with illegal instruction
+00000bad
+00000002 # S mode write to mhpmcounter31h with illegal instruction
+00000002 # S mode read from mhpmcounter31h with illegal instruction
+00000bad
 00000002 # S mode write to mvendorid with illegal instruction
 00000002 # S mode read from mvendorid with illegal instruction
 00000bad
@@ -923,102 +1022,3 @@ deadbeef
 deadbeef
 deadbeef
 deadbeef
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-deadbeef
-deadbeef

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-s-01.S

@@ -37,6 +37,44 @@ GOTO_S_MODE 0x0, 0x0
 # Attempt to write 0xbad to each of these CSRs and read the value back
 # should result in an illegal instruction for the write and read, respectively
 
+# High-bit versions storing the upper 32 bits of some CSRs for RV32
+# WRITE_READ_CSR mstatush 0xbad # *** these appear not to be implemented in GCC
+# WRITE_READ_CSR menvcfgh 0xbad
+# WRITE_READ_CSR mseccfgh 0xbad
+WRITE_READ_CSR pmpcfg1 0xbad
+WRITE_READ_CSR pmpcfg3 0xbad
+WRITE_READ_CSR mcycleh 0xbad
+WRITE_READ_CSR minstreth 0xbad
+WRITE_READ_CSR mhpmcounter3h 0xbad
+WRITE_READ_CSR mhpmcounter4h 0xbad
+WRITE_READ_CSR mhpmcounter5h 0xbad
+WRITE_READ_CSR mhpmcounter6h 0xbad
+WRITE_READ_CSR mhpmcounter7h 0xbad
+WRITE_READ_CSR mhpmcounter8h 0xbad
+WRITE_READ_CSR mhpmcounter9h 0xbad
+WRITE_READ_CSR mhpmcounter10h 0xbad
+WRITE_READ_CSR mhpmcounter11h 0xbad
+WRITE_READ_CSR mhpmcounter12h 0xbad
+WRITE_READ_CSR mhpmcounter13h 0xbad
+WRITE_READ_CSR mhpmcounter14h 0xbad
+WRITE_READ_CSR mhpmcounter15h 0xbad
+WRITE_READ_CSR mhpmcounter16h 0xbad
+WRITE_READ_CSR mhpmcounter17h 0xbad
+WRITE_READ_CSR mhpmcounter18h 0xbad
+WRITE_READ_CSR mhpmcounter19h 0xbad
+WRITE_READ_CSR mhpmcounter20h 0xbad
+WRITE_READ_CSR mhpmcounter21h 0xbad
+WRITE_READ_CSR mhpmcounter22h 0xbad
+WRITE_READ_CSR mhpmcounter23h 0xbad
+WRITE_READ_CSR mhpmcounter24h 0xbad
+WRITE_READ_CSR mhpmcounter25h 0xbad
+WRITE_READ_CSR mhpmcounter26h 0xbad
+WRITE_READ_CSR mhpmcounter27h 0xbad
+WRITE_READ_CSR mhpmcounter28h 0xbad
+WRITE_READ_CSR mhpmcounter29h 0xbad
+WRITE_READ_CSR mhpmcounter30h 0xbad
+WRITE_READ_CSR mhpmcounter31h 0xbad
+
 # Machine information Registers
 WRITE_READ_CSR mvendorid, 0xbad
 WRITE_READ_CSR marchid, 0xbad
@@ -68,7 +106,7 @@ WRITE_READ_CSR mip, 0xbad
 
 # Machine Memory Protection
 WRITE_READ_CSR pmpcfg0, 0xbad
-WRITE_READ_CSR pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs 
+WRITE_READ_CSR pmpcfg2, 0xbad # there's 1 pmpcfg reg per 8 pmpaddr regs 
 
 WRITE_READ_CSR pmpaddr0, 0xbad
 WRITE_READ_CSR pmpaddr1, 0xbad