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Minor fixes in regression

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This commit is contained in:
Jarred Allen 2021-05-09 13:57:09 -04:00
parent c7f400262c
commit 041149eaf7
2 changed files with 7 additions and 7 deletions
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2
wally-pipelined/regression/regression-wally.py
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@ -45,7 +45,7 @@ configs = [
), ),
TestCase( TestCase(
name="lints", name="lints",
cmd="../lint-wally > {}", cmd="../lint-wally &> {}",
grepstr="All lints run with no errors or warnings" grepstr="All lints run with no errors or warnings"
), ),
] ]

12
wally-pipelined/regression/wally-busybear-batch.do
View File

@ -17,23 +17,23 @@
onbreak {resume} onbreak {resume}
# create library # create library
if [file exists work-busybear] { if [file exists work_busybear] {
vdel -all -lib work-busybear vdel -all -lib work_busybear
} }
vlib work-busybear vlib work_busybear
# compile source files # compile source files
# suppress spurious warnngs about # suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time" # "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt # because vsim will run vopt
vlog +incdir+../config/busybear ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583 vlog -work work_busybear +incdir+../config/busybear ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583
# start and run simulation # start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals # remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt work.testbench -o workopt vopt work_busybear.testbench -o workopt_busybear
vsim workopt -suppress 8852,12070 vsim workopt_busybear -suppress 8852,12070
run -all run -all
quit quit