Not sure I understand the Misaligned hptw - seems like a bug and should be L1_ADR instead of L0_ADR

wally-pipelined/src/mmu/hptw.sv

@@ -146,6 +146,7 @@ module hptw
 	  if (`XLEN == 32) begin
 		assign InitialWalkerState = L1_ADR;
 		assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0
+	     // *** Possible bug - should be L1_ADR?
 		assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned);
 	  end else begin
 		logic  GigapageMisaligned, TerapageMisaligned;