Fixed lint WIDTH errors

wally-pipelined/src/ebu/amoalu.sv

@@ -50,7 +50,7 @@ module amoalu (
       5'b10100: y = ($signed(a) >= $signed(b)) ? a : b;                 // amomax
       5'b11000: y = ($unsigned(a) < $unsigned(b)) ? a : b;  // amominu
       5'b11100: y = ($unsigned(a) >= $unsigned(b)) ? a : b; // amomaxu
-      default:  y = 'bx;                              // undefined; *** could change to b for efficiency
+      default:  y = `XLEN'bx;                              // undefined; *** could change to b for efficiency
     endcase
 
   // sign extend if necessary

wally-pipelined/src/ieu/controller.sv

@@ -156,7 +156,7 @@ module controller(
   assign IllegalBaseInstrFaultD = ControlsD[0];
   assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD,
           ResultSrcD, BranchD, ALUOpD, JumpD, TargetSrcD, W64D, CSRReadD, 
-          PrivilegedD, MulDivD, AtomicD, unused} = ControlsD & ~IllegalIEUInstrFaultD;
+          PrivilegedD, MulDivD, AtomicD, unused} = IllegalIEUInstrFaultD ? `CTRLW'b0 : ControlsD;
           // *** move Privileged, CSRwrite??  Or move controller out of IEU into datapath and handle all instructions
 
   assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source?

wally-pipelined/src/mmu/pagetablewalker.sv

@@ -353,7 +353,7 @@ module pagetablewalker (
       // Assign outputs to ahblite
       // *** Currently truncate address to 32 bits. This must be changed if
       // we support larger physical address spaces
-      assign MMUPAdr = TranslationPAdr[31:0];
+      assign MMUPAdr = {{(`XLEN-32){1'b0}}, TranslationPAdr[31:0]};
     end
   endgenerate
 

wally-pipelined/src/mmu/physicalpagemask.sv

@@ -36,7 +36,7 @@ module physicalpagemask (
 );
 
   localparam EXTRA_BITS = `PPN_BITS - `VPN_BITS;
-  logic ZeroExtendedVPN = {{EXTRA_BITS{1'b0}}, VPN}; // forces the VPN to be the same width as PPN.
+  logic [`PPN_BITS-1:0] ZeroExtendedVPN = {{EXTRA_BITS{1'b0}}, VPN}; // forces the VPN to be the same width as PPN.
 
   logic [`PPN_BITS-1:0] OffsetMask;
 

wally-pipelined/src/mmu/priorityencoder.sv

@@ -40,7 +40,9 @@ module priorityencoder #(parameter BINARY_BITS = 3) (
   always_comb begin
     binary = 0;
     for (i = 0; i < 2**BINARY_BITS; i++) begin
+      // verilator lint_off WIDTH
       if (onehot[i]) binary = i; // prioritizes the most significant bit
+      // verilator lint_on WIDTH
     end
   end
   // *** triple check synthesizability here

wally-pipelined/src/muldiv/mul.sv

@@ -59,8 +59,8 @@ module mul (
     assign PP = SrcAE[`XLEN-1] & SrcBE[`XLEN-1];
 
     // flavor of multiplication
-    assign MULH = (Funct3E == 2'b01);
+    assign MULH   = (Funct3E == 3'b001);
-    assign MULHSU = (Funct3E == 2'b10);
+    assign MULHSU = (Funct3E == 3'b010);
     // assign MULHU = (Funct3E == 2'b11); // signal unused
 
     // Handle signs

wally-pipelined/src/privileged/csr.sv

@@ -53,7 +53,7 @@ module csr #(parameter
   output logic [1:0]       STATUS_MPP,
   output logic             STATUS_SPP, STATUS_TSR,
   output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
-  output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW, 
+  output logic [11:0]      MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW, 
   output logic [`XLEN-1:0] SATP_REGW,
   output logic [11:0]      MIP_REGW, MIE_REGW,
   output logic             STATUS_MIE, STATUS_SIE,

wally-pipelined/src/privileged/csrc.sv

@@ -53,6 +53,7 @@ module csrc (
     integer MHPEVENT [`COUNTERS:0];
 
     genvar i;
+    // *** this is totally incorrect.  Fix parameterized counters dh 6/9/21
     generate
     for (i = 0; i <= `COUNTERS; i = i + 1) begin 
         if (i != 1) begin

wally-pipelined/src/privileged/csri.sv

@@ -37,7 +37,7 @@ module csri #(parameter
     input  logic             CSRMWriteM, CSRSWriteM,
     input  logic [11:0]      CSRAdrM,
     input  logic             ExtIntM, TimerIntM, SwIntM,
-    input  logic [`XLEN-1:0] MIDELEG_REGW,
+    input  logic [11:0]      MIDELEG_REGW,
     output logic [11:0]      MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
     input  logic [`XLEN-1:0] CSRWriteValM
   );
@@ -87,8 +87,8 @@ module csri #(parameter
     end
     always @(posedge clk, posedge reset) begin
       if (reset)          IE_REGW <= 12'b0;
-      else if (WriteMIEM) IE_REGW <= (CSRWriteValM & 12'hAAA); // MIE controls M and S fields
+      else if (WriteMIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'hAAA); // MIE controls M and S fields
-      else if (WriteSIEM) IE_REGW <= (CSRWriteValM & 12'h222) | (IE_REGW & 12'h888); // only S fields
+      else if (WriteSIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (IE_REGW & 12'h888); // only S fields
 //      else if (WriteUIEM) IE_REGW = (CSRWriteValM & 12'h111) | (IE_REGW & 12'hAAA); // only U field
     end
   endgenerate

wally-pipelined/src/privileged/csrm.sv

@@ -74,13 +74,7 @@ module csrm #(parameter
   DCSR = 12'h7B0,
   DPC = 12'h7B1,
   DSCRATCH0 = 12'h7B2,
-  DSCRATCH1 = 12'h7B3,
+  DSCRATCH1 = 12'h7B3  
-
-  // Constants
-  ZERO = {(`XLEN){1'b0}},
-  ALL_ONES = 32'hfffffff,
-  MEDELEG_MASK = ~(ZERO | 1'b1 << 11),
-  MIDELEG_MASK = {{(`XLEN-12){1'b0}}, 12'h222}
 ) (
     input  logic             clk, reset, 
     input  logic             StallW,
@@ -90,7 +84,7 @@ module csrm #(parameter
     input  logic [`XLEN-1:0] CSRWriteValM,
     output logic [`XLEN-1:0] CSRMReadValM, MEPC_REGW, MTVEC_REGW, 
     output logic [31:0]      MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, 
-    output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW,
+    output logic [11:0]      MEDELEG_REGW, MIDELEG_REGW,
     // 64-bit registers in RV64, or two 32-bit registers in RV32
     output logic [63:0]      PMPCFG01_REGW, PMPCFG23_REGW,
     output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1],
@@ -149,8 +143,8 @@ module csrm #(parameter
   flopenl #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, `XLEN'b0, MTVEC_REGW); //busybear: changed reset value to 0
   generate
     if (`S_SUPPORTED | (`U_SUPPORTED & `N_SUPPORTED)) begin // DELEG registers should exist
-      flopenl #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK, ZERO, MEDELEG_REGW);
+      flopenl #(12) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM[11:0] & 12'h7FF, 12'b0, MEDELEG_REGW);
-      flopenl #(`XLEN) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM & MIDELEG_MASK, ZERO, MIDELEG_REGW);
+      flopenl #(12) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM[11:0] & 12'h222, 12'b0, MIDELEG_REGW);
     end else begin
       assign MEDELEG_REGW = 0;
       assign MIDELEG_REGW = 0;
@@ -167,9 +161,9 @@ module csrm #(parameter
     if (`OVPSIM_CSR_CONFIG)
       flopenl #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, MCOUNTEREN_REGW);
     else
-      flopenl #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], ALL_ONES, MCOUNTEREN_REGW);
+      flopenl #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], 32'hFFFFFFFF, MCOUNTEREN_REGW);
   endgenerate
-  flopenl #(32)   MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], ALL_ONES, MCOUNTINHIBIT_REGW);
+  flopenl #(32)   MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], 32'hFFFFFFFF, MCOUNTINHIBIT_REGW);
 
   // There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop
   generate
@@ -202,13 +196,13 @@ module csrm #(parameter
       MISA_ADR:  CSRMReadValM = MISA_REGW;
       MVENDORID: CSRMReadValM = 0;
       MARCHID:   CSRMReadValM = 0;
-      MIMPID:    CSRMReadValM = 'h100; // pipelined implementation
+      MIMPID:    CSRMReadValM = `XLEN'h100; // pipelined implementation
       MHARTID:   CSRMReadValM = 0; 
       MSTATUS:   CSRMReadValM = MSTATUS_REGW;
       MSTATUSH:  CSRMReadValM = 0; // flush this out later if MBE and SBE fields are supported
       MTVEC:     CSRMReadValM = MTVEC_REGW;
-      MEDELEG:   CSRMReadValM = MEDELEG_REGW;
+      MEDELEG:   CSRMReadValM = {{(`XLEN-12){1'b0}}, MEDELEG_REGW};
-      MIDELEG:   CSRMReadValM = MIDELEG_REGW;
+      MIDELEG:   CSRMReadValM = {{(`XLEN-12){1'b0}}, MIDELEG_REGW};
       MIP:       CSRMReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW};
       MIE:       CSRMReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW};
       MSCRATCH:  CSRMReadValM = MSCRATCH_REGW;
@@ -218,9 +212,9 @@ module csrm #(parameter
       MCOUNTEREN:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTEREN_REGW};
       MCOUNTINHIBIT:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW};
       PMPCFG0:   CSRMReadValM = PMPCFG01_REGW[`XLEN-1:0];
-      PMPCFG1:   CSRMReadValM = {{(`XLEN-32){1'b0}}, PMPCFG01_REGW[63:31]};
+      PMPCFG1:   CSRMReadValM = {{(`XLEN-32){1'b0}}, PMPCFG01_REGW[63:32]};
       PMPCFG2:   CSRMReadValM = PMPCFG23_REGW[`XLEN-1:0];
-      PMPCFG3:   CSRMReadValM = {{(`XLEN-32){1'b0}}, PMPCFG23_REGW[63:31]};
+      PMPCFG3:   CSRMReadValM = {{(`XLEN-32){1'b0}}, PMPCFG23_REGW[63:32]};
       PMPADDR0:  CSRMReadValM = PMPADDR_ARRAY_REGW[0]; // *** make configurable
       PMPADDR1:  CSRMReadValM = PMPADDR_ARRAY_REGW[1];
       PMPADDR2:  CSRMReadValM = PMPADDR_ARRAY_REGW[2];

wally-pipelined/src/privileged/csrs.sv

@@ -40,12 +40,7 @@ module csrs #(parameter
   SCAUSE = 12'h142,
   STVAL = 12'h143,
   SIP= 12'h144,
-  SATP = 12'h180,
+  SATP = 12'h180
-
-  // Constants
-  ZERO = {(`XLEN){1'b0}},
-  ALL_ONES = 32'hfffffff,
-  SEDELEG_MASK = ~(ZERO | 3'b111 << 9)
   ) (
     input  logic             clk, reset, 
     input  logic             StallW,
@@ -55,7 +50,7 @@ module csrs #(parameter
     input  logic [`XLEN-1:0] CSRWriteValM,
     output logic [`XLEN-1:0] CSRSReadValM, SEPC_REGW, STVEC_REGW, 
     output logic [31:0]      SCOUNTEREN_REGW,     
-    output logic [`XLEN-1:0] SEDELEG_REGW, SIDELEG_REGW, 
+    output logic [11:0]      SEDELEG_REGW, SIDELEG_REGW, 
     output logic [`XLEN-1:0] SATP_REGW,
     input  logic [11:0]      SIP_REGW, SIE_REGW,
     output logic             WriteSSTATUSM,
@@ -84,22 +79,22 @@ module csrs #(parameter
       assign WriteSCOUNTERENM = CSRSWriteM && (CSRAdrM == SCOUNTEREN) && ~StallW;
 
       // CSRs
-      flopenl #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, ZERO, STVEC_REGW); //busybear: change reset to 0
+      flopenl #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, `XLEN'b0, STVEC_REGW); //busybear: change reset to 0
       flopenr #(`XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW);
       flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW); 
-      flopenl #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, ZERO, SCAUSE_REGW); 
+      flopenl #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, `XLEN'b0, SCAUSE_REGW); 
       flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW);
       flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
       if (`OVPSIM_CSR_CONFIG)
         flopenl #(32)   SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, SCOUNTEREN_REGW);
       else
-        flopenl #(32)   SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], ALL_ONES, SCOUNTEREN_REGW);
+        flopenl #(32)   SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], 32'hFFFFFFFF, SCOUNTEREN_REGW);
       if (`N_SUPPORTED) begin
         logic WriteSEDELEGM, WriteSIDELEGM;
         assign WriteSEDELEGM = CSRSWriteM && (CSRAdrM == SEDELEG);
         assign WriteSIDELEGM = CSRSWriteM && (CSRAdrM == SIDELEG);
-        flopenl #(`XLEN) SEDELEGreg(clk, reset, WriteSEDELEGM, CSRWriteValM & SEDELEG_MASK, ZERO, SEDELEG_REGW);
+        flopenl #(12) SEDELEGreg(clk, reset, WriteSEDELEGM, CSRWriteValM[11:0] & 12'h1FF, 12'b0, SEDELEG_REGW);
-        flopenl #(`XLEN) SIDELEGreg(clk, reset, WriteSIDELEGM, CSRWriteValM, ZERO, SIDELEG_REGW);
+        flopenl #(12) SIDELEGreg(clk, reset, WriteSIDELEGM, CSRWriteValM[11:0], 12'b0, SIDELEG_REGW);
       end else begin
         assign SEDELEG_REGW = 0;
         assign SIDELEG_REGW = 0;
@@ -111,8 +106,8 @@ module csrs #(parameter
         case (CSRAdrM) 
           SSTATUS:   CSRSReadValM = SSTATUS_REGW;
           STVEC:     CSRSReadValM = STVEC_REGW;
-          SEDELEG:   CSRSReadValM = SEDELEG_REGW;
+          SEDELEG:   CSRSReadValM = {{(`XLEN-12){1'b0}}, SEDELEG_REGW};
-          SIDELEG:   CSRSReadValM = SIDELEG_REGW;
+          SIDELEG:   CSRSReadValM = {{(`XLEN-12){1'b0}}, SIDELEG_REGW};
           SIP:       CSRSReadValM = {{(`XLEN-12){1'b0}}, SIP_REGW};
           SIE:       CSRSReadValM = {{(`XLEN-12){1'b0}}, SIE_REGW};
           SSCRATCH:  CSRSReadValM = SSCRATCH_REGW;

wally-pipelined/src/privileged/privileged.sv

@@ -76,8 +76,7 @@ module privileged (
 
   logic [`XLEN-1:0] CauseM, NextFaultMtvalM;
   logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW;
-  logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW;
+  logic [11:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW;
-//  logic [11:0]     MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW;
 
   logic uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM;
   logic IllegalCSRAccessM;
@@ -105,8 +104,8 @@ module privileged (
   ///////////////////////////////////////////
 
   // get bits of DELEG registers based on CAUSE
-  assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[4:0]] : MEDELEG_REGW[CauseM[4:0]];
+  assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[3:0]];
-  assign sd = CauseM[`XLEN-1] ? SIDELEG_REGW[CauseM[4:0]] : SEDELEG_REGW[CauseM[4:0]]; // depricated
+  assign sd = CauseM[`XLEN-1] ? SIDELEG_REGW[CauseM[3:0]] : SEDELEG_REGW[CauseM[3:0]]; // depricated
   
   // PrivilegeMode FSM
   always_comb

wally-pipelined/src/privileged/trap.sv

@@ -49,15 +49,16 @@ module trap (
 //  input  logic            WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM
 );
 
-  logic [11:0] MIntGlobalEnM, SIntGlobalEnM, PendingIntsM; 
+  logic MIntGlobalEnM, SIntGlobalEnM;
+  logic [11:0] PendingIntsM; 
   //logic InterruptM;
   logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector;
   logic BusTrapM;
 
   // Determine pending enabled interrupts
-  assign MIntGlobalEnM = {12{(PrivilegeModeW != `M_MODE) || STATUS_MIE}}; // if M ints enabled or lower priv 3.1.9
+  assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9
   assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || STATUS_SIE; // if S ints enabled or lower priv 3.1.9
-  assign PendingIntsM = (MIP_REGW & MIE_REGW) & ((MIntGlobalEnM & 12'h888) | (SIntGlobalEnM & 12'h222));
+  assign PendingIntsM = (MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888) | ({12{SIntGlobalEnM}} & 12'h222);
   assign InterruptM = (|PendingIntsM) & InstrValidM & ~CommittedM;
   // interrupt if any sources are pending
   // & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage)

wally-pipelined/src/uncore/dtim.sv

@@ -96,6 +96,7 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
   end
  -----/\----- EXCLUDED -----/\----- */
   
+  /* verilator lint_off WIDTH */
   generate
     if (`XLEN == 64)  begin
       always_ff @(posedge HCLK) begin
@@ -111,7 +112,8 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
       end
     end
   endgenerate
+  /* verilator lint_on WIDTH */
 
-  assign HREADTim = HREADYTim ? HREADTim0 : 'bz;
+  assign HREADTim = HREADYTim ? HREADTim0 : `XLEN'bz;
 endmodule
 

wally-pipelined/src/uncore/uartPC16550D.sv

@@ -70,7 +70,7 @@ module uartPC16550D(
 
   // Baud and rx/tx timing
   logic baudpulse, txbaudpulse, rxbaudpulse; // high one system clk cycle each baud/16 period
-  logic [23:0] baudcount;
+  logic [16+`UART_PRESCALE-1:0] baudcount;
   logic [3:0] rxoversampledcnt, txoversampledcnt; // count oversampled-by-16
   logic [3:0] rxbitsreceived, txbitssent;
   statetype rxstate, txstate;
@@ -97,7 +97,8 @@ module uartPC16550D(
   logic [15:0] rxerrbit, rxfullbit;
 
   // transmit data
-  logic [11:0] TXHR, txdata, nexttxdata, txsr;
+  logic [7:0] TXHR, nexttxdata;
+  logic [11:0] txdata, txsr;
   logic txnextbit, txhrfull, txsrfull;
   logic txparity;
   logic txfifoempty, txfifofull, txfifodmaready;
@@ -166,7 +167,7 @@ module uartPC16550D(
   always_comb
     if (~MEMRb)
       case (A)
-        3'b000: if (DLAB) Dout = DLL; else Dout = RBR;
+        3'b000: if (DLAB) Dout = DLL; else Dout = RBR[7:0];
         3'b001: if (DLAB) Dout = DLM; else Dout = {4'b0, IER[3:0]};
         3'b010: Dout = {{2{fifoenabled}}, 2'b00, intrID[2:0], ~intrpending}; // Read only Interupt Ident Register
         3'b011: Dout = LCR;
@@ -226,13 +227,13 @@ module uartPC16550D(
     end
 
   assign rxcentered = rxbaudpulse && (rxoversampledcnt == 4'b1000);  // implies rxstate = UART_ACTIVE
-  assign rxbitsexpected = 1 + (5 + LCR[1:0]) + LCR[3] + 1; // start bit + data bits + (parity bit) + stop bit 
+  assign rxbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1; // start bit + data bits + (parity bit) + stop bit 
   
   ///////////////////////////////////////////
   // receive shift register, buffer register, FIFO
   ///////////////////////////////////////////
   always_ff @(posedge HCLK, negedge HRESETn)
-    if (~HRESETn) rxshiftreg <= #1 9'b000000001; // initialize so that there is a valid stop bit
+    if (~HRESETn) rxshiftreg <= #1 10'b0000000001; // initialize so that there is a valid stop bit
     else if (rxcentered) rxshiftreg <= #1 {rxshiftreg[8:0], SINsync}; // capture bit
   assign rxparitybit = rxshiftreg[1]; // parity, if it exists, in bit 1 when all done
   assign rxstopbit = rxshiftreg[0];
@@ -276,8 +277,10 @@ module uartPC16550D(
     end
 
   assign rxfifoempty = (rxfifohead == rxfifotail);
+  // verilator lint_off WIDTH
   assign rxfifoentries = (rxfifohead >= rxfifotail) ? (rxfifohead-rxfifotail) : 
                                                       (rxfifohead + 16 - rxfifotail);
+  // verilator lint_on WIDTH
   assign rxfifotriggered = rxfifoentries >= rxfifotriggerlevel;
   //assign rxfifotimeout = rxtimeoutcnt[6]; // time out after 4 character periods; *** probably not right yet
   assign rxfifotimeout = 0; // disabled pending fix
@@ -335,7 +338,7 @@ module uartPC16550D(
       txstate <= #1 UART_IDLE;
     end
 
-  assign txbitsexpected = 1 + (5 + LCR[1:0]) + LCR[3] + 1 + LCR[2] - 1; // start bit + data bits + (parity bit) + stop bit(s)
+  assign txbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1 + {3'b000, LCR[2]} - 4'd1; // start bit + data bits + (parity bit) + stop bit(s)
   assign txnextbit = txbaudpulse && (txoversampledcnt == 4'b0000);  // implies txstate = UART_ACTIVE
 
   ///////////////////////////////////////////
@@ -399,8 +402,10 @@ module uartPC16550D(
     end
 
   assign txfifoempty = (txfifohead == txfifotail);
+  // verilator lint_off WIDTH
   assign txfifoentries = (txfifohead >= txfifotail) ? (txfifohead-txfifotail) : 
                                                       (txfifohead + 16 - txfifotail);
+  // verilator lint_on WIDTH
   assign txfifofull = (txfifoentries == 4'b1111);
 
   // transmit buffer ready bit
@@ -442,7 +447,7 @@ module uartPC16550D(
   always @(posedge HCLK) INTR <= #1 intrpending; // prevent glitches on interrupt pin
 
     // Side effect of reading IIR is lowering THRE if most significant intr
-  assign suppressTHREbecauseIIRtrig = ~MEMRb & (A==3'b010) & (intrID==2'h1);
+  assign suppressTHREbecauseIIRtrig = ~MEMRb & (A==3'b010) & (intrID==3'h1);
   flopr #(1) suppressTHREreg(HCLK, (~HRESETn | (fifoenabled ? ~txfifoempty : txhrfull)), (suppressTHREbecauseIIRtrig | suppressTHREbecauseIIR), suppressTHREbecauseIIR);
 
   ///////////////////////////////////////////

wally-pipelined/testbench/testbench-imperas.sv

@@ -516,6 +516,10 @@ string tests32f[] = '{
   
   flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
   flopenr  #(32)   InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW,  dut.hart.ifu.InstrM, InstrW);
+
+  // check assertions for a legal configuration
+  riscvassertions riscvassertions();
+
   // pick tests based on modes supported
   initial begin
     if (`XLEN == 64) begin // RV64
@@ -713,6 +717,13 @@ string tests32f[] = '{
   
 endmodule
 
+module riscvassertions();
+  // Legal number of PMP entries are 0, 16, or 64
+  initial begin
+    assert (`PMP_ENTRIES == 0 || `PMP_ENTRIES==16 || `PMP_ENTRIES==64) else $error("Illegal number of PMP entries");
+  end
+endmodule
+
 /* verilator lint_on STMTDLY */
 /* verilator lint_on WIDTH */