Removed unused signals; added check for atomic in pmachecker

pipelined/src/ifu/ifu.sv

@@ -164,7 +164,7 @@ module ifu (
          .TLBFlush,
          .PhysicalAddress(PCPF),
          .TLBMiss(ITLBMissF),
-         .Cacheable(CacheableF), .Idempotent(), .AtomicAllowed(), .SelTIM(SelIROM),
+         .Cacheable(CacheableF), .Idempotent(), .SelTIM(SelIROM),
          .InstrAccessFaultF, .LoadAccessFaultM(), .StoreAmoAccessFaultM(),
          .InstrPageFaultF, .LoadPageFaultM(), .StoreAmoPageFaultM(),
          .LoadMisalignedFaultM(), .StoreAmoMisalignedFaultM(),
@@ -195,8 +195,7 @@ module ifu (
   // The IROM uses untranslated addresses, so it is not compatible with virtual memory.
   if (`IROM_SUPPORTED) begin : irom 
     assign IFURWF = 2'b10;
-    irom irom(.clk, .reset, .ce(~GatedStallD | reset), .Adr(PCNextFSpill[`XLEN-1:0]), .ReadData(IROMInstrF));
- 
+    irom irom(.clk, .ce(~GatedStallD | reset), .Adr(PCNextFSpill[`XLEN-1:0]), .ReadData(IROMInstrF));
   end else begin
     assign IFURWF = 2'b10;
   end

pipelined/src/ifu/irom.sv

@@ -30,7 +30,7 @@
 `include "wally-config.vh"
 
 module irom(
-  input logic               clk, reset, ce,
+  input logic               clk, ce,
   input logic [`XLEN-1:0]   Adr,
   output logic [31:0]  ReadData
 );

pipelined/src/lsu/dtim.sv

@@ -30,7 +30,7 @@
 `include "wally-config.vh"
 
 module dtim(
-  input logic                clk, reset, ce,
+  input logic                clk, ce,
   input logic [1:0]          MemRWM,
   input logic [`PA_BITS-1:0] Adr,
   input logic                FlushW, 

pipelined/src/lsu/lsu.sv

@@ -171,7 +171,7 @@ module lsu (
       .TLBFlush(sfencevmaM),
       .PhysicalAddress(PAdrM),
       .TLBMiss(DTLBMissM),
-      .Cacheable(CacheableM), .Idempotent(), .AtomicAllowed(), .SelTIM(SelDTIM),
+      .Cacheable(CacheableM), .Idempotent(), .SelTIM(SelDTIM),
       .InstrAccessFaultF(), .LoadAccessFaultM(LSULoadAccessFaultM), .StoreAmoAccessFaultM(LSUStoreAmoAccessFaultM),
       .InstrPageFaultF(),.LoadPageFaultM, .StoreAmoPageFaultM,
       .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,   // *** these faults need to be supressed during hptw.
@@ -218,9 +218,8 @@ module lsu (
     assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : '0;
     // **** fix ReadDataWordM to be LLEN. ByteMask is wrong length.
     // **** create config to support DTIM with floating point.
-    dtim dtim(.clk, .reset, .ce(~GatedStallW), .MemRWM(DTIMMemRWM),
-              .Adr(DTIMAdr),
-              .FlushW, .WriteDataM(LSUWriteDataM), 
+    dtim dtim(.clk, .ce(~GatedStallW), .MemRWM(DTIMMemRWM),
+              .Adr(DTIMAdr), .FlushW, .WriteDataM(LSUWriteDataM), 
               .ReadDataWordM(DTIMReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]));
   end else begin
   end
@@ -233,12 +232,9 @@ module lsu (
       localparam integer   LINELEN = `DCACHE ? `DCACHE_LINELENINBITS : `XLEN;
       logic [LINELEN-1:0]  FetchBuffer;
       logic [`PA_BITS-1:0] DCacheBusAdr;
-      logic                DCacheWriteLine;
-      logic                DCacheFetchLine;
       logic [AHBWLOGBWPL-1:0]  BeatCount;
       logic                DCacheBusAck;
       logic                SelBusBeat;
-      logic [`XLEN/8-1:0]  ByteMaskMDelay;
       logic [1:0]          CacheBusRW, BusRW;
       localparam integer   LLENPOVERAHBW = `LLEN / `AHBW;
       logic                CacheableOrFlushCacheM;
@@ -280,7 +276,6 @@ module lsu (
                                     .d2({{`LLEN-`XLEN{1'b0}}, DTIMReadDataWordM[`XLEN-1:0]}),
                                     .s({SelDTIM, ~(CacheableOrFlushCacheM)}), .y(ReadDataWordMuxM));
     end else begin : passthrough // just needs a register to hold the value from the bus
-      logic CaptureEn;
       logic [1:0] BusRW;
       logic [`XLEN-1:0] FetchBuffer;
       assign BusRW = ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0;

pipelined/src/mmu/mmu.sv

@@ -66,7 +66,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
   // Physical address outputs
   output logic [`PA_BITS-1:0] PhysicalAddress,
   output logic                TLBMiss,
-  output logic                Cacheable, Idempotent, AtomicAllowed, SelTIM,
+  output logic                Cacheable, Idempotent, SelTIM,
 
   // Faults
   output logic                InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM,
@@ -126,7 +126,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
 
   pmachecker pmachecker(.PhysicalAddress, .Size,
                         .AtomicAccessM, .ExecuteAccessF, .WriteAccessM, .ReadAccessM,
-                        .Cacheable, .Idempotent, .AtomicAllowed, .SelTIM,
+                        .Cacheable, .Idempotent, .SelTIM,
                         .PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM);
  
   pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW,

pipelined/src/mmu/pmachecker.sv

@@ -33,12 +33,10 @@
 `include "wally-config.vh"
 
 module pmachecker (
-//  input  logic        clk, reset, // *** unused in this module and all sub modules.
-
   input  logic [`PA_BITS-1:0] PhysicalAddress,
   input  logic [1:0]          Size,
   input  logic        AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // *** atomicaccessM is unused but might want to stay in for future use.
-  output logic        Cacheable, Idempotent, AtomicAllowed, SelTIM,
+  output logic        Cacheable, Idempotent, SelTIM,
   output logic        PMAInstrAccessFaultF,
   output logic        PMALoadAccessFaultM,
   output logic        PMAStoreAmoAccessFaultM
@@ -47,6 +45,7 @@ module pmachecker (
   logic PMAAccessFault;
   logic AccessRW, AccessRWX, AccessRX;
   logic [10:0]  SelRegions;
+  logic AtomicAllowed;
 
   // Determine what type of access is being made
   assign AccessRW = ReadAccessM | WriteAccessM;
@@ -63,7 +62,7 @@ module pmachecker (
   assign SelTIM = SelRegions[10] | SelRegions[9];
 
   // Detect access faults
-  assign PMAAccessFault = (SelRegions[0]) & AccessRWX;  
+  assign PMAAccessFault = (SelRegions[0]) & AccessRWX | AtomicAccessM & ~AtomicAllowed;  
   assign PMAInstrAccessFaultF = ExecuteAccessF & PMAAccessFault;
   assign PMALoadAccessFaultM  = ReadAccessM    & PMAAccessFault;
   assign PMAStoreAmoAccessFaultM = WriteAccessM   & PMAAccessFault;