forked from Github_Repos/cvw
Added FlushF to hazard unit.
Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined. I will look this up and add it to the compiler.
This commit is contained in:
Ross Thompson
parent
f25de68b7d
commit
00de91cc87
@ -44,7 +44,7 @@ mem load -infile twoBitPredictor.txt -format bin testbench/dut/hart/ifu/bpred/Di
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mem load -infile BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory
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do wave.do
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add log /* -recursive
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add log -r /*
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-- Run the Simulation
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#run 1000
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1622
wally-pipelined/regression/wave-all.do
Normal file
1622
wally-pipelined/regression/wave-all.do
Normal file
File diff suppressed because it is too large
Load Diff
@ -3,17 +3,25 @@ quietly WaveActivateNextPane {} 0
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/reset
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add wave -noupdate -radix ascii /testbench/memfilename
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -divider <NULL>
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add wave -noupdate /testbench/dut/hart/ebu/IReadF
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add wave -noupdate -expand -group HDU /testbench/dut/hart/DataStall
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add wave -noupdate -expand -group HDU /testbench/dut/hart/InstrStall
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add wave -noupdate -expand -group HDU -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -expand -group HDU -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -expand -group HDU -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -expand -group HDU -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -expand -group HDU -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -expand -group HDU -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -expand -group HDU -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/InstrStall
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DataStall
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -expand -group Bpred -expand -group direction -divider Update
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add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdatePC
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add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdateEN
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@ -23,17 +31,23 @@ add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/
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add wave -noupdate -expand -group InstrClass /testbench/dut/hart/ifu/bpred/InstrClassF
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add wave -noupdate -expand -group InstrClass /testbench/dut/hart/ifu/bpred/InstrClassD
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add wave -noupdate -expand -group InstrClass /testbench/dut/hart/ifu/bpred/InstrClassE
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add wave -noupdate /testbench/dut/hart/ifu/bpred/InstrF
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrF
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
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add wave -noupdate /testbench/dut/hart/ifu/bpred/BPPredWrongE
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add wave -noupdate /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate /testbench/dut/hart/ifu/PCF
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add wave -noupdate /testbench/dut/hart/ifu/PCPlus2or4F
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add wave -noupdate /testbench/dut/hart/ifu/PCNext0F
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add wave -noupdate /testbench/dut/hart/ifu/PCNext1F
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add wave -noupdate /testbench/dut/hart/ifu/SelBPPredF
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add wave -noupdate /testbench/dut/hart/ifu/bpred/BTBValidF
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add wave -noupdate /testbench/dut/hart/ifu/bpred/BPPredF
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
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add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/ValidBits
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add wave -noupdate /testbench/dut/hart/ifu/bpred/BPPredF
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add wave -noupdate /testbench/dut/hart/ifu/bpred/BTBValidF
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add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/LookUpPCIndexQ
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add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePCIndexQ
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add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/LookUpPC
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@ -42,15 +56,38 @@ add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/FallT
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add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionDirWrongE
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add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionPCWrongE
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add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/BPPredWrongE
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add wave -noupdate -expand -group BTB -divider Update
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add wave -noupdate -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateEN
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add wave -noupdate -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePC
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add wave -noupdate -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateTarget
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/InstrClassE
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add wave -noupdate -group BTB -divider Update
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add wave -noupdate -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateEN
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add wave -noupdate -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePC
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add wave -noupdate -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateTarget
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add wave -noupdate -group BTB -divider Lookup
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add wave -noupdate -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/TargetPC
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add wave -noupdate -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/Valid
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add wave -noupdate /testbench/dut/hart/ifu/bpred/BTBPredPCF
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add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/TargetPC
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add wave -noupdate /testbench/dut/hart/ifu/bpred/CorrectPCE
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add wave -noupdate /testbench/dut/hart/ifu/bpred/FlushF
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add wave -noupdate /testbench/dut/hart/FlushF
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rf
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
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add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
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add wave -noupdate /testbench/dut/hart/ieu/c/RegWriteE
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -group {Decode Stage} /testbench/InstrDName
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
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add wave -noupdate /testbench/InstrFName
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {137177 ns} 0}
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quietly wave cursor active 1
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WaveRestoreCursors {{Cursor 2} {332469 ns} 0} {{Cursor 3} {333566 ns} 0} {{Cursor 4} {675 ns} 0}
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quietly wave cursor active 2
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 185
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configure wave -justifyvalue left
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@ -65,4 +102,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {136946 ns} {137442 ns}
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WaveRestoreZoom {333505 ns} {333689 ns}
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@ -34,7 +34,7 @@ module hazard(
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input logic LoadStallD,
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input logic InstrStall, DataStall,
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// Stall outputs
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output logic StallF, StallD, FlushD, FlushE, FlushM, FlushW
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output logic StallF, StallD, FlushF, FlushD, FlushE, FlushM, FlushW
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);
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logic BranchFlushDE;
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@ -58,7 +58,7 @@ module bpred
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logic [1:0] BPPredF, BPPredD, BPPredE, UpdateBPPredE;
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logic [3:0] InstrClassD, InstrClassF, InstrClassE;
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logic [`XLEN-1:0] BTBPredPCF, RASPCF, BTBPredPCMemoryF;
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logic [`XLEN-1:0] BTBPredPCF, RASPCF;
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logic TargetWrongE;
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logic FallThroughWrongE;
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logic PredictionDirWrongE;
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@ -71,7 +71,7 @@ module bpred
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// This is probably too much logic.
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// *** This also encourages me to switch to predicting the class.
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assign InstrClassF[2] = InstrF[6:0] == 7'h67 && InstrF[19:15] == 5'h01; // jump register, but not return
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assign InstrClassF[2] = InstrF[6:0] == 7'h67 && InstrF[19:15] != 5'h01; // jump register, but not return
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assign InstrClassF[1] = InstrF[6:0] == 7'h6F; // jump
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assign InstrClassF[0] = InstrF[6:0] == 7'h63; // branch
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@ -102,7 +102,7 @@ module bpred
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BTBPredictor TargetPredictor(.clk(clk),
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.reset(reset),
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.LookUpPC(PCNextF),
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.TargetPC(BTBPredPCMemoryF),
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.TargetPC(BTBPredPCF),
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.Valid(BTBValidF),
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// update
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.UpdateEN(InstrClassE[2] | InstrClassE[1] | InstrClassE[0]),
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@ -111,7 +111,7 @@ module bpred
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// need to forward when updating to the same address as reading.
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assign CorrectPCE = PCSrcE ? PCTargetE : PCLinkE;
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assign TargetPC = (PCE == PCNextF) ? CorrectPCE : BTBPredPCMemoryF;
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assign TargetPC = (PCE == PCNextF) ? CorrectPCE : BTBPredPCF;
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// Part 4 RAS
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// *** need to add the logic to restore RAS on flushes. We will use incr for this.
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@ -155,7 +155,7 @@ module bpred
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flopenrc #(4) InstrClassRegE(.clk(clk),
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.reset(reset),
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.en(~StallD),
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.clear(flushD),
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.clear(FlushD),
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.d(InstrClassD),
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.q(InstrClassE));
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@ -74,7 +74,7 @@ module ifu (
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assign PrivilegedChangePCM = RetM | TrapM;
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assign StallExceptResolveBranchesF = StallF & ~(PCSrcE | PrivilegedChangePCM);
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assign StallExceptResolveBranchesF = StallF & ~(SelBPPredF | BPPredWrongE | PrivilegedChangePCM);
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//mux3 #(`XLEN) pcmux(PCPlus2or4F, PCCorrectE, PrivilegedNextPCM, {PrivilegedChangePCM, BPPredWrongE}, UnalignedPCNextF);
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mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F),
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