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Minor optimization to cache replacement.

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This commit is contained in:
Ross Thompson 2022-01-06 17:19:14 -06:00
parent e1db967417
commit 008ac20a43
1 changed files with 2 additions and 2 deletions
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4
pipelined/src/cache/cache.sv vendored
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@ -147,7 +147,7 @@ module cache #(parameter integer LINELEN,
cachereplacementpolicy(.clk, .reset,
.WayHit,
.VictimWay,
.PAdr(PAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.PAdr(NoTranAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.RAdr,
.LRUWriteEn);
end else begin:vict
@ -197,7 +197,7 @@ module cache #(parameter integer LINELEN,
assign SRAMLineWayWriteEnable = SRAMLineWriteEnable ? VictimWay : '0;
mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnable ? WayHit : '0),
.d1(SRAMLineWayWriteEnable),
.d1(VictimWay),
.s(SRAMLineWriteEnable),
.y(SRAMWayWriteEnable));