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Add synthesis using DC shell back into repository

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This commit is contained in:
James Stine 2022-01-30 17:34:56 -06:00
parent 8fd975da74
commit 00619eda07
5 changed files with 514 additions and 0 deletions
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78
synthDC/.synopsys_dc.setup Executable file
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# Search Paths
set CURRENT_DIR [exec pwd]
set search_path [list "./" ]
set s8lib ../addins/sky130_osu_sc_t18/18T_ms/lib
lappend search_path $s8lib
# Synthetic libraries
set synthetic_library [list dw_foundation.sldb]
# Set OKSTATE standard cell libraries
set target_library [list]
lappend target_library sky130_osu_sc_18T_ms_TT_1P8_25C.ccs.db
# Set Link Library
set link_library "$target_library $synthetic_library"
# Set up DesignWare cache read and write directories to speed up compile.
set cache_write ~
set cache_read $cache_write
# Tell DC where to look for files
lappend search_path ./scripts
lappend search_path ./hdl
lappend search_path ./mapped
# Set up User Information
set company "Oklahoma State University"
set user "James E. Stine"
# Alias
alias ra report_area
alias rt report_timing
alias rc {report_constraint -all_violators}
alias sf set_flatten
alias ss set_structure
alias rco report_compile_options
alias cs compile -scan
alias csi compile -scan -incr -map high
alias h history
history keep 100
alias all_gone {remove_design -designs}
alias page_on {set sh_enable_page_mode true}
alias page_off {set sh_enable_page_mode false}
# specify directory for intermediate files from analyze
define_design_lib DEFAULT -path ./analyzed
# suppress Driving cell warning
suppress_message {UID-401}
########### Source Useful Tcl Procedures ###########
foreach _file [glob -nocomplain ./tcl_procs/*.tcl] {
source $_file
}
############# Enable line editing in 2004.12 ###########
set sh_enable_line_editing true
############# Setup the view utility ###########
proc view {args} {
redirect tmpfile1212 {uplevel $args}
# Without redirect, exec echos the PID of the new process to the screen
redirect /dev/null {exec ./tcl_procs/view.tk tmpfile1212 "$args" &}
}
alias vrt {view report_timing -nosplit}
alias vrtm {view report_timing -nosplit -delay min}
alias vman {view man}

34
synthDC/Makefile Executable file
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#
# Makefile for synthesis
#
NAME := synth
VARIANT := 18T_ms
default:
@echo "Basic synthesis procedure for OSU/HMC/UNLV:"
@echo " adapt Makefile to your liking..."
@echo
synth:
@sed -i 's/18T_ms/${VARIANT}/g' scripts/synth.tcl
@sed -i 's/18T_ms/${VARIANT}/g' .synopsys_dc.setup
@echo "DC Synthesis"
@mkdir -p reports
@mkdir -p mapped
dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(NAME).out
# @cp mapped/*.sdc ../../outputs/
# @cp mapped/*.vh ../../outputs/
# @sed -i 's/${VARIANT}/18T_ms/g' scripts/synth.tcl
# @sed -i 's/${VARIANT}/18T_ms/g' .synopsys_dc.setup
clean:
rm -rf alib-52 WORK mapped unmapped reports analyzed $(NAME).out
mkdir mapped unmapped reports
rm -f hdl/*
rm -f default.svf
rm -f command.log
rm -f filenames*.log

34
synthDC/README.md Normal file
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This subdirectory contains synthesis scripts for use with Synopsys
Design Compiler (DC). The scripts are separated into two distinct
sections: user and technology setups. The technology setup is found
in .synopsys_dc.setup file. Key items within this technology setup
are the location of the PDK and standard cell libraries.
We are using the Skywater Technology 130nm process for the synthesis.
The Oklahoma State University standard-cell libraries for this process
are located via the target_library keyword. There are currently three
versions of the standard-cell libraries available (see
http://stineje.github.io) for dowload locations. Currently, the TT 18
track OSU standard-cell library is utilized.
There are other useful elements within the technology setup file, as
well. These include user information as well as search path
information. Good tool flows usually rely on finding the right files
correctly and having a search path set correctly is importantly.
The user setup is found in two main areas. The scripts/ and hdl/
directories. The scripts directory contains a basic DC synthesis Tcl
script that is involved when synthesis is run. Please modify this
synth.tcl file to add information about PPA and information about your
design (e.g., top-level name, SV files). The SV is found within the
hdl/ subdirectory. Just put all your synthesis-friendly files in this
directory or allude to the correct location in the synthesis Tcl
script.
After synthesis completes, always check your synthesis log file that
will be called synth.log. Good tool flow starts and ends with
understanding what is happening during a specific part of the flow.
This can only be done through interpreting what the Electronic Design
Automation (EDA) tool is doing. So, always check this file for any
possible warnings or errors after completion. All output of synthesis
is found in the reports/ subdirectory.

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synthDC/scripts/synth.tcl Executable file
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#
# Main Synopsys Flow
# james.stine@okstate.edu 26 Jan 2022
#
# Config
set hdl_src "../pipelined/src"
eval file copy ${hdl_src}/../config/rv64gc/wally-config.vh {hdl/}
eval file copy ${hdl_src}/../config/rv64gc/wally-config.vh {reports/}
eval file copy [glob ${hdl_src}/../config/shared/*.vh] {hdl/}
eval file copy [glob ${hdl_src}/*/*.sv] {hdl/}
eval file copy [glob ${hdl_src}/*/flop/*.sv] {hdl/}
# Verilog files
set my_verilog_files [glob hdl/*]
# Set toplevel
set my_toplevel wallypipelinedcore
# Set number of significant digits
set report_default_significant_digits 6
# V(HDL) Unconnectoed Pins Output
set verilogout_show_unconnected_pins "true"
set vhdlout_show_unconnected_pins "true"
#
# Due to parameterized Verilog must use analyze/elaborate and not
# read_verilog/vhdl (change to pull in Verilog and/or VHDL)
#
define_design_lib WORK -path ./WORK
analyze -f sverilog -lib WORK $my_verilog_files
#
# Added if you had any VHDL
# analyze -f vhdl -lib WORK $my_vhdl_files
#
elaborate $my_toplevel -lib WORK
# Set the current_design
current_design $my_toplevel
link
# Reset all constraints
reset_design
# Set Frequency in [MHz] or [ps]
set my_clock_pin clk
set my_clk_freq_MHz 10
set my_period [expr 1000 / $my_clk_freq_MHz]
set my_uncertainty [expr .1 * $my_period]
# Create clock object
set find_clock [ find port [list $my_clock_pin] ]
if { $find_clock != [list] } {
echo "Found clock!"
set my_clk $my_clock_pin
create_clock -period $my_period $my_clk
set_clock_uncertainty $my_uncertainty [get_clocks $my_clk]
} else {
echo "Did not find clock! Design is probably combinational!"
set my_clk vclk
create_clock -period $my_period -name $my_clk
}
# Partitioning - flatten or hierarchically synthesize
#ungroup -flatten -simple_names { dp* }
#ungroup -flatten -simple_names { c* }
#ungroup -all -flatten -simple_names
# Set input pins except clock
set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]]
# Specifies delays be propagated through the clock network
set_propagated_clock [get_clocks $my_clk]
# Setting constraints on input ports
set_driving_cell -lib_cell sky130_osu_sc_18T_ms__dff_1 -pin Q $all_in_ex_clk
# Set input/output delay
set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk
set_output_delay 0.0 -max -clock $my_clk [all_outputs]
# Setting load constraint on output ports
set_load [expr [load_of sky130_osu_sc_18T_ms_TT_1P8_25C.ccs/sky130_osu_sc_18T_ms__dff_1/D] * 1] [all_outputs]
# Set the wire load model
set_wire_load_mode "top"
# Attempt Area Recovery - if looking for minimal area
# set_max_area 2000
# Set fanout
set_max_fanout 6 $all_in_ex_clk
# Fix hold time violations
set_fix_hold [all_clocks]
# Deal with constants and buffers to isolate ports
set_fix_multiple_port_nets -all -buffer_constants
# setting up the group paths to find out the required timings
#group_path -name OUTPUTS -to [all_outputs]
#group_path -name INPUTS -from [all_inputs]
#group_path -name COMBO -from [all_inputs] -to [all_outputs]
# Save Unmapped Design
set filename [format "%s%s%s" "unmapped/" $my_toplevel ".ddc"]
write_file -format ddc -hierarchy -o $filename
# Compile statements - either compile or compile_ultra
compile -scan -incr -map_effort low
# compile_ultra -no_seq_output_inversion -no_boundary_optimization
# Eliminate need for assign statements (yuck!)
set verilogout_no_tri true
set verilogout_equation false
# setting to generate output files
set write_v 1 ;# generates structual netlist
set write_sdc 1 ;# generates synopsys design constraint file for p&r
set write_ddc 1 ;# compiler file in ddc format
set write_sdf 1 ;# sdf file for backannotated timing sim
set write_pow 1 ;# genrates estimated power report
set write_rep 1 ;# generates estimated area and timing report
set write_cst 1 ;# generate report of constraints
set write_hier 1 ;# generate hierarchy report
# Report Constraint Violators
set filename [format "%s%s%s" "reports/" $my_toplevel "_constraint_all_violators.rpt"]
redirect $filename {report_constraint -all_violators}
# Check design
redirect reports/check_design.rpt { check_design }
# Report Final Netlist (Hierarchical)
set filename [format "%s%s%s" "mapped/" $my_toplevel ".vh"]
write_file -f verilog -hierarchy -output $filename
set filename [format "%s%s%s" "mapped/" $my_toplevel ".sdc"]
write_sdc $filename
set filename [format "%s%s%s" "mapped/" $my_toplevel ".ddc"]
write_file -format ddc -hierarchy -o $filename
set filename [format "%s%s%s" "mapped/" $my_toplevel ".sdf"]
write_sdf $filename
# QoR
set filename [format "%s%s%s" "reports/" $my_toplevel "_qor.rep"]
redirect $filename { report_qor }
# Report Timing
set filename [format "%s%s%s" "reports/" $my_toplevel "_reportpath.rep"]
redirect $filename { report_path_group }
set filename [format "%s%s%s" "reports/" $my_toplevel "_report_clock.rep"]
redirect $filename { report_clock }
set filename [format "%s%s%s" "reports/" $my_toplevel "_timing.rep"]
redirect $filename { report_timing -capacitance -transition_time -nets -nworst 1 }
set filename [format "%s%s%s" "reports/" $my_toplevel "_min_timing.rep"]
redirect $filename { report_timing -delay min }
set filename [format "%s%s%s" "reports/" $my_toplevel "_area.rep"]
redirect $filename { report_area -hierarchy -nosplit -physical -designware}
set filename [format "%s%s%s" "reports/" $my_toplevel "_cell.rep"]
redirect $filename { report_cell [get_cells -hier *] }
set filename [format "%s%s%s" "reports/" $my_toplevel "_power.rep"]
redirect $filename { report_power }
set filename [format "%s%s%s" "reports/" $my_toplevel "_constraint.rep"]
redirect $filename { report_constraint }
set filename [format "%s%s%s" "reports/" $my_toplevel "_hier.rep"]
redirect $filename { report_hierarchy }
# Quit
quit

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synthDC/scripts/synth.tcl~ Executable file
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#
# Main Synopsys Flow
# james.stine@okstate.edu 26 Jan 2022
#
# Config
set hdl_src "../pipelined/src"
eval file copy ${hdl_src}/../config/rv64gc/wally-config.vh {hdl/}
eval file copy ${hdl_src}/../config/rv64gc/wally-config.vh {reports/}
eval file copy [glob ${hdl_src}/../config/shared/*.vh] {hdl/}
eval file copy [glob ${hdl_src}/*/*.sv] {hdl/}
eval file copy [glob ${hdl_src}/*/flop/*.sv] {hdl/}
# Verilog files
set my_verilog_files [glob hdl/*]
# Set toplevel
set my_toplevel wallypipelinedcore
# Set number of significant digits
set report_default_significant_digits 6
# V(HDL) Unconnectoed Pins Output
set verilogout_show_unconnected_pins "true"
set vhdlout_show_unconnected_pins "true"
#
# Due to parameterized Verilog must use analyze/elaborate and not
# read_verilog/vhdl (change to pull in Verilog and/or VHDL)
#
define_design_lib WORK -path ./WORK
analyze -f sverilog -lib WORK $my_verilog_files
#
# Added if you had any VHDL
# analyze -f vhdl -lib WORK $my_vhdl_files
#
elaborate $my_toplevel -lib WORK
# Set the current_design
current_design $my_toplevel
link
# Reset all constraints
reset_design
# Set Frequency in [MHz] or [ps]
set my_clock_pin clk
set my_clk_freq_MHz 25
set my_period [expr 1000 / $my_clk_freq_MHz]
set my_uncertainty [expr .1 * $my_period]
# Create clock object
set find_clock [ find port [list $my_clock_pin] ]
if { $find_clock != [list] } {
echo "Found clock!"
set my_clk $my_clock_pin
create_clock -period $my_period $my_clk
set_clock_uncertainty $my_uncertainty [get_clocks $my_clk]
} else {
echo "Did not find clock! Design is probably combinational!"
set my_clk vclk
create_clock -period $my_period -name $my_clk
}
# Partitioning - flatten or hierarchically synthesize
#ungroup -flatten -simple_names { dp* }
#ungroup -flatten -simple_names { c* }
#ungroup -all -flatten -simple_names
# Set input pins except clock
set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]]
# Specifies delays be propagated through the clock network
set_propagated_clock [get_clocks $my_clk]
# Setting constraints on input ports
set_driving_cell -lib_cell sky130_osu_sc_18T_ms__dff_1 -pin Q $all_in_ex_clk
# Set input/output delay
set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk
set_output_delay 0.0 -max -clock $my_clk [all_outputs]
# Setting load constraint on output ports
set_load [expr [load_of sky130_osu_sc_18T_ms_TT_1P8_25C.ccs/sky130_osu_sc_18T_ms__dff_1/D] * 1] [all_outputs]
# Set the wire load model
set_wire_load_mode "top"
# Attempt Area Recovery - if looking for minimal area
# set_max_area 2000
# Set fanout
set_max_fanout 6 $all_in_ex_clk
# Fix hold time violations
set_fix_hold [all_clocks]
# Deal with constants and buffers to isolate ports
set_fix_multiple_port_nets -all -buffer_constants
# setting up the group paths to find out the required timings
#group_path -name OUTPUTS -to [all_outputs]
#group_path -name INPUTS -from [all_inputs]
#group_path -name COMBO -from [all_inputs] -to [all_outputs]
# Save Unmapped Design
set filename [format "%s%s%s" "unmapped/" $my_toplevel ".ddc"]
write_file -format ddc -hierarchy -o $filename
# Compile statements - either compile or compile_ultra
compile -scan -incr -map_effort high
# compile_ultra -no_seq_output_inversion -no_boundary_optimization
# Eliminate need for assign statements (yuck!)
set verilogout_no_tri true
set verilogout_equation false
# setting to generate output files
set write_v 1 ;# generates structual netlist
set write_sdc 1 ;# generates synopsys design constraint file for p&r
set write_ddc 1 ;# compiler file in ddc format
set write_sdf 1 ;# sdf file for backannotated timing sim
set write_pow 1 ;# genrates estimated power report
set write_rep 1 ;# generates estimated area and timing report
set write_cst 1 ;# generate report of constraints
set write_hier 1 ;# generate hierarchy report
# Report Constraint Violators
set filename [format "%s%s%s" "reports/" $my_toplevel "_constraint_all_violators.rpt"]
redirect $filename {report_constraint -all_violators}
# Check design
redirect reports/check_design.rpt { check_design }
# Report Final Netlist (Hierarchical)
set filename [format "%s%s%s" "mapped/" $my_toplevel ".vh"]
write_file -f verilog -hierarchy -output $filename
set filename [format "%s%s%s" "mapped/" $my_toplevel ".sdc"]
write_sdc $filename
set filename [format "%s%s%s" "mapped/" $my_toplevel ".ddc"]
write_file -format ddc -hierarchy -o $filename
set filename [format "%s%s%s" "mapped/" $my_toplevel ".sdf"]
write_sdf $filename
# QoR
set filename [format "%s%s%s" "reports/" $my_toplevel "_qor.rep"]
redirect $filename { report_qor }
# Report Timing
set filename [format "%s%s%s" "reports/" $my_toplevel "_reportpath.rep"]
redirect $filename { report_path_group }
set filename [format "%s%s%s" "reports/" $my_toplevel "_report_clock.rep"]
redirect $filename { report_clock }
set filename [format "%s%s%s" "reports/" $my_toplevel "_timing.rep"]
redirect $filename { report_timing -capacitance -transition_time -nets -nworst 1 }
set filename [format "%s%s%s" "reports/" $my_toplevel "_min_timing.rep"]
redirect $filename { report_timing -delay min }
set filename [format "%s%s%s" "reports/" $my_toplevel "_area.rep"]
redirect $filename { report_area -hierarchy -nosplit -physical -designware}
set filename [format "%s%s%s" "reports/" $my_toplevel "_cell.rep"]
redirect $filename { report_cell [get_cells -hier *] }
set filename [format "%s%s%s" "reports/" $my_toplevel "_power.rep"]
redirect $filename { report_power }
set filename [format "%s%s%s" "reports/" $my_toplevel "_constraint.rep"]
redirect $filename { report_constraint }
set filename [format "%s%s%s" "reports/" $my_toplevel "_hier.rep"]
redirect $filename { report_hierarchy }
# Quit
quit