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busybear: start adding ram

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This commit is contained in:
Noah Boorstin 2021-02-23 22:01:23 +00:00
parent d5e7a8a4cf
commit 00605864fc
2 changed files with 45 additions and 13 deletions
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2
wally-pipelined/regression/wally-busybear.do
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@ -48,6 +48,8 @@ add wave /testbench_busybear/lastInstrF
add wave /testbench_busybear/speculative add wave /testbench_busybear/speculative
add wave /testbench_busybear/lastPC2 add wave /testbench_busybear/lastPC2
add wave -divider add wave -divider
add wave -hex /testbench_busybear/readPC
add wave -hex /testbench_busybear/readRAM
#add wave -hex /testbench_busybear/dut/hart/priv/csr/MTVEC_REG #add wave -hex /testbench_busybear/dut/hart/priv/csr/MTVEC_REG
#add wave -hex /testbench_busybear/dut/hart/priv/csr/MSTATUS_REG #add wave -hex /testbench_busybear/dut/hart/priv/csr/MSTATUS_REG
#add wave -hex /testbench_busybear/dut/hart/priv/csr/SCOUNTEREN_REG #add wave -hex /testbench_busybear/dut/hart/priv/csr/SCOUNTEREN_REG

56
wally-pipelined/testbench/testbench-busybear.sv
View File

@ -140,18 +140,18 @@ module testbench_busybear();
if ($time == 0) begin if ($time == 0) begin
scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected); scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
if (dut.hart.ieu.dp.regf.rf[i] != regExpected) begin if (dut.hart.ieu.dp.regf.rf[i] != regExpected) begin
$display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected); $display("%0t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
`ERROR `ERROR
end end
end else begin end else begin
scan_file_rf = $fscanf(data_file_rf, "%d\n", regNumExpected); scan_file_rf = $fscanf(data_file_rf, "%d\n", regNumExpected);
scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected); scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
if (i != regNumExpected) begin if (i != regNumExpected) begin
$display("%t ps, instr %0d: wrong register changed: %0d, %0d expected", $time, instrs, i, regNumExpected); $display("%0t ps, instr %0d: wrong register changed: %0d, %0d expected", $time, instrs, i, regNumExpected);
`ERROR `ERROR
end end
if (~equal(dut.hart.ieu.dp.regf.rf[i],regExpected, 0)) begin if (~equal(dut.hart.ieu.dp.regf.rf[i],regExpected, 0)) begin
$display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected); $display("%0t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
`ERROR `ERROR
end end
if (dut.hart.ieu.dp.regf.rf[i] !== regExpected) begin if (dut.hart.ieu.dp.regf.rf[i] !== regExpected) begin
@ -162,6 +162,27 @@ module testbench_busybear();
end end
end end
endgenerate endgenerate
`define MAX_RAM 'h8000000
logic [`XLEN-1:0] RAM[`MAX_RAM:0];
logic [`XLEN-1:0] readRAM, readPC;
integer RAMAdr, RAMPC;
assign RAMAdr = HADDR - 'h80000000;
assign RAMPC = PCF - 'h80000000;
always @(HWDATA or HADDR or HSIZE or HWRITE or dut.hart.MemRWM[1]) begin
if ((HWRITE || dut.hart.MemRWM[1]) && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin
if (HWRITE) begin
RAM[RAMAdr] = HWDATA;
end else begin
readRAM = RAM[RAMAdr];
end
end
end
always @(PCF) begin
if (PCF >= 'h80000000 && PCF <= 'h87FFFFFF) begin
readPC = RAM[RAMPC];
end
end
logic [`XLEN-1:0] readAdrExpected; logic [`XLEN-1:0] readAdrExpected;
// this might need to change // this might need to change
@ -175,7 +196,12 @@ module testbench_busybear();
scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA); scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA);
#1; #1;
if (~equal(HADDR,readAdrExpected,4)) begin if (~equal(HADDR,readAdrExpected,4)) begin
$display("%t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrExpected); $display("%0t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrExpected);
`ERROR
end
if (HRDATA != readRAM && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin
$display("warning %0t ps, instr %0d: HRDATA does not equal readRAM: %x, %x from address %x", $time, instrs, HRDATA, readRAM, HADDR);
warningCount += 1;
`ERROR `ERROR
end end
end end
@ -183,7 +209,7 @@ module testbench_busybear();
logic [`XLEN-1:0] writeDataExpected, writeAdrExpected; logic [`XLEN-1:0] writeDataExpected, writeAdrExpected;
// this might need to change // this might need to change
always @(HWDATA or HADDR or HSIZE) begin always @(HWDATA or HADDR or HSIZE or HWRITE) begin
#1; #1;
if (HWRITE) begin if (HWRITE) begin
if($feof(data_file_memW)) begin if($feof(data_file_memW)) begin
@ -193,11 +219,11 @@ module testbench_busybear();
scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected); scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected);
scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected); scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected);
if (writeDataExpected != HWDATA) begin if (writeDataExpected != HWDATA) begin
$display("%t ps, instr %0d: HWDATA does not equal writeDataExpected: %x, %x", $time, instrs, HWDATA, writeDataExpected); $display("%0t ps, instr %0d: HWDATA does not equal writeDataExpected: %x, %x", $time, instrs, HWDATA, writeDataExpected);
`ERROR `ERROR
end end
if (~equal(writeAdrExpected,HADDR,1)) begin if (~equal(writeAdrExpected,HADDR,1)) begin
$display("%t ps, instr %0d: HADDR does not equal writeAdrExpected: %x, %x", $time, instrs, HADDR, writeAdrExpected); $display("%0t ps, instr %0d: HADDR does not equal writeAdrExpected: %x, %x", $time, instrs, HADDR, writeAdrExpected);
`ERROR `ERROR
end end
end end
@ -226,17 +252,17 @@ module testbench_busybear();
scan_file_csr = $fscanf(data_file_csr, "%s\n", CSR); \ scan_file_csr = $fscanf(data_file_csr, "%s\n", CSR); \
scan_file_csr = $fscanf(data_file_csr, "%x\n", expected``CSR``); \ scan_file_csr = $fscanf(data_file_csr, "%x\n", expected``CSR``); \
if(CSR.icompare(`"CSR`")) begin \ if(CSR.icompare(`"CSR`")) begin \
$display("%t ps, instr %0d: %s changed, expected %s", $time, instrs, `"CSR`", CSR); \ $display("%0t ps, instr %0d: %s changed, expected %s", $time, instrs, `"CSR`", CSR); \
end \ end \
if(``PATH``.``CSR``_REGW != ``expected``CSR) begin \ if(``PATH``.``CSR``_REGW != ``expected``CSR) begin \
$display("%t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", CSR, ``PATH``.``CSR``_REGW, ``expected``CSR); \ $display("%0t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", CSR, ``PATH``.``CSR``_REGW, ``expected``CSR); \
`ERROR \ `ERROR \
end \ end \
end else begin \ end else begin \
for(integer j=0; j<totalCSR; j++) begin \ for(integer j=0; j<totalCSR; j++) begin \
if(!StartCSRname[j].icompare(`"CSR`")) begin \ if(!StartCSRname[j].icompare(`"CSR`")) begin \
if(``PATH``.``CSR``_REGW != StartCSRexpected[j]) begin \ if(``PATH``.``CSR``_REGW != StartCSRexpected[j]) begin \
$display("%t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", StartCSRname[j], ``PATH``.``CSR``_REGW, StartCSRexpected[j]); \ $display("%0t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", StartCSRname[j], ``PATH``.``CSR``_REGW, StartCSRexpected[j]); \
`ERROR \ `ERROR \
end \ end \
end \ end \
@ -299,11 +325,11 @@ module testbench_busybear();
// then expected PC value // then expected PC value
scan_file_PCW = $fscanf(data_file_PCW, "%x\n", PCWExpected); scan_file_PCW = $fscanf(data_file_PCW, "%x\n", PCWExpected);
if(~equal(dut.hart.ifu.PCW,PCWExpected,2)) begin if(~equal(dut.hart.ifu.PCW,PCWExpected,2)) begin
$display("%t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, dut.hart.ifu.PCW, PCWExpected); $display("%0t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, dut.hart.ifu.PCW, PCWExpected);
`ERROR `ERROR
end end
//if(it.InstrW != InstrWExpected) begin //if(it.InstrW != InstrWExpected) begin
// $display("%t ps, instr %0d: InstrW does not equal InstrW expected: %x, %x", $time, instrs, it.InstrW, InstrWExpected); // $display("%0t ps, instr %0d: InstrW does not equal InstrW expected: %x, %x", $time, instrs, it.InstrW, InstrWExpected);
//end //end
end end
end end
@ -372,9 +398,13 @@ module testbench_busybear();
//check things! //check things!
if ((~speculative) && (~equal(PCF,pcExpected,3))) begin if ((~speculative) && (~equal(PCF,pcExpected,3))) begin
$display("%t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, PCF, pcExpected); $display("%0t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, PCF, pcExpected);
`ERROR `ERROR
end end
if (readPC != InstrF) begin
$display("%0t ps, instr %0d: readPC does not equal InstrF: %x, %x", $time, instrs, readPC, InstrF);
warningCount += 1;
end
end end
end end