forked from Github_Repos/cvw
52 lines
2.0 KiB
Systemverilog
52 lines
2.0 KiB
Systemverilog
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///////////////////////////////////////////
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// arrs.sv
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//
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// Written: Ross Thompson ross1728@gmail.com
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// Modified: November 12, 2021
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//
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// Purpose: resets are typically asynchronous but need to be synchronized to
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// a clock to prevent changing in the invalid window clock edge.
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// arrs takes in the asynchronous reset and outputs an asynchronous
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// rising edge, but then syncs the falling edge to the posedge clk.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module arrs
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(input logic clk,
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input logic areset,
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output logic reset);
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logic metaStable;
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logic resetB;
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always_ff @(posedge clk , posedge areset) begin
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if(areset) begin
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metaStable <= 1'b0;
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resetB <= 1'b0;
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end else begin
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metaStable <= 1'b1;
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resetB <= metaStable;
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end
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end
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assign reset = ~resetB;
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endmodule
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