forked from Github_Repos/cvw
1185 lines
50 KiB
C
1185 lines
50 KiB
C
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#include "encoding.h"
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// TODO the following should come from the YAML.
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#ifndef NUM_SPECD_INTCAUSES
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#define NUM_SPECD_INTCAUSES 16
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#endif
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//#define RVTEST_FIXED_LEN
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#ifndef UNROLLSZ
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#define UNROLLSZ 5
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#endif
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// #ifndef rvtest_gpr_save
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// #define rvtest_gpr_save
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// #endif
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#define TEST_CASE_1
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//-----------------------------------------------------------------------
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// RV Arch Test Macros
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//-----------------------------------------------------------------------
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#ifndef RVMODEL_SET_MSW_INT
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#warning "RVMODEL_SET_MSW_INT is not defined by target. Declaring as empty macro"
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#define RVMODEL_SET_MSW_INT
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#endif
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#ifndef RVMODEL_CLEAR_MSW_INT
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#warning "RVMODEL_CLEAR_MSW_INT is not defined by target. Declaring as empty macro"
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#define RVMODEL_CLEAR_MSW_INT
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#endif
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#ifndef RVMODEL_CLEAR_MTIMER_INT
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#warning "RVMODEL_CLEAR_MTIMER_INT is not defined by target. Declaring as empty macro"
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#define RVMODEL_CLEAR_MTIMER_INT
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#endif
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#ifndef RVMODEL_CLEAR_MEXT_INT
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#warning "RVMODEL_CLEAR_MEXT_INT is not defined by target. Declaring as empty macro"
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#define RVMODEL_CLEAR_MEXT_INT
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#endif
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#ifdef RVTEST_FIXED_LEN
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#define LI(reg, val)\
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.option push;\
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.option norvc;\
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.align UNROLLSZ;\
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li reg,val;\
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.align UNROLLSZ;\
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.option pop;
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#define LA(reg, val)\
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.option push;\
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.option norvc;\
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.align UNROLLSZ;\
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la reg,val;\
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.align UNROLLSZ;\
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.option pop;
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#else
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#define LI(reg,val);\
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.option push;\
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.option norvc;\
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li reg,val;\
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.option pop;
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#define LA(reg,val);\
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.option push;\
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.option norvc;\
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la reg,val;\
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.option pop;
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#endif
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#if XLEN==64
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#define SREG sd
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#define LREG ld
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#define REGWIDTH 8
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#define MASK 0xFFFFFFFFFFFFFFFF
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#else
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#if XLEN==32
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#define SREG sw
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#define LREG lw
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#define REGWIDTH 4
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#define MASK 0xFFFFFFFF
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#endif
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#endif
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#if FLEN==64
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#define FLREG fld
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#define FSREG fsd
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#define FREGWIDTH 8
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#else
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#if FLEN==32
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#define FLREG flw
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#define FSREG fsw
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#define FREGWIDTH 4
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#endif
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#endif
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#if XLEN==64
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#if FLEN==32
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#define SREG sw
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#define LREG lW
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#define REGWIDTH 4
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#define MASK 0xFFFFFFFF
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#endif
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#endif
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#define MMODE_SIG 3
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#define RLENG (REGWIDTH<<3)
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#define RVTEST_ISA(_STR)
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#ifndef DATA_REL_TVAL_MSK
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#define DATA_REL_TVAL_MSK 0x0F05 << (REGWIDTH*8-16)
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#endif
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#ifndef CODE_REL_TVAL_MSK
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#define CODE_REL_TVAL_MSK 0xD008 << (REGWIDTH*8-16)
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#endif
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// ----------------------------------- CODE BEGIN w/ TRAP HANDLER START ------------------------ //
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.macro RVTEST_CODE_BEGIN
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.align UNROLLSZ
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.section .text.init;
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.globl rvtest_init; \
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rvtest_init:
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#ifdef rvtest_mtrap_routine
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LA(x1, rvtest_trap_prolog );
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jalr ra, x1
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rvtest_prolog_done:
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#endif
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LI (x1, (0xFEEDBEADFEEDBEAD & MASK));
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LI (x2, (0xFF76DF56FF76DF56 & MASK));
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LI (x3, (0x7FBB6FAB7FBB6FAB & MASK));
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LI (x4, (0xBFDDB7D5BFDDB7D5 & MASK));
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LA (x5, rvtest_code_begin);
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LA (x6, rvtest_data_begin);
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LI (x7, (0xB7FBB6FAB7FBB6FA & MASK));
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LI (x8, (0x5BFDDB7D5BFDDB7D & MASK));
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LI (x9, (0xADFEEDBEADFEEDBE & MASK));
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LI (x10, (0x56FF76DF56FF76DF & MASK));
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LI (x11, (0xAB7FBB6FAB7FBB6F & MASK));
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LI (x12, (0xD5BFDDB7D5BFDDB7 & MASK));
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LI (x13, (0xEADFEEDBEADFEEDB & MASK));
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LI (x14, (0xF56FF76DF56FF76D & MASK));
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LI (x15, (0xFAB7FBB6FAB7FBB6 & MASK));
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#ifndef RVTEST_E
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LI (x16, (0x7D5BFDDB7D5BFDDB & MASK));
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LI (x17, (0xBEADFEEDBEADFEED & MASK));
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LI (x18, (0xDF56FF76DF56FF76 & MASK));
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LI (x19, (0x6FAB7FBB6FAB7FBB & MASK));
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LI (x20, (0xB7D5BFDDB7D5BFDD & MASK));
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LI (x21, (0xDBEADFEEDBEADFEE & MASK));
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LI (x22, (0x6DF56FF76DF56FF7 & MASK));
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LI (x23, (0xB6FAB7FBB6FAB7FB & MASK));
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LI (x24, (0xDB7D5BFDDB7D5BFD & MASK));
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LI (x25, (0xEDBEADFEEDBEADFE & MASK));
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LI (x26, (0x76DF56FF76DF56FF & MASK));
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LI (x27, (0xBB6FAB7FBB6FAB7F & MASK));
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LI (x28, (0xDDB7D5BFDDB7D5BF & MASK));
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LI (x29, (0xEEDBEADFEEDBEADF & MASK));
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LI (x30, (0xF76DF56FF76DF56F & MASK));
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LI (x31, (0xFBB6FAB7FBB6FAB7 & MASK));
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#endif
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.globl rvtest_code_begin
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rvtest_code_begin:
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.endm
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// --------------------------------- CODE BEGIN w/ TRAP HANDLER END -----------------------------//
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.macro RVTEST_CODE_END
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.align 4;
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.global rvtest_code_end
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rvtest_code_end:
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#ifdef rvtest_mtrap_routine
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.option push
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.option norvc
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j exit_cleanup
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rvtest_trap_prolog:
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/******************************************************************************/
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/**** Prolog, to be run before any tests ****/
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/**** #include 1 copy of this per mode in rvmodel_boot code? ****/
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/**** ------------------------------------------------------------------- ****/
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/**** if xTVEC isn't completely RW, then we need to change the code at its ****/
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/**** target. The entire trap trampoline and mtrap handler replaces the ****/
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/**** area pointed to by mtvec, after saving its original contents first. ****/
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/**** If it isn't possible to fully write that area, restore and fail. ****/
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/******************************************************************************/
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//trap_handler_prolog; enter with t1..t6 available
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init_mscratch:
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la t1, trapreg_sv
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csrrw t1, CSR_MSCRATCH, t1 // swap old mscratch. mscratch not points to trapreg_sv
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la t2, mscratch_save
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SREG t1, 0(t2) // save old mscratch in mscratch_save region
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csrr t1, CSR_MSCRATCH // read the trapreg_sv address
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LA( t2, mtrap_sigptr ) // locate the start of the trap signature
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SREG t2, 0(t1) // save mtrap_sigptr at first location of trapreg_sv
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init_mtvec:
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la t1, mtrampoline
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la t4, mtvec_save
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csrrw t2, CSR_MTVEC, t1 // swap mtvec and trap_trampoline
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SREG t2, 0(t4) // save orig mtvec
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csrr t3, CSR_MTVEC // now read new_mtval back
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beq t3, t1, rvtest_prolog_done // if mtvec==trap_trampoline, mtvec is writable, continue
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/****************************************************************/
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/**** fixed mtvec, can't move it so move trampoline instead ****/
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/**** t1=trampoline, t2=oldmtvec, t3=save area, t4=save end ****/
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/****************************************************************/
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// t2 = dut's original mtvec setting
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// t1 = mtrampoline address
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init_tramp: /**** copy trampoline at mtvec tgt ****/
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csrw CSR_MTVEC, t2 // restore orig mtvec, will now attemp to copy trampoline to it
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la t3, tramptbl_sv // addr of save area
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addi t4, t3, NUM_SPECD_INTCAUSES*4 // end of save area
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overwrite_tt: // now build new trampoline table with offsets base from curr mtvec
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lw t6, 0(t2) // get original mtvec target
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sw t6, 0(t3) // save it
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lw t5, 0(t1) // get trampoline src
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sw t5, 0(t2) // overwrite mtvec target
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lw t6, 0(t2) // rd it back to make sure it was written
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bne t6, t5, resto_tramp // table isn't fully writable, restore and give up
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addi t1, t1, 4 // next src index
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addi t2, t2, 4 // next tgt index
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addi t3, t3, 4 // next save index
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bne t3, t4, overwrite_tt // not done, loop
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j rvtest_prolog_done
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resto_tramp: // vector table not writeable, restore
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LREG t1, 16(t4) // load mscratch_SAVE at fixed offset from table end
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csrw CSR_MSCRATCH, t1 // restore mscratch
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LREG t4, 8(t4) // load mtvec_SAVE (used as end of loop marker)
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resto_loop: // goes backwards, t2= dest vec tbl ptr, t3=src save area ptr, t4=vec tbl begin
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lw t6, 0(t3) // read saved tgt entry
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sw t6, 0(t2) // restore original tgt
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addi t2, t2, -4 // prev tgt index
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addi t3, t3, -4 // prev save index
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bne t2, t4, resto_loop // didn't restore to begining yet, loop
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j rvtest_end // failure to replace trampoline
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#define mhandler \
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csrrw sp, CSR_MSCRATCH, sp; \
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SREG t6, 6*REGWIDTH(sp); \
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jal t6, common_prolog;
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/**********************************************************************/
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/**** This is the entry point for all m-modetraps, vectored or not.****/
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/**** At entry, mscratch will contain a pointer to a scratch area. ****/
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/**** This is an array of branches at 4B intevals that spreads out ****/
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/**** to an array of 32B mhandler macros for specd int causes, and ****/
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/**** to a return for anything above that (which causes a mismatch)****/
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/**********************************************************************/
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mtrampoline: // 64 or 32 entry table
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value = 0
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.rept NUM_SPECD_INTCAUSES // located at each possible int vectors
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j mtrap_handler + 12*(value) //offset < +/- 1MB
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value = value + 1
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.endr
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.rept RLENG-NUM_SPECD_INTCAUSES // fill at each impossible entry
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mret
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.endr
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mtrap_handler: /* after executing, sp points to temp save area, t4 is PC */
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.rept NUM_SPECD_INTCAUSES
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mhandler
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.endr
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common_prolog:
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la t5, common_mhandler
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jr t5
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/*********************************************************************/
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/**** common code for all ints & exceptions, will fork to handle ****/
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/**** each separately. The common handler first stores trap mode+ ****/
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/**** vector, and mcause signatures. All traps have 4wd sigs, but ****/
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/**** sw and timer ints only store 3 of the 4. ****/
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/**** sig offset Exception ExtInt SWInt TimerInt ****/
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/**** 0: tval IntID -1 -1 ****/
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/**** 4: mepc mip mip mip ****/
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/**** 8: <---------------------- mcause -------------> ****/
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/**** 12: <--------------------- Vect+mode ----------> ****/
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/*********************************************************************/
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/* in general, CSRs loaded in t2, addresses into t3 */
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common_mhandler: /* enter with link in t6 */
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SREG t5, 5*REGWIDTH(sp)
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SREG t4, 4*REGWIDTH(sp)
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SREG t3, 3*REGWIDTH(sp)
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SREG t2, 2*REGWIDTH(sp)
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SREG t1, 1*REGWIDTH(sp) /* save other temporaries */
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LREG t1, 0(sp) /* load trap sig pointer (runs backwards from DATA_END) */
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LA( t3, mtrampoline)
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sub t2, t6, t3 /* reloc “link” to 0..63 to show which int vector was taken */
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addi t2, t2, MMODE_SIG /* insert mode# into 1:0 */
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SREG t2, 0*REGWIDTH(t1) /* save 1st sig value, (vect, trapmode) */
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sv_mcause:
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csrr t2, CSR_MCAUSE
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SREG t2, 1*REGWIDTH(t1) /* save 2nd sig value, (mcause) */
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bltz t2, common_mint_handler /* this is a interrupt, not a trap */
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|||
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/********************************************************************/
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/**** This is the exceptions specific code, storing relative mepc****/
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|||
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/**** & relative tval signatures. tval is relocated by code or ****/
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|||
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/**** data start, or 0 depending on mcause. mepc signature value ****/
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|||
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/**** is relocated by code start, and restored adjusted depending****/
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/**** on op alignment so trapped op isn't re-executed. ****/
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|||
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/********************************************************************/
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common_mexcpt_handler:
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csrr t2, CSR_MEPC
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sv_mepc:
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|||
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LA( t3, rvtest_prolog_done) /* offset to compensate for different loader offsets */
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|||
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sub t4, t2, t3 /* convert mepc to rel offset of beginning of test*/
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|||
|
|
SREG t4, 2*REGWIDTH(t1) /* save 3rd sig value, (rel mepc) into trap signature area */
|
|||
|
|
adj_mepc: //adj mepc so there is padding after op, and its 8B aligned
|
|||
|
|
andi t4, t2, 0x2 /* set to 2 if mepc was misaligned */
|
|||
|
|
sub t2, t2, t4 /* adjust mepc to prev 4B alignment */
|
|||
|
|
addi t2, t2, 0x8 /* adjust mepc, so it skips past the op, has padding & is 4B aligned */
|
|||
|
|
csrw CSR_MEPC, t2 /* restore adjusted value, has 1,2, or 3 bytes of padding */
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* calculate relative mtval if it’s an address (by code_begin or data_begin amt) */
|
|||
|
|
/* note that masks that determine this are implementation specific from YAML */
|
|||
|
|
|
|||
|
|
/* masks are bit reversed, so mcause==0 bit is in MSB (so different for RV32 and RV64) */
|
|||
|
|
|
|||
|
|
adj_mtval:
|
|||
|
|
csrr t2, CSR_MCAUSE /* code begin adjustment amount already in t3 */
|
|||
|
|
|
|||
|
|
LI(t4, CODE_REL_TVAL_MSK) /* trap#s 12, 3,1,0, -- adjust w/ code_begin */
|
|||
|
|
sll t4, t4, t2 /* put bit# in MSB */
|
|||
|
|
bltz t4, sv_mtval /* correct adjustment is code_begin in t3 */
|
|||
|
|
|
|||
|
|
LA( t3, mtrap_sigptr) /* adjustment assuming access is to signature region */
|
|||
|
|
LI(t4, DATA_REL_TVAL_MSK) /* trap#s not 14, 11..8, 2 adjust w/ data_begin */
|
|||
|
|
sll t4, t4, t2 /* put bit# in MSB */
|
|||
|
|
bgez t4, no_adj /* correct adjustment is data_begin in t3 */
|
|||
|
|
sigbound_chk:
|
|||
|
|
csrr t4, CSR_MTVAL /* do a bounds check on mtval */
|
|||
|
|
bge t3, t4, sv_mtval /* if mtval is greater than the rvmodel_data_begin then use that as anchor */
|
|||
|
|
LA( t3, rvtest_data_begin) /* else change anchor to rvtest_data_begin */
|
|||
|
|
blt t3, t4, sv_mtval /* before the signature, use data_begin adj */
|
|||
|
|
mv t4, t3 /* use sig relative adjust */
|
|||
|
|
no_adj:
|
|||
|
|
LI(t3, 0) /* else zero adjustment amt */
|
|||
|
|
|
|||
|
|
// For Illegal op handling
|
|||
|
|
addi t2, t2, -2 /* check if mcause==2 (illegal op) */
|
|||
|
|
bnez t2, sv_mtval /* not illegal op, no special treatment */
|
|||
|
|
csrr t2, CSR_MTVAL
|
|||
|
|
bnez t2, sv_mtval /* mtval isn’t zero, no special treatment */
|
|||
|
|
illop:
|
|||
|
|
LI(t5, 0x20000) /* get mprv mask */
|
|||
|
|
csrrs t5, CSR_MSTATUS, t5 /* set mprv while saving the old value */
|
|||
|
|
csrr t3, CSR_MEPC
|
|||
|
|
lhu t2, 0(t3) /* load 1st 16b of opc w/ old priv, endianess*/
|
|||
|
|
andi t4, t2, 0x3
|
|||
|
|
addi t4, t4, -0x3 /* does opcode[1:0]==0b11? (Meaning >16b op) */
|
|||
|
|
bnez t4, sv_mtval /* entire mtval is in tt2, adj amt will be set to zero */
|
|||
|
|
lhu t4, 2(t3)
|
|||
|
|
sll t4, t4, 16
|
|||
|
|
or t3, t2, t4 /* get 2nd hwd, align it & insert it into opcode */
|
|||
|
|
csrw CSR_MSTATUS, t5 /* restore mstatus */
|
|||
|
|
|
|||
|
|
/*******FIXME: this will not handle 48 or 64b opcodes in an RV64) ********/
|
|||
|
|
|
|||
|
|
sv_mtval:
|
|||
|
|
csrr t2, CSR_MTVAL
|
|||
|
|
sub t2, t2, t3 /* perform mtval adjust by either code or data position or zero*/
|
|||
|
|
SREG t2, 3*REGWIDTH(t1) /* save 4th sig value, (rel mtval) into trap signature area */
|
|||
|
|
|
|||
|
|
resto_rtn: /* restore and return */
|
|||
|
|
addi t1, t1,4*REGWIDTH /* adjust trap signature ptr (traps always save 4 words) */
|
|||
|
|
SREG t1, 0*REGWIDTH(sp) /* save updated trap sig pointer (pts to trap_sigptr */
|
|||
|
|
|
|||
|
|
LREG t1, 1*REGWIDTH(sp)
|
|||
|
|
LREG t2, 2*REGWIDTH(sp)
|
|||
|
|
LREG t3, 3*REGWIDTH(sp)
|
|||
|
|
LREG t4, 4*REGWIDTH(sp)
|
|||
|
|
LREG t5, 5*REGWIDTH(sp)
|
|||
|
|
LREG t6, 6*REGWIDTH(sp) /* restore temporaries */
|
|||
|
|
|
|||
|
|
csrrw sp, CSR_MSCRATCH, sp /* restore sp from scratch */
|
|||
|
|
mret
|
|||
|
|
|
|||
|
|
common_mint_handler: /* t1 has sig ptr, t2 has mcause */
|
|||
|
|
|
|||
|
|
LI(t3, 1)
|
|||
|
|
sll t3, t3, t2 /* create mask 1<<mcause */
|
|||
|
|
csrrc t4, CSR_MIP, t3 /* read, then attempt to clear int pend bit */
|
|||
|
|
csrrc t4, CSR_MIE, t3 /* read, then attempt to clear int pend bit */
|
|||
|
|
sv_mip: /* note: clear has no effect on MxIP */
|
|||
|
|
SREG t4, 2*REGWIDTH(t1) /* save 3rd sig value, (mip) */
|
|||
|
|
|
|||
|
|
/* case table branch to interrupt clearing code, depending on mcause */
|
|||
|
|
slli t2, t2, 3 /* convert mcause to 8B offset */
|
|||
|
|
LA( t3, clrint_tbl ) /* load jump table address */
|
|||
|
|
add t3, t3, t2 /* index into to it, load vector, then jump to it */
|
|||
|
|
LREG t3, 0(t3)
|
|||
|
|
jr t3
|
|||
|
|
|
|||
|
|
clr_sw_int:
|
|||
|
|
RVMODEL_CLEAR_MSW_INT
|
|||
|
|
j resto_rtn
|
|||
|
|
|
|||
|
|
clr_tmr_int:
|
|||
|
|
RVMODEL_CLEAR_MTIMER_INT
|
|||
|
|
j resto_rtn
|
|||
|
|
|
|||
|
|
clr_ext_int:
|
|||
|
|
RVMODEL_CLEAR_MEXT_INT
|
|||
|
|
SREG t3, -3*REGWIDTH(t1) /* save 4rd sig value, (intID) */
|
|||
|
|
j resto_rtn
|
|||
|
|
.align 3
|
|||
|
|
clrint_tbl:
|
|||
|
|
.dword resto_rtn /* int cause 0 is reserved, just return */
|
|||
|
|
.dword clr_sw_int /* int cause 1 Smode SW int */
|
|||
|
|
.dword resto_rtn /* int cause 2 is reserved, just return */
|
|||
|
|
.dword clr_sw_int /* int cause 3 Mmode SW int */
|
|||
|
|
.dword resto_rtn /* int cause 4 is reserved, just return */
|
|||
|
|
.dword clr_tmr_int /* int cause 5 Smode Tmr int */
|
|||
|
|
.dword resto_rtn /* int cause 6 is reserved, just return */
|
|||
|
|
.dword clr_tmr_int /* int cause 7 Mmode Tmr int */
|
|||
|
|
.dword resto_rtn /* int cause 8 is reserved, just return */
|
|||
|
|
.dword clr_ext_int /* int cause 9 Smode Ext int */
|
|||
|
|
.dword resto_rtn /* int cause A is reserved, just return */
|
|||
|
|
.dword clr_ext_int /* int cause B Mmode Ext int */
|
|||
|
|
.dword resto_rtn /* int cause C is reserved, just return */
|
|||
|
|
.dword resto_rtn /* int cause D is reserved, just return */
|
|||
|
|
.dword resto_rtn /* int cause E is reserved, just return */
|
|||
|
|
.dword resto_rtn /* int cause F is reserved, just return */
|
|||
|
|
.dword resto_rtn /* int cause 10 is reserved, just return */
|
|||
|
|
.dword resto_rtn /* int cause 11 is reserved, just return */
|
|||
|
|
.dword resto_rtn /* int cause 12 is reserved, just return */
|
|||
|
|
.dword resto_rtn /* int cause 13 is reserved, just return */
|
|||
|
|
.dword resto_rtn /* int cause 14 is reserved, just return */
|
|||
|
|
.dword resto_rtn /* int cause 15 is reserved, just return */
|
|||
|
|
.dword resto_rtn /* int cause 16 is reserved, just return */
|
|||
|
|
.dword resto_rtn /* int cause 17 is reserved, just return */
|
|||
|
|
.dword resto_rtn /* int cause 18 is reserved, just return */
|
|||
|
|
.dword resto_rtn /* int cause 19 is reserved, just return */
|
|||
|
|
.dword resto_rtn /* int cause 1A is reserved, just return */
|
|||
|
|
.dword resto_rtn /* int cause 1B is reserved, just return */
|
|||
|
|
.dword resto_rtn /* int cause 1C is reserved, just return */
|
|||
|
|
.dword resto_rtn /* int cause 1D is reserved, just return */
|
|||
|
|
.dword resto_rtn /* int cause 1E is reserved, just return */
|
|||
|
|
.dword resto_rtn /* int cause 1F is reserved, just return */
|
|||
|
|
|
|||
|
|
1: // xtvec_installed:
|
|||
|
|
ret
|
|||
|
|
|
|||
|
|
// ----------------------------------------------------------------------------------------------
|
|||
|
|
// ----------------------------------------------------------------------------------------------
|
|||
|
|
// ----------------------------------------------------------------------------------------------
|
|||
|
|
// ----------------------------------------------------------------------------------------------
|
|||
|
|
|
|||
|
|
exit_cleanup://COMPLIANCE_HALT should get here
|
|||
|
|
la t3, tramptbl_sv+ NUM_SPECD_INTCAUSES*4 // end of save area
|
|||
|
|
|
|||
|
|
la t5, mtvec_save
|
|||
|
|
LREG t1, 8(t5)
|
|||
|
|
csrw CSR_MSCRATCH, t1 // restore mscratch
|
|||
|
|
LREG t4, 0(t5) // load orig mtvec
|
|||
|
|
csrrw t2, CSR_MTVEC, t4 // restore mtvec (not redundant)
|
|||
|
|
bne t4, t2, 1f// if saved!=mtvec, done, else need to restore
|
|||
|
|
|
|||
|
|
addi t2, t4, NUM_SPECD_INTCAUSES*4 // start pt is end of vect area
|
|||
|
|
resto_vec: // goes backwards, t2= dest vec tbl ptr,
|
|||
|
|
// t3=src save area ptr, t4=vec tbl begin
|
|||
|
|
lw t6, 0(t3) // read saved tgt entry
|
|||
|
|
sw t6, 0(t2) // restore original tgt
|
|||
|
|
addi t2, t2, -4 // prev tgt index
|
|||
|
|
addi t3, t3, -4 // prev save index
|
|||
|
|
bne t2, t4, resto_vec // didn't get to end, continue
|
|||
|
|
1:
|
|||
|
|
rvtest_end:
|
|||
|
|
.option pop
|
|||
|
|
#endif
|
|||
|
|
#ifdef rvtest_gpr_save
|
|||
|
|
csrw CSR_MSCRATCH, x31 //save x31, get temp pointer
|
|||
|
|
LA(x31, gpr_save)
|
|||
|
|
SREG x0, 0*REGWIDTH(x31)
|
|||
|
|
SREG x1, 1*REGWIDTH(x31)
|
|||
|
|
SREG x2, 2*REGWIDTH(x31)
|
|||
|
|
SREG x3, 3*REGWIDTH(x31)
|
|||
|
|
SREG x4, 4*REGWIDTH(x31)
|
|||
|
|
SREG x5, 5*REGWIDTH(x31)
|
|||
|
|
SREG x6, 6*REGWIDTH(x31)
|
|||
|
|
SREG x7, 7*REGWIDTH(x31)
|
|||
|
|
SREG x8, 8*REGWIDTH(x31)
|
|||
|
|
SREG x9, 9*REGWIDTH(x31)
|
|||
|
|
SREG x10, 10*REGWIDTH(x31)
|
|||
|
|
SREG x11, 11*REGWIDTH(x31)
|
|||
|
|
SREG x12, 12*REGWIDTH(x31)
|
|||
|
|
SREG x13, 13*REGWIDTH(x31)
|
|||
|
|
SREG x14, 14*REGWIDTH(x31)
|
|||
|
|
SREG x15, 15*REGWIDTH(x31)
|
|||
|
|
SREG x16, 16*REGWIDTH(x31)
|
|||
|
|
SREG x17, 17*REGWIDTH(x31)
|
|||
|
|
SREG x18, 18*REGWIDTH(x31)
|
|||
|
|
SREG x19, 19*REGWIDTH(x31)
|
|||
|
|
SREG x20, 20*REGWIDTH(x31)
|
|||
|
|
SREG x21, 21*REGWIDTH(x31)
|
|||
|
|
SREG x22, 22*REGWIDTH(x31)
|
|||
|
|
SREG x23, 23*REGWIDTH(x31)
|
|||
|
|
SREG x24, 24*REGWIDTH(x31)
|
|||
|
|
SREG x25, 25*REGWIDTH(x31)
|
|||
|
|
SREG x26, 26*REGWIDTH(x31)
|
|||
|
|
SREG x27, 27*REGWIDTH(x31)
|
|||
|
|
SREG x28, 28*REGWIDTH(x31)
|
|||
|
|
SREG x29, 29*REGWIDTH(x31)
|
|||
|
|
SREG x30, 30*REGWIDTH(x31)
|
|||
|
|
addi x30, x31, 0 // mv gpr pointer to x30
|
|||
|
|
csrr x31, CSR_MSCRATCH // restore value of x31
|
|||
|
|
SREG x31, 31*REGWIDTH(x30) // store x31
|
|||
|
|
#endif
|
|||
|
|
.endm
|
|||
|
|
|
|||
|
|
|
|||
|
|
.macro RVTEST_DATA_BEGIN
|
|||
|
|
.data
|
|||
|
|
.align 4
|
|||
|
|
.global rvtest_data_begin
|
|||
|
|
rvtest_data_begin:
|
|||
|
|
#ifdef rvtest_mtrap_routine
|
|||
|
|
trapreg_sv:
|
|||
|
|
.fill 7, REGWIDTH, 0xdeadbeef /* handler reg save area, 1 extra wd just in case */
|
|||
|
|
tramptbl_sv: // save area of existing trampoline table
|
|||
|
|
.rept NUM_SPECD_INTCAUSES
|
|||
|
|
J .+0 /* prototype jump instruction, offset to be filled in */
|
|||
|
|
.endr
|
|||
|
|
mtvec_save:
|
|||
|
|
.dword 0 /* save area for incoming mtvec */
|
|||
|
|
mscratch_save:
|
|||
|
|
.dword 0 /* save area for incoming mscratch */
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
.endm
|
|||
|
|
|
|||
|
|
.macro RVTEST_DATA_END
|
|||
|
|
.global rvtest_data_end
|
|||
|
|
rvtest_data_end:
|
|||
|
|
.endm
|
|||
|
|
|
|||
|
|
|
|||
|
|
#define RVTEST_CASE(_PNAME,_DSTR,...)
|
|||
|
|
|
|||
|
|
#define RVTEST_FP_ENABLE()\
|
|||
|
|
LI x2, MSTATUS_FS;\
|
|||
|
|
csrrs x3, mstatus,x0;\
|
|||
|
|
or x2, x3, x2;\
|
|||
|
|
csrrw x0,mstatus,x2;
|
|||
|
|
|
|||
|
|
#define RVTEST_SIGBASE(_R,_TAG) \
|
|||
|
|
LA(_R,_TAG);\
|
|||
|
|
.set offset,0;
|
|||
|
|
|
|||
|
|
.set offset,0;
|
|||
|
|
#define _ARG5(_1ST,_2ND, _3RD,_4TH,_5TH,...) _5TH
|
|||
|
|
#define _ARG4(_1ST,_2ND, _3RD,_4TH,...) _4TH
|
|||
|
|
#define _ARG3(_1ST,_2ND, _3RD, ...) _3RD
|
|||
|
|
#define _ARG2(_1ST,_2ND, ...) _2ND
|
|||
|
|
#define _ARG1(_1ST,...) _1ST
|
|||
|
|
#define NARG(...) _ARG5(__VA_OPT__(__VA_ARGS__,)4,3,2,1,0)
|
|||
|
|
#define RVTEST_SIGUPD(_BR,_R,...)\
|
|||
|
|
.if NARG(__VA_ARGS__) == 1;\
|
|||
|
|
SREG _R,_ARG1(__VA_ARGS__,0)(_BR);\
|
|||
|
|
.set offset,_ARG1(__VA_OPT__(__VA_ARGS__,)0)+REGWIDTH;\
|
|||
|
|
.endif;\
|
|||
|
|
.if NARG(__VA_ARGS__) == 0;\
|
|||
|
|
SREG _R,offset(_BR);\
|
|||
|
|
.set offset,offset+REGWIDTH;\
|
|||
|
|
.endif;
|
|||
|
|
|
|||
|
|
#define RVTEST_SIGUPD_F(_BR,_R,_F,...)\
|
|||
|
|
.if NARG(__VA_ARGS__) == 1;\
|
|||
|
|
FSREG _R,_ARG1(__VA_ARGS__,0)(_BR);\
|
|||
|
|
SREG _F,_ARG1(__VA_ARGS__,0)+REGWIDTH(_BR);\
|
|||
|
|
.set offset,_ARG1(__VA_OPT__(__VA_ARGS__,)0)+(REGWIDTH+REGWIDTH);\
|
|||
|
|
.endif;\
|
|||
|
|
.if NARG(__VA_ARGS__) == 0;\
|
|||
|
|
FSREG _R,offset(_BR);\
|
|||
|
|
SREG _F,offset+REGWIDTH(_BR);\
|
|||
|
|
.set offset,offset+(REGWIDTH+REGWIDTH);\
|
|||
|
|
.endif;
|
|||
|
|
|
|||
|
|
#define RVTEST_SIGUPD_FID(_BR,_R,_F,...)\
|
|||
|
|
.if NARG(__VA_ARGS__) == 1;\
|
|||
|
|
SREG _R,_ARG1(__VA_ARGS__,0)(_BR);\
|
|||
|
|
SREG _F,_ARG1(__VA_ARGS__,0)+REGWIDTH(_BR);\
|
|||
|
|
.set offset,_ARG1(__VA_ARGS__,0)+(2*REGWIDTH);\
|
|||
|
|
.endif;\
|
|||
|
|
.if NARG(__VA_ARGS__) == 0;\
|
|||
|
|
SREG _R,offset(_BR);\
|
|||
|
|
SREG _F,offset+REGWIDTH(_BR);\
|
|||
|
|
.set offset,offset+(2*REGWIDTH);\
|
|||
|
|
.endif;
|
|||
|
|
|
|||
|
|
#define RVTEST_VALBASEUPD(_BR,...)\
|
|||
|
|
.if NARG(__VA_ARGS__) == 0;\
|
|||
|
|
addi _BR,_BR,2040;\
|
|||
|
|
.endif;\
|
|||
|
|
.if NARG(__VA_ARGS__) == 1;\
|
|||
|
|
LA(_BR,_ARG1(__VA_ARGS__,x0));\
|
|||
|
|
.endif;
|
|||
|
|
|
|||
|
|
#define RVTEST_VALBASEMOV(_NR,_BR)\
|
|||
|
|
add _NR, _BR, x0;
|
|||
|
|
/*
|
|||
|
|
* RVTEST_BASEUPD(base reg) - updates the base register the last signature address + REGWIDTH
|
|||
|
|
* RVTEST_BASEUPD(base reg, new reg) - moves value of the next signature region to update into new reg
|
|||
|
|
* The hidden variable offset is reset always
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
#define RVTEST_BASEUPD(_BR,...)\
|
|||
|
|
.if NARG(__VA_ARGS__) == 0;\
|
|||
|
|
addi _BR,_BR,offset;\
|
|||
|
|
.endif;\
|
|||
|
|
.if NARG(__VA_ARGS__) == 1;\
|
|||
|
|
addi _ARG1(__VA_ARGS__,x0),_BR,offset;\
|
|||
|
|
.endif;\
|
|||
|
|
.set offset,0;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
//------------------------------ BORROWED FROM ANDREW's RISC-V TEST MACROS -----------------------//
|
|||
|
|
#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
|
|||
|
|
|
|||
|
|
#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
|
|||
|
|
|
|||
|
|
#define TEST_JALR_OP(tempreg, rd, rs1, imm, swreg, offset,adj) \
|
|||
|
|
5: ;\
|
|||
|
|
LA(rd,5b ) ;\
|
|||
|
|
.if adj & 1 == 1 ;\
|
|||
|
|
LA(rs1, 3f-imm+adj-1 ) ;\
|
|||
|
|
jalr rd, imm+1(rs1) ;\
|
|||
|
|
.else ;\
|
|||
|
|
LA(rs1, 3f-imm+adj) ;\
|
|||
|
|
jalr rd, imm(rs1) ;\
|
|||
|
|
.endif ;\
|
|||
|
|
nop ;\
|
|||
|
|
nop ;\
|
|||
|
|
xori rd,rd, 0x2 ;\
|
|||
|
|
j 4f ;\
|
|||
|
|
;\
|
|||
|
|
3: .if adj & 2 == 2 ;\
|
|||
|
|
.fill 2,1,0x00 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
xori rd,rd, 0x3 ;\
|
|||
|
|
j 4f ;\
|
|||
|
|
.if adj&2 == 2 ;\
|
|||
|
|
.fill 2,1,0x00 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
;\
|
|||
|
|
4: LA(tempreg, 5b ) ;\
|
|||
|
|
andi tempreg,tempreg,~(3) ;\
|
|||
|
|
sub rd,rd,tempreg ;\
|
|||
|
|
RVTEST_SIGUPD(swreg,rd,offset)
|
|||
|
|
//SREG rd, offset(swreg);
|
|||
|
|
|
|||
|
|
#define TEST_JAL_OP(tempreg, rd, imm, label, swreg, offset, adj)\
|
|||
|
|
5: ;\
|
|||
|
|
LA(tempreg, 2f ) ;\
|
|||
|
|
jalr x0,0(tempreg) ;\
|
|||
|
|
6: LA(tempreg, 4f ) ;\
|
|||
|
|
jalr x0,0(tempreg) ;\
|
|||
|
|
1: .if adj & 2 == 2 ;\
|
|||
|
|
.fill 2,1,0x00 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
xori rd,rd, 0x1 ;\
|
|||
|
|
beq x0,x0,6b ;\
|
|||
|
|
.if adj & 2 == 2 ;\
|
|||
|
|
.fill 2,1,0x00 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.if (imm/2) - 2 >= 0 ;\
|
|||
|
|
.set num,(imm/2)-2 ;\
|
|||
|
|
.else ;\
|
|||
|
|
.set num,0 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.if label == 3f ;\
|
|||
|
|
.set num,0 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.rept num ;\
|
|||
|
|
nop ;\
|
|||
|
|
.endr ;\
|
|||
|
|
;\
|
|||
|
|
2: jal rd, label+(adj) ;\
|
|||
|
|
.if adj & 2 == 2 ;\
|
|||
|
|
nop ;\
|
|||
|
|
nop ;\
|
|||
|
|
.endif ;\
|
|||
|
|
xori rd,rd, 0x2 ;\
|
|||
|
|
j 4f ;\
|
|||
|
|
.if (imm/2) - 3 >= 0 ;\
|
|||
|
|
.set num,(imm/2)-3 ;\
|
|||
|
|
.else ;\
|
|||
|
|
.set num,0 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.if label == 1b ;\
|
|||
|
|
.set num,0 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.rept num ;\
|
|||
|
|
nop ;\
|
|||
|
|
.endr ;\
|
|||
|
|
3: .if adj & 2 == 2 ;\
|
|||
|
|
.fill 2,1,0x00 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
xori rd,rd, 0x3 ;\
|
|||
|
|
LA(tempreg, 4f ) ;\
|
|||
|
|
jalr x0,0(tempreg) ;\
|
|||
|
|
.if adj&2 == 2 ;\
|
|||
|
|
.fill 2,1,0x00 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
4: LA(tempreg, 5b ) ;\
|
|||
|
|
andi tempreg,tempreg,~(3) ;\
|
|||
|
|
sub rd,rd,tempreg ;\
|
|||
|
|
RVTEST_SIGUPD(swreg,rd,offset)
|
|||
|
|
//SREG rd, offset(swreg);
|
|||
|
|
|
|||
|
|
#define TEST_BRANCH_OP(inst, tempreg, reg1, reg2, val1, val2, imm, label, swreg, offset,adj) \
|
|||
|
|
LI(reg1, MASK_XLEN(val1)) ;\
|
|||
|
|
LI(reg2, MASK_XLEN(val2)) ;\
|
|||
|
|
addi tempreg,x0,0 ;\
|
|||
|
|
j 2f ;\
|
|||
|
|
;\
|
|||
|
|
1: .if adj & 2 == 2 ;\
|
|||
|
|
.fill 2,1,0x00 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
addi tempreg,tempreg, 0x1 ;\
|
|||
|
|
j 4f ;\
|
|||
|
|
.if adj & 2 == 2 ;\
|
|||
|
|
.fill 2,1,0x00 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.if (imm/2) - 2 >= 0 ;\
|
|||
|
|
.set num,(imm/2)-2 ;\
|
|||
|
|
.else ;\
|
|||
|
|
.set num,0 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.if label == 3f ;\
|
|||
|
|
.set num,0 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.rept num ;\
|
|||
|
|
nop ;\
|
|||
|
|
.endr ;\
|
|||
|
|
;\
|
|||
|
|
2: inst reg1, reg2, label+adj ;\
|
|||
|
|
addi tempreg, tempreg,0x2 ;\
|
|||
|
|
j 4f ;\
|
|||
|
|
.if (imm/4) - 3 >= 0 ;\
|
|||
|
|
.set num,(imm/4)-3 ;\
|
|||
|
|
.else ;\
|
|||
|
|
.set num,0 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.if label == 1b ;\
|
|||
|
|
.set num,0 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.rept num ;\
|
|||
|
|
nop ;\
|
|||
|
|
.endr ;\
|
|||
|
|
;\
|
|||
|
|
3: .if adj & 2 == 2 ;\
|
|||
|
|
.fill 2,1,0x00 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
addi tempreg, tempreg,0x3 ;\
|
|||
|
|
j 4f ;\
|
|||
|
|
.if adj&2 == 2 ;\
|
|||
|
|
.fill 2,1,0x00 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
;\
|
|||
|
|
4: RVTEST_SIGUPD(swreg,tempreg,offset)
|
|||
|
|
//SREG tempreg, offset(swreg);
|
|||
|
|
|
|||
|
|
#define TEST_STORE(swreg,testreg,index,rs1,rs2,rs2_val,imm_val,offset,inst,adj) ;\
|
|||
|
|
LI(rs2,rs2_val) ;\
|
|||
|
|
addi rs1,swreg,offset+adj ;\
|
|||
|
|
LI(testreg,imm_val) ;\
|
|||
|
|
sub rs1,rs1,testreg ;\
|
|||
|
|
inst rs2, imm_val(rs1) ;\
|
|||
|
|
nop ;\
|
|||
|
|
nop
|
|||
|
|
|
|||
|
|
#define TEST_LOAD(swreg,testreg,index,rs1,destreg,imm_val,offset,inst,adj) ;\
|
|||
|
|
LA(rs1,rvtest_data+(index*4)+adj-imm_val) ;\
|
|||
|
|
inst destreg, imm_val(rs1) ;\
|
|||
|
|
nop ;\
|
|||
|
|
nop ;\
|
|||
|
|
RVTEST_SIGUPD(swreg,destreg,offset)
|
|||
|
|
//SREG destreg, offset(swreg);
|
|||
|
|
|
|||
|
|
#define TEST_STORE_F(swreg,testreg,index,rs1,rs2,rs2_val,imm_val,offset,inst,adj,flagreg) ;\
|
|||
|
|
LI(flagreg,rs2_val) ;\
|
|||
|
|
fmv.w.x rs2, flagreg ;\
|
|||
|
|
addi rs1,swreg,offset+adj ;\
|
|||
|
|
LI(testreg,imm_val) ;\
|
|||
|
|
sub rs1,rs1,testreg ;\
|
|||
|
|
inst rs2, imm_val(rs1) ;\
|
|||
|
|
nop ;\
|
|||
|
|
nop ;\
|
|||
|
|
csrrs flagreg, fflags, x0 ;\
|
|||
|
|
RVTEST_SIGUPD(swreg,flagreg,offset)
|
|||
|
|
|
|||
|
|
#define TEST_LOAD_F(swreg,testreg,index,rs1,destreg,imm_val,offset,inst,adj,flagreg) ;\
|
|||
|
|
LA(rs1,rvtest_data+(index*4)+adj-imm_val) ;\
|
|||
|
|
inst destreg, imm_val(rs1) ;\
|
|||
|
|
nop ;\
|
|||
|
|
nop ;\
|
|||
|
|
csrrs flagreg, fflags, x0 ;\
|
|||
|
|
RVTEST_SIGUPD_F(swreg,destreg,flagreg,offset)
|
|||
|
|
|
|||
|
|
#define TEST_CSR_FIELD(ADDRESS,TEMP_REG,MASK_REG,NEG_MASK_REG,VAL,DEST_REG,OFFSET,BASE_REG) \
|
|||
|
|
LI(TEMP_REG,VAL);\
|
|||
|
|
and TEMP_REG,TEMP_REG,MASK_REG;\
|
|||
|
|
csrr DEST_REG,ADDRESS;\
|
|||
|
|
and DEST_REG,DEST_REG,NEG_MASK_REG;\
|
|||
|
|
or TEMP_REG,TEMP_REG,DEST_REG;\
|
|||
|
|
csrw ADDRESS,TEMP_REG;\
|
|||
|
|
csrr DEST_REG,ADDRESS;\
|
|||
|
|
RVTEST_SIGUPD(BASE_REG,DEST_REG,OFFSET)
|
|||
|
|
|
|||
|
|
|
|||
|
|
#define TEST_CASE(testreg, destreg, correctval, swreg, offset, code... ) \
|
|||
|
|
code; \
|
|||
|
|
RVTEST_SIGUPD(swreg,destreg,offset); \
|
|||
|
|
RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)
|
|||
|
|
|
|||
|
|
#define TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, offset, code... ) \
|
|||
|
|
code; \
|
|||
|
|
RVTEST_SIGUPD_F(swreg,destreg,flagreg,offset); \
|
|||
|
|
RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)
|
|||
|
|
|
|||
|
|
#define TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, offset, code... ) \
|
|||
|
|
code; \
|
|||
|
|
RVTEST_SIGUPD_FID(swreg,destreg,flagreg,offset); \
|
|||
|
|
RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)
|
|||
|
|
|
|||
|
|
#define TEST_AUIPC(inst, destreg, correctval, imm, swreg, offset, testreg) \
|
|||
|
|
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
|
|||
|
|
LA testreg, 1f; \
|
|||
|
|
1: \
|
|||
|
|
inst destreg, imm; \
|
|||
|
|
sub destreg, destreg, testreg; \
|
|||
|
|
)
|
|||
|
|
|
|||
|
|
//Tests for a instructions with register-immediate operand
|
|||
|
|
#define TEST_IMM_OP( inst, destreg, reg, correctval, val, imm, swreg, offset, testreg) \
|
|||
|
|
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
|
|||
|
|
LI(reg, MASK_XLEN(val)); \
|
|||
|
|
inst destreg, reg, SEXT_IMM(imm); \
|
|||
|
|
)
|
|||
|
|
|
|||
|
|
//Tests for floating-point instructions with a single register operand
|
|||
|
|
#define TEST_FPSR_OP( inst, destreg, freg, rm, correctval, valaddr_reg, val_offset, flagreg, swreg, offset, testreg) \
|
|||
|
|
TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, offset, \
|
|||
|
|
FLREG freg, val_offset(valaddr_reg); \
|
|||
|
|
csrrwi x0, frm, rm; \
|
|||
|
|
inst destreg, freg; \
|
|||
|
|
csrrs flagreg, fflags, x0; \
|
|||
|
|
)
|
|||
|
|
|
|||
|
|
//Tests for floating-point instructions with a single register operand and integer destination register
|
|||
|
|
#define TEST_FPID_OP( inst, destreg, freg, rm, correctval, valaddr_reg, val_offset, flagreg, swreg, offset, testreg) \
|
|||
|
|
TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, offset, \
|
|||
|
|
FLREG freg, val_offset(valaddr_reg); \
|
|||
|
|
csrrwi x0, frm, rm; \
|
|||
|
|
inst destreg, freg; \
|
|||
|
|
csrrs flagreg, fflags, x0; \
|
|||
|
|
)
|
|||
|
|
|
|||
|
|
//Tests for floating-point instructions with a single register operand and integer operand register
|
|||
|
|
#define TEST_FPIO_OP( inst, destreg, freg, rm, correctval, valaddr_reg, val_offset, flagreg, swreg, offset, testreg) \
|
|||
|
|
TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, offset, \
|
|||
|
|
LREG freg, val_offset(valaddr_reg); \
|
|||
|
|
csrrwi x0, frm, rm; \
|
|||
|
|
inst destreg, freg; \
|
|||
|
|
csrrs flagreg, fflags, x0; \
|
|||
|
|
)
|
|||
|
|
//Tests for a instructions with register-register operand
|
|||
|
|
#define TEST_RRI_OP(inst, destreg, reg1, reg2, imm, correctval, val1, val2, swreg, offset, testreg) \
|
|||
|
|
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
|
|||
|
|
LI(reg1, MASK_XLEN(val1)); \
|
|||
|
|
LI(reg2, MASK_XLEN(val2)); \
|
|||
|
|
inst destreg, reg1, reg2, imm; \
|
|||
|
|
)
|
|||
|
|
|
|||
|
|
//Tests for a instructions with register-register operand
|
|||
|
|
#define TEST_RI_OP(inst, destreg, reg1, reg2, imm, correctval, val1, val2, swreg, offset, testreg) \
|
|||
|
|
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
|
|||
|
|
LI(reg1, MASK_XLEN(val1)); \
|
|||
|
|
LI(reg2, MASK_XLEN(val2)); \
|
|||
|
|
inst destreg, reg1, reg2, imm; \
|
|||
|
|
)
|
|||
|
|
|
|||
|
|
//Tests for a instructions with register-register operand
|
|||
|
|
#define TEST_RR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, testreg) \
|
|||
|
|
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
|
|||
|
|
LI(reg1, MASK_XLEN(val1)); \
|
|||
|
|
LI(reg2, MASK_XLEN(val2)); \
|
|||
|
|
inst destreg, reg1, reg2; \
|
|||
|
|
)
|
|||
|
|
//Tests for floating-point instructions with register-register operand
|
|||
|
|
#define TEST_FPRR_OP(inst, destreg, freg1, freg2, rm, correctval, valaddr_reg, val_offset, flagreg, swreg, offset, testreg) \
|
|||
|
|
TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, offset, \
|
|||
|
|
FLREG freg1, val_offset(valaddr_reg); \
|
|||
|
|
FLREG freg2, val_offset+FREGWIDTH(valaddr_reg); \
|
|||
|
|
csrrwi x0, frm, rm; \
|
|||
|
|
inst destreg, freg1, freg2; \
|
|||
|
|
csrrs flagreg, fflags, x0; \
|
|||
|
|
)
|
|||
|
|
|
|||
|
|
//Tests for floating-point CMP instructions with register-register operand
|
|||
|
|
#define TEST_FCMP_OP(inst, destreg, freg1, freg2, correctval, valaddr_reg, val_offset, flagreg, swreg, offset, testreg) \
|
|||
|
|
TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, offset, \
|
|||
|
|
FLREG freg1, val_offset(valaddr_reg); \
|
|||
|
|
FLREG freg2, val_offset+FREGWIDTH(valaddr_reg); \
|
|||
|
|
inst destreg, freg1, freg2; \
|
|||
|
|
csrrs flagreg, fflags, x0; \
|
|||
|
|
)
|
|||
|
|
|
|||
|
|
//Tests for floating-point R4 type instructions
|
|||
|
|
#define TEST_FPR4_OP(inst, destreg, freg1, freg2, freg3, rm, correctval, valaddr_reg, val_offset, flagreg, swreg, offset, testreg) \
|
|||
|
|
TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, offset, \
|
|||
|
|
FLREG freg1, val_offset(valaddr_reg); \
|
|||
|
|
FLREG freg2, val_offset+FREGWIDTH(valaddr_reg); \
|
|||
|
|
FLREG freg3, val_offset+2*FREGWIDTH(valaddr_reg); \
|
|||
|
|
csrrwi x0, frm, rm; \
|
|||
|
|
inst destreg, freg1, freg2, freg3; \
|
|||
|
|
csrrs flagreg, fflags, x0; \
|
|||
|
|
)
|
|||
|
|
|
|||
|
|
#define TEST_CNOP_OP( inst, testreg, imm_val, swreg, offset) \
|
|||
|
|
TEST_CASE(testreg, x0, 0, swreg, offset, \
|
|||
|
|
inst imm_val; \
|
|||
|
|
)
|
|||
|
|
|
|||
|
|
#define TEST_CMV_OP( inst, destreg, reg, correctval, val2, swreg, offset, testreg) \
|
|||
|
|
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
|
|||
|
|
LI(reg, MASK_XLEN(val2)); \
|
|||
|
|
inst destreg, reg; \
|
|||
|
|
)
|
|||
|
|
|
|||
|
|
#define TEST_CR_OP( inst, destreg, reg, correctval, val1, val2, swreg, offset, testreg) \
|
|||
|
|
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
|
|||
|
|
LI(reg, MASK_XLEN(val2)); \
|
|||
|
|
LI(destreg, MASK_XLEN(val1)); \
|
|||
|
|
inst destreg, reg; \
|
|||
|
|
)
|
|||
|
|
|
|||
|
|
#define TEST_CI_OP( inst, destreg, correctval, val, imm, swreg, offset, testreg) \
|
|||
|
|
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
|
|||
|
|
LI(destreg, MASK_XLEN(val)); \
|
|||
|
|
inst destreg, imm; \
|
|||
|
|
)
|
|||
|
|
|
|||
|
|
#define TEST_CADDI4SPN_OP( inst, destreg, correctval, imm, swreg, offset, testreg) \
|
|||
|
|
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
|
|||
|
|
LI(x2, 0); \
|
|||
|
|
inst destreg, x2,imm; \
|
|||
|
|
)
|
|||
|
|
|
|||
|
|
#define TEST_CBRANCH_OP(inst, tempreg, reg2, val2, imm, label, swreg, offset) \
|
|||
|
|
LI(reg2, MASK_XLEN(val2)) ;\
|
|||
|
|
j 2f ;\
|
|||
|
|
addi tempreg, x0,0 ;\
|
|||
|
|
.option push ;\
|
|||
|
|
.option norvc ;\
|
|||
|
|
1: addi tempreg, tempreg,0x1 ;\
|
|||
|
|
j 4f ;\
|
|||
|
|
.option pop ;\
|
|||
|
|
.if (imm/2) - 4 >= 0 ;\
|
|||
|
|
.set num,(imm/2)-4 ;\
|
|||
|
|
.else ;\
|
|||
|
|
.set num,0 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.if label == 3f ;\
|
|||
|
|
.set num,0 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.rept num ;\
|
|||
|
|
c.nop ;\
|
|||
|
|
.endr ;\
|
|||
|
|
2: inst reg2, label ;\
|
|||
|
|
.option push ;\
|
|||
|
|
.option norvc ;\
|
|||
|
|
addi tempreg, tempreg, 0x2 ;\
|
|||
|
|
j 4f ;\
|
|||
|
|
.option pop ;\
|
|||
|
|
.if (imm/2) - 5 >= 0 ;\
|
|||
|
|
.set num,(imm/2)-5 ;\
|
|||
|
|
.else ;\
|
|||
|
|
.set num,0 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.if label == 1b ;\
|
|||
|
|
.set num,0 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.rept num ;\
|
|||
|
|
c.nop ;\
|
|||
|
|
.endr ;\
|
|||
|
|
;\
|
|||
|
|
3: addi tempreg, tempreg ,0x3 ;\
|
|||
|
|
;\
|
|||
|
|
4: RVTEST_SIGUPD(swreg,tempreg,offset)
|
|||
|
|
//SREG tempreg, offset(swreg);
|
|||
|
|
|
|||
|
|
|
|||
|
|
#define TEST_CJ_OP(inst, tempreg, imm, label, swreg, offset) \
|
|||
|
|
.option push ;\
|
|||
|
|
.option norvc ;\
|
|||
|
|
j 2f ;\
|
|||
|
|
addi tempreg,x0,0 ;\
|
|||
|
|
1: addi tempreg, tempreg,0x1 ;\
|
|||
|
|
j 4f ;\
|
|||
|
|
.option pop ;\
|
|||
|
|
.if (imm/2) - 4 >= 0 ;\
|
|||
|
|
.set num,(imm/2)-4 ;\
|
|||
|
|
.else ;\
|
|||
|
|
.set num,0 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.if label == 3f ;\
|
|||
|
|
.set num,0 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.rept num ;\
|
|||
|
|
c.nop ;\
|
|||
|
|
.endr ;\
|
|||
|
|
2: inst label ;\
|
|||
|
|
.option push ;\
|
|||
|
|
.option norvc ;\
|
|||
|
|
addi tempreg, tempreg, 0x2 ;\
|
|||
|
|
j 4f ;\
|
|||
|
|
.option pop ;\
|
|||
|
|
.if (imm/2) - 5 >= 0 ;\
|
|||
|
|
.set num,(imm/2)-5 ;\
|
|||
|
|
.else ;\
|
|||
|
|
.set num,0 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.if label == 1b ;\
|
|||
|
|
.set num,0 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.rept num ;\
|
|||
|
|
c.nop ;\
|
|||
|
|
.endr ;\
|
|||
|
|
;\
|
|||
|
|
3: addi tempreg, tempreg, 0x3 ;\
|
|||
|
|
;\
|
|||
|
|
4: RVTEST_SIGUPD(swreg,tempreg,offset)
|
|||
|
|
//SREG tempreg, offset(swreg);
|
|||
|
|
|
|||
|
|
#define TEST_CJAL_OP(inst, tempreg, imm, label, swreg, offset) \
|
|||
|
|
5: ;\
|
|||
|
|
j 2f ;\
|
|||
|
|
;\
|
|||
|
|
.option push ;\
|
|||
|
|
.option norvc ;\
|
|||
|
|
1: xori x1,x1, 0x1 ;\
|
|||
|
|
j 4f ;\
|
|||
|
|
.option pop ;\
|
|||
|
|
.if (imm/2) - 4 >= 0 ;\
|
|||
|
|
.set num,(imm/2)-4 ;\
|
|||
|
|
.else ;\
|
|||
|
|
.set num,0 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.if label == 3f ;\
|
|||
|
|
.set num,0 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.rept num ;\
|
|||
|
|
c.nop ;\
|
|||
|
|
.endr ;\
|
|||
|
|
2: inst label ;\
|
|||
|
|
.option push ;\
|
|||
|
|
.option norvc ;\
|
|||
|
|
xori x1,x1, 0x2 ;\
|
|||
|
|
j 4f ;\
|
|||
|
|
.option pop ;\
|
|||
|
|
.if (imm/2) - 5 >= 0 ;\
|
|||
|
|
.set num,(imm/2)-5 ;\
|
|||
|
|
.else ;\
|
|||
|
|
.set num,0 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.if label == 1b ;\
|
|||
|
|
.set num,0 ;\
|
|||
|
|
.endif ;\
|
|||
|
|
.rept num ;\
|
|||
|
|
c.nop ;\
|
|||
|
|
.endr ;\
|
|||
|
|
;\
|
|||
|
|
3: xori x1,x1, 0x3 ;\
|
|||
|
|
;\
|
|||
|
|
4: LA(tempreg, 5b) ;\
|
|||
|
|
andi tempreg,tempreg,~(3) ;\
|
|||
|
|
sub x1,x1,tempreg ;\
|
|||
|
|
RVTEST_SIGUPD(swreg,x1,offset)
|
|||
|
|
//SREG x1, offset(swreg);
|
|||
|
|
|
|||
|
|
#define TEST_CJR_OP(tempreg, rs1, swreg, offset) \
|
|||
|
|
5: ;\
|
|||
|
|
LA(rs1, 3f) ;\
|
|||
|
|
;\
|
|||
|
|
2: c.jr rs1 ;\
|
|||
|
|
xori rs1,rs1, 0x2 ;\
|
|||
|
|
j 4f ;\
|
|||
|
|
;\
|
|||
|
|
3: xori rs1,rs1, 0x3 ;\
|
|||
|
|
;\
|
|||
|
|
4: LA(tempreg, 5b) ;\
|
|||
|
|
andi tempreg,tempreg,~(3) ;\
|
|||
|
|
sub rs1,rs1,tempreg ;\
|
|||
|
|
RVTEST_SIGUPD(swreg,rs1,offset)
|
|||
|
|
//SREG rs1, offset(swreg);
|
|||
|
|
|
|||
|
|
#define TEST_CJALR_OP(tempreg, rs1, swreg, offset) \
|
|||
|
|
5: ;\
|
|||
|
|
LA(rs1, 3f ) ;\
|
|||
|
|
;\
|
|||
|
|
2: c.jalr rs1 ;\
|
|||
|
|
xori x1,x1, 0x2 ;\
|
|||
|
|
j 4f ;\
|
|||
|
|
;\
|
|||
|
|
3: xori x1,x1, 0x3 ;\
|
|||
|
|
;\
|
|||
|
|
4: LA(tempreg, 5b ) ;\
|
|||
|
|
andi tempreg,tempreg,~(3) ;\
|
|||
|
|
sub x1,x1,tempreg ;\
|
|||
|
|
RVTEST_SIGUPD(swreg,x1,offset)
|
|||
|
|
//SREG x1, offset(swreg);
|
|||
|
|
|
|||
|
|
|
|||
|
|
//--------------------------------- Migration aliases ------------------------------------------
|
|||
|
|
#ifdef RV_COMPLIANCE_RV32M
|
|||
|
|
#warning "RV_COMPLIANCE_RV32M macro will be deprecated."
|
|||
|
|
#define RVMODEL_BOOT \
|
|||
|
|
RVTEST_IO_INIT; \
|
|||
|
|
RV_COMPLIANCE_RV32M ; \
|
|||
|
|
RV_COMPLIANCE_CODE_BEGIN
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
#define SWSIG(a, b)
|
|||
|
|
|
|||
|
|
#ifdef RV_COMPLIANCE_DATA_BEGIN
|
|||
|
|
#warning "RV_COMPLIANCE_DATA_BEGIN macro deprecated in v0.2. Please use RVMODEL_DATA_BEGIN instead"
|
|||
|
|
#define RVMODEL_DATA_BEGIN \
|
|||
|
|
RV_COMPLIANCE_DATA_BEGIN
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
#ifdef RV_COMPLIANCE_DATA_END
|
|||
|
|
#warning "RV_COMPLIANCE_DATA_END macro deprecated in v0.2. Please use RVMODEL_DATA_END instead"
|
|||
|
|
#define RVMODEL_DATA_END \
|
|||
|
|
RV_COMPLIANCE_DATA_END
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
#ifdef RV_COMPLIANCE_HALT
|
|||
|
|
#warning "RV_COMPLIANCE_HALT macro deprecated in v0.2. Please use RVMODEL_HALT instead"
|
|||
|
|
#define RVMODEL_HALT \
|
|||
|
|
RV_COMPLIANCE_HALT
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
#ifdef RVTEST_IO_ASSERT_GPR_EQ
|
|||
|
|
#warning "RVTEST_IO_ASSERT_GPR_EQ macro deprecated in v0.2. Please use RVMODEL_IO_ASSERT_GPR_EQ instead"
|
|||
|
|
#define RVMODEL_IO_ASSERT_GPR_EQ(_SP, _R, _I) \
|
|||
|
|
RVTEST_IO_ASSERT_GPR_EQ(_SP,_R, _I)
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
#ifdef RVTEST_IO_WRITE_STR
|
|||
|
|
#warning "RVTEST_IO_WRITE_STR macro deprecated in v0.2. Please use RVMODEL_IO_WRITE_STR instead"
|
|||
|
|
#define RVMODEL_IO_WRITE_STR(_SP, _STR) \
|
|||
|
|
RVTEST_IO_WRITE_STR(_SP, _STR)
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
#ifdef RVTEST_IO_INIT
|
|||
|
|
#warning "RVTEST_IO_INIT is deprecated in v0.2. Please use RVMODEL_BOOT for initialization"
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
#ifdef RVTEST_IO_CHECK
|
|||
|
|
#warning "RVTEST_IO_CHECK is deprecated in v0.2.
|
|||
|
|
#endif
|